8 results about "Simd processing" patented technology

Disclosed are techniques for post-quantum encrypted trusted execution environments on edge devices. An edge computing device includes a trusted execution environment that encompasses at least some SIMD processing units such as Graphics Processing Units (GPUs). A data record, such as machine learning inferences from a machine learning or artificial intelligence model, is generated on the edge computing device within the trusted execution environment and encrypted with post-quantum encryption (such as lattice based encryption) using SIMD processing units in the trusted execution environment. Workloads received for the trusted execution environment, also encrypted with post-quantum encryption, are decrypted using the SIMD processing units in the trusted execution environment.

A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.

This application discloses a data processing apparatus, a data processing method, a chip, and an electronic device, relating to the field of data processing technology. The data processing apparatus includes: a storage module configured to store x sets of original data vectors, each original data vector containing m data elements, where x and m are positive integers; and a computation module including a single instruction multiple data (SIMD) execution unit and a vector register group, the SIMD execution unit being coupled to the vector register group, and the vector register group being coupled to the storage module. The computation module is configured to: determine whether x is an integer multiple of the SIMD processing capability, split x, and obtain the top-k data elements in the original data vectors based on different data strategies. The algorithm of this application is flexible, requires no dedicated hardware sorting network, avoids dependence on dedicated hardware, and improves programming flexibility and versatility, facilitating the expansion and migration of large models across different hardware platforms.

A SIMD processing unit processes a plurality of tasks which each include up to a predetermined maximum number of work items. The work items of a task are arranged for executing a common sequence of instructions on respective data items. The data items are arranged into blocks, with some of the blocks including at least one invalid data item. Work items which relate to invalid data items are invalid work items. The SIMD processing unit comprises a group of processing lanes configured to execute instructions of work items of a particular task over a plurality of processing cycles. A control module assembles work items into the tasks based on the validity of the work items, so that invalid work items of the particular task are temporally aligned across the processing lanes. In this way the number of wasted processing slots due to invalid work items may be reduced.

The invention provides a design method based on floating point feature map format conversion. The method comprises the following steps: S1, designing the number of rows processed each time; s2, converting a simd processing format; and S3, specific implementation steps based on Oram. The method comprises the following steps: firstly, carrying data from a ddr storage to an oam through a dma instruction, carrying out format conversion on the data in the oam, storing the converted data in the oam, and finally carrying the data from the oam storage to the ddr by using the dma instruction. Through the method, the processing speed is increased, and the time is shortened.

The present application discloses a computing system and an associated method. The computing system includes a memory, a master computing device and a slave computing device. The master computing device includes a memory controller and an input-output memory management unit (IOMMU). When the slave computing device accesses a first virtual address, and a first translation lookaside buffer (TLB) of the slave computing device does not store the first virtual address, the first TLB sends a translation request to the IOMMU. The IOMMU traverses page tables of the memory controller to obtain a first physical address corresponding to the first virtual address, selects and clears a first virtual address entry from a second TLB of the computing system according to a recent use time and a dependent workload of each virtual address entry to store the first virtual address and the first physical address.

An apparatus has processing circuitry to perform single instruction multiple data (SIMD) processing on an array having a plurality of data items, and the processing circuitry supports the SIMD processing for multiple array sizes. The processing circuitry is capable of selecting an array size for performing the SIMD processing based on SIMD processing configuration information. Diagnostic information collection circuitry is provided to collect diagnostic information about software executing on the processing circuitry, and the diagnostic information collection circuitry screens the collection of the diagnostic information based on the SIMD processing configuration information.

A cache system in a graphics processing system stores graphics data items for use in rendering primitives. It is determined whether graphics data items relating to primitives to be rendered are present in the cache, and if not then computation instances for generating the graphics data items are created. Computation instances are allocated to tasks using a task assembly unit which stores task entries for respective tasks. The task entries indicate which computation instances have been allocated to the respective tasks. The task entries are associated with characteristics of computation instances which can be allocated to the respective tasks. A computation instance to be executed is allocated to a task based on the characteristics of the computation instance. SIMD processing logic executes computation instances of a task outputted from the task assembly unit to thereby determine graphics data items, which can be used to render the primitives.