356 results about "Register bank" patented technology

The invention provides a collaborative computing method, system and device based on SIMD and SIMT, and belongs to the technical field of computer processing. The method is applied to a Warp composed of a plurality of SPs, and the Warp comprises an SIMT front end and an SIMD rear end. Each SP corresponds to a vector register combined by a plurality of short registers; generating instruction fetching indication information under the condition that a thread bundle scheduler at the front end of the SIMT determines that a first thread bundle corresponding to the calculation task is in an activated state; obtaining a first cache instruction corresponding to the first thread bundle through an instruction fetching unit, and sending the first cache instruction to a decoding unit at the front end of the SIMT for analysis; obtaining one or more corresponding required operands through an operand collection unit at the rear end of the SIMD; and distributing the required operands to the corresponding calculation management units through the SIMD rear end to execute the corresponding calculation tasks, and writing the calculation results corresponding to the calculation tasks back to the storage unit through the write-back unit.

The invention discloses an attention mechanism calculation method and device, a storage medium and a product, and the method comprises the steps: carrying out matrix multiplication operation through employing a query matrix block of a first register block and a key matrix block of a shared memory, obtaining a first product matrix block, and writing the first product matrix block into a second register block; performing exponential operation by using the first product matrix blocks to obtain sub-matrix blocks, writing the sub-matrix blocks into a second register block in a covering manner, and writing the sub-matrix blocks into a third register block in the form of a target precision type; performing matrix multiplication operation by using the sub-matrix blocks of the third register block and the value matrix blocks of the shared memory to obtain second product matrix blocks, and writing the second product matrix blocks into a second register block; performing softmax operation by using the second product matrix blocks to obtain attention result matrix blocks, and writing the attention result matrix blocks into a fourth register block; and writing the attention result matrix of the fourth register group into the shared memory in blocks. According to the embodiment of the invention, overflow of the register can be avoided, and the utilization of hardware resources is maximized.

The invention discloses an attention calculation implementation method and device, a medium, equipment and a product, and the method comprises the steps: loading the current to-be-calculated ith query block from a shared memory to a first register group of a consumer thread group, and carrying out the internal splitting calculation of the query block and a key block, so as to obtain corresponding attention score blocks; sequentially obtaining MK attention score blocks, and executing attention fusion calculation of mixing precision with the corresponding value blocks to obtain an attention output block corresponding to the ith query block; and after the attention output blocks are logically divided into N2 batches, a specified register group for storing target precision type data in the fusion calculation process is multiplexed and executed according to batches, target precision type conversion is carried out, and an output result after conversion of each batch is written back to a shared memory. According to the method, the existing hardware resources can be efficiently utilized to improve the calculation performance, and the method is particularly suitable for large-size query block and key block scenes.

The invention discloses a depth operation implementation method and device for parallel pixels in the vertical direction, a medium, equipment and a product. The method comprises the following steps: mapping each channel group with a thread bundle containing NT threads; acquiring jumping step length of vertical direction access and parameter configuration of a sliding window operator; performing register resource allocation for each thread to form a sliding window data cache region; determining NH row starting point coordinates of the current scanning round; when the current scanning round is executed, in each column slice participating in calculation, pixel groups at NT row and column positions are scanned from each row starting point coordinate with the jump step length as the span, and the pixel groups are loaded to register groups of all threads in corresponding thread bundles in sequence, so that each thread can process the calculation task of the corresponding local sliding window view. According to the method, thread-level independent calculation task allocation is realized through a pixel parallel strategy among threads, and allocated hardware resources can be utilized to the maximum extent.

The invention discloses a server slot resource allocation system and method, a server, equipment and a medium, and relates to the technical field of servers, the system comprises at least one physical slot of the server, a register component and a firmware component, the register component comprises a first register and a second register, the first register is used for storing a global identifier of a physical slot position, determining a resource allocation mode of the physical slot position, configuring a second register at each physical slot position to store a resource allocation parameter of the physical slot position, and reading the first register and the second register by utilizing a firmware component after the server is powered on, according to the resource allocation mode and the resource allocation parameters, resources are allocated to at least one physical slot, on-demand allocation and safe management and control of the resources are achieved, the method is not limited by the slots, the technical problems of resource waste and slot limitation caused by static allocation in related technologies are solved, and the resource allocation efficiency is improved. The technical effects of dynamically allocating resources, remarkably improving the resource utilization rate and deployment flexibility and the like are achieved.

The invention provides a multi-thread beam debugging method and device and an artificial intelligence chip, and relates to the technical field of artificial intelligence, and the method comprises the steps: determining an expected thread beam to trigger debugging based on a comparison result of instruction information of executing an original program by each thread beam and instruction information stored in a target register group, and a thread beam identifier of each thread beam; sending debugging trigger information to a processor to enable the processor to send debugging enabling information to each thread bundle, and controlling the unexpected thread bundle to wait for the expected thread bundle to be debugged; based on the debugging enabling information, controlling the expected thread bundle to execute the debugging program based on an instruction address of the debugging program stored in the target register group; and sending debugging ending information to the processor to enable the processor to send debugging stopping information to each thread bundle, and controlling each thread bundle to continue to execute the original program. According to the method and the device provided by the invention, the debugging aiming at the specific thread beam can be realized in the multi-thread beam parallel computing process.

The invention discloses a pixel parallel depth operation implementation method and device, a medium, equipment and a product, and the method comprises the steps: dividing an input tensor into m channel groups, and distributing the channel groups to a thread bundle containing NT threads for independent processing; obtaining the number of elements, participating in coverage operation, of a sliding window operator in a two-dimensional plane, a sliding step length and row and column starting point coordinates of initial coverage of each element; allocating register groups with the same number as the elements for each thread; each register group is used for storing a pixel group of a corresponding element; in the channel group, NT row and column positions are scanned by rows from each row and column starting point coordinate according to the sliding step length, and corresponding pixel groups are loaded to register groups of corresponding threads in sequence, so that each thread can process a calculation task of a local sliding window view. According to the method, thread-level independent calculation task allocation is realized through a pixel parallel strategy among threads, and allocated hardware resources can be utilized to the maximum extent.

The embodiment of the invention discloses a cross-level gating conversion method and device, equipment and a storage medium, and the method comprises the steps: obtaining a target gating circuit diagram; identifying a connection relationship between devices in the target gating circuit diagram, and determining at least one clock path according to the connection relationship; wherein the clock path is used for representing a signal transmission path from the register to the top port; compiling a device in the clock path into a corresponding integrated unit so as to complete a conversion process of the target gating circuit diagram; wherein the integrated unit represents a device set composed of at least one register. According to the technical scheme, the clock paths in the circuit diagram can be automatically recognized, the devices in the clock paths are compiled into the corresponding integrated units, a large number of fan-out devices do not need to be processed in the conversion process, the logic copy amount is reduced, system resource consumption is reduced, and the device compiling efficiency is improved by conducting device compiling based on the clock paths. Original hierarchical structures between devices can be retained.

The invention provides a universal Transform acceleration method and system based on floating point instruction set extension, and the method comprises the steps: constructing a multiplier which comprises a plurality of stages of adders and a 4-Booth coding algorithm which are connected in sequence, and coding data; the coded data is operated through a plurality of stages of adders in sequence to obtain the output of a multiplier; the construction of the floating-point number register comprises the following specific steps: adding a floating-point number register group, generating the floating-point number register group, enabling input result register indexes to correspond to respective register numbers by writing port logic of the floating-point number register group, generating a writing enable signal, writing data into the register by an enabled general register, and writing the data into the floating-point number register group. The read port is realized by using a multi-path parallel selector, and a selection signal of the multi-path parallel selector is an index of a read operand register; and the RISC-V processor accelerates the operation of the Transform neural network based on the constructed multiplier and the floating-point number register.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention discloses a control circuit of a serial port transceiver circuit and a clock synchronization method, and belongs to the technical field of data communication. The circuit comprises a clock synchronization circuit and a register value generation circuit, wherein the output end of the register value generation circuit is connected with the first input end of a first selector in a transceiver circuit; the clock synchronization circuit outputs a reference clock rising edge according to the received slow reference clock; the register value generation circuit counts a main clock based on the rising edge of the reference clock and outputs a self-adaptive baud rate count value; the first selector selects the self-adaptive baud rate count value and a configuration signal of the register block and outputs a selection signal; and the transceiving module drives data transceiving with the register group according to the clock corresponding to the selection signal so as to adjust the main clock. According to the circuit, the influence of the deviation between the preset value and the actual value on the communication precision can be reduced under the condition that the main clock of the equipment is unstable.

The invention discloses an interrupt register processing method and device, a product, equipment and a medium. The method comprises the steps that configuration information and input signal indication information of an interrupt register set to be verified are acquired; the configuration information comprises working attribute information, and the working attribute information indicates working logic of the interrupt register block; the input signal indication information indicates whether the interrupt register group has an input signal; generating a reference output result of the interrupt register block based on the input signal indication information and the working attribute information; obtaining a target output result of the interrupt register block; the target output result is a result output when the interrupt register group executes work according to the corresponding work logic under the condition that the interrupt register group is indicated by the input signal indication information; and generating a target verification result of the interrupt register block based on the matching between the target output result and the reference output result. By adopting the method and the device, the verification efficiency and verification accuracy of the interrupt register block can be improved.

The invention discloses an instruction conversion context switching optimization method based on stack frame hierarchical compression, which comprises the following steps of: loading and executing an executable file in a dynamic instruction conversion mode, and establishing a storage instruction set and a recovery instruction set containing a context switching complete process for context switching related instructions; constructing a register group according to the association degree of registers in the storage instruction set so as to realize the combined storage of register data by adopting a continuous memory space in the ARM architecture, and carrying out hierarchical compression on push data according to a function call hierarchical structure, recovery of the register data and the stack pressing data is achieved in the recovery instruction set according to the mapping relation table and the incidence relation table recorded in the storage process, the flexibility of processing a complex nested structure and a data type is improved, and correct execution of a program is ensured.

The present application relates to a data processing method and device based on a low-power multi-core processor. The method includes: the multi-core processor data is configured through a network configuration register group, and the register group sends an enable instruction to a data selector to start data transmission. After receiving the enable instruction, the data selector obtains the multi-core processor data and determines the first data involved in the reduction. The first data is stored in the FIFO register group according to the address of the multi-core processor to obtain storage information. The control unit performs a reduction operation on the first data according to the storage information to obtain a multi-core data processing result, and sends the multi-core data processing result to a shared memory after being processed by an operation unit. The use of this method can reduce the memory access power consumption and delay in the reduction operation without changing the instruction set.

The invention discloses an attention mechanism calculation method and device, a storage medium and a product, and the method comprises the steps: carrying out the matrix multiplication operation of a query matrix block and a key matrix block, obtaining a first product matrix block of a first precision type, writing the first product matrix block into a second register group, and then carrying out the index operation, and obtaining a molecular matrix block; writing the quantized sub-matrix blocks into a third register block according to a second precision type; writing the sub-matrix blocks into a fourth register block according to a third precision type, and performing layout conversion through a shared memory; performing softmax operation by using the molecular matrix blocks and the value matrix blocks after layout conversion to obtain attention result matrix blocks of a first precision type, and writing the attention result matrix blocks into a fifth register block; and writing the attention result matrix blocks into the shared memory according to the third precision type. The embodiment of the invention can reduce the accumulative error of the intermediate operation result.

The embodiment of the invention provides a polynomial calculation method and device, and the method comprises the steps: obtaining a plurality of to-be-calculated polynomials in a polynomial calculation application, dividing the plurality of to-be-calculated polynomials, obtaining a plurality of to-be-calculated groups, and enabling the plurality of to-be-calculated groups to comprise a first to-be-calculated group and a second to-be-calculated group; loading a common variable corresponding to at least one to-be-calculated polynomial in the first to-be-calculated group to at least one first register group, loading a variable coefficient to at least one second register group, and loading a reference variable to at least one third register group, and controlling common variables in the at least one first register group and variable coefficients in the at least one second register group to perform outer product calculation to obtain a first result, and controlling the first result and reference variables in the at least one third register group to perform inner product calculation to obtain a second result. By means of the method, polynomial calculation can be converted into matrix calculation between the register blocks, and the calculation speed is increased.

The invention provides a memory access system oriented to vector and matrix calculation, the system comprises a vector memory access unit, a matrix memory access unit, a vector register group and a matrix register group, the vector memory access unit is connected with a memory interface and the vector register group, reads elements of a one-dimensional data structure or a two-dimensional data structure from a memory, and stores the elements of the one-dimensional data structure or the two-dimensional data structure; vector data are generated through data reorganization operation, a matrix access unit is connected with a memory interface and a matrix register set, matrix block data of a two-dimensional data structure are read from a memory together with the matrix access unit, matrix data are generated after data reorganization, and the matrix data are broadcasted to one or more computing units according to rows or columns. And performing calculation on the matrix data and the vector data. In the memory access system, the vector memory access unit and the matrix memory access unit can load data in parallel, and the utilization rate is improved through a plurality of computing units, so that the problems of low memory access efficiency and low memory bandwidth utilization rate are solved.

The embodiment of the present invention discloses a data caching method, device, electronic device, storage medium and program, which are applied to a cache component, and the cache component is configured with a target register group, wherein the method includes: receiving a data access request sent by a target processor; determining the type of the data access request according to the configuration information of the target register group; replacing the current cached data with the target data requested to be accessed by the data access request according to the type of the data access request and the configuration information of the target register group; wherein the target register group is configured with multiple registers, each of which is used to store the configuration information of a persistent data address window. The technical solution of the embodiment of the present invention realizes a highly fair data caching strategy that supports data persistence, enriches the data caching function, and reduces the requirements for software and hardware resources in the data caching process.

The invention discloses a storage resource allocation method and device, a computing device and a storage medium. The storage resource allocation method is used for allocation of shared registers in a processor and comprises the steps that a discontinuous register block list is added into an available register block list, the discontinuous register block list comprises a plurality of discontinuous register blocks with the interval step length being M, and M is a positive integer larger than 1; in response to an allocation request that the current instruction occupies K discontinuous registers, allocating a discontinuous register group to the current instruction, K being a positive integer greater than 1; and updating the state of the distributed discontinuous register block in the discontinuous register block list. According to the storage resource allocation method, the utilization rate of the register can be improved, so that the number of synchronously executed threads is increased, and the program execution parallelism is improved.

The invention discloses a device and a method for realizing a register block shared by a general-purpose computing core and a tensor core, a tensor core read request unit sends a read request and stores the read request in a tensor core read request queue, and a life cycle counter and a clock cycle counter are triggered to start counting; the life cycle counter records life cycle values of read requests in the tensor core read request queue; the tensor core read request scheduler transmits a to-be-executed read request to the register block when the life cycle value of the to-be-executed read request reaches a preset value, so as to read a tensor core operand from the register block and store the tensor core operand in a tensor core operand cache; the priority of the general calculation core is higher than that of the tensor core before the life cycle value of the to-be-executed read request reaches a preset value; the clock period counter triggers the tensor core operand cache to send the tensor core operand to the tensor core execution unit when the count value reaches a preset trigger value. According to the invention, the read bandwidth of the register block can be utilized to the maximum extent, and the overall performance is effectively improved.

The invention provides a task scheduling method, a task scheduling device and electronic equipment, and aims to solve the problem that the real-time performance of a system can be improved while the load of a CPU (Central Processing Unit) is increased by accelerating the interruption period of the system. The task scheduling method comprises the steps that a special register block is configured for each created task, and the special register block is used for dynamically storing scheduling parameters of the tasks; updating the expiration times of the tasks according to the system reference time through hardware logic; generating a ready state of the task based on the expiration times and the task type through hardware logic; the priorities and the ready states of all the tasks are compared through hardware logic, and the ready task with the highest priority is screened out; and comparing the priority of the ready task with the highest priority with the priority of the currently executed task through hardware logic, and when the priority of the ready task with the highest priority is higher than that of the currently executed task, triggering task switching interruption to an operating system, so that the operating system performs task switching according to the information of the ready task with the highest priority.

The invention provides an FIFO (First In First Out) data reading method, device, system, equipment and medium, the method comprises the following steps: when a data reading request is triggered, calculating a read address according to a data reading address carried in the data reading request; the read address is used for representing a value when the read address register is about to be updated in the previous clock period; selecting target data from the next beat of data of the register file or the beat-to-write data through the multiplexer according to the beat-to-read address; the next beat of data of the register file refers to data stored in the register file in the next clock period; the current data are data which are currently written into a first-in first-out (FIFO) queue; and performing a beating operation on the target data through a register, and performing a reading operation through a data reading interface of the FIFO queue. According to the scheme, the overall delay of data reading is reduced, the running speed and performance of the whole system are improved, and then the running speed of a chip is increased.

The invention discloses a data processing device, a data processing method, a chip and electronic equipment, and relates to the technical field of data processing. The data processing device comprises a storage module which is configured to store x groups of original data vectors, the original data vectors comprise m data elements, and x and m are positive integers; the calculation module is configured to access the original data vectors stored in the storage module, and reconstruct the x groups of original data vectors into one or more intermediate matrixes according to the parallel processing capability of the single-instruction multi-data execution unit and a target value k of a Top-k operator; loading the intermediate matrix into a vector register block according to columns, carrying out odd-even merging sorting by utilizing a single-instruction multi-data execution unit, and realizing in-line sorting on the intermediate matrix; and loading the intermediate matrix subjected to in-line sorting into a vector register block according to columns, and performing one or more rounds of merging sorting by utilizing a single-instruction multi-data execution unit to obtain top-k data elements in x groups of original data vectors.

The invention provides an AXI bus monitoring system and method, the system comprises a host side monitor, a slave side monitor and an error summarization processing module, and the error summarization processing module is respectively connected with the host side monitor and the slave side monitor; a plurality of register groups are arranged in each monitor, and each register group corresponds to one timer and one state machine and is used for monitoring one read or write transaction; the timer is used for carrying out timeout counting on the read / write transaction, and when the count exceeds a preset value, a timeout error is triggered to be reported to the error summarization processing module; the state machine is used for tracking which stage the read or write transaction is performed in real time; the register block is used for latching an AXI bus signal so that a monitor constructs data to complete access; and the error summarization processing module is used for executing corresponding processing according to the error codes reported by the host side monitor and / or the slave side monitor and the information latched by the register block. The system can effectively avoid system deadlock.

The invention provides a matrix multiplication operation method and device and a matrix transposition operation method and device of a processor. The matrix multiplication operation method of the processor comprises the following steps: taking a first matrix of which the storage sequence is inconsistent with the loading sequence for carrying out element-by-element multiplication operation as a second matrix, loading the second matrix through a register set in the processor, and dividing the second matrix into a plurality of third matrixes, replacing elements in a plurality of nth register groups included in the register set; for each nth register group, reading elements in the nth register group according to an alternating sequence of the elements of the first register and the elements of the second register through the (n + 1) th register group; when iteration is carried out for n to N-1, the obtained sixth matrix is stored in the memory; and performing element-by-element multiplication and accumulation on the elements at each position of the first matrix and the sixth matrix. According to the invention, the time required by matrix multiplication operation can be reduced.

The invention provides an RISC-V tensor instruction set extension method based on an intelligent processor. The method comprises the steps that a special tensor configuration register set is introduced to store tensor element information and operation element information; encoding a tensor extension instruction by adopting a 64-bit fixed-length instruction encoding format; and setting high-capacity on-chip tight coupling storage with uniform addressing in a processor core, and taking the high-capacity on-chip tight coupling storage as a direct operation space of all tensor expansion instructions. The invention further provides an intelligent processor-based RISC-V tensor instruction set extension device, a storage medium and electronic equipment. According to the method, the RISC-V tensor instruction set extension which supports high-dimensional tensor operation, is dense in calculation and is friendly to hardware can be realized.

The invention relates to the technical field of processor function verification, in particular to a processor architecture verification method, which comprises the following steps of: based on architecture description document information, analyzing an instruction name, an operand attribute and a register state, screening instruction set structure information according to an operand definition rule through an architecture document, judging the availability of register calling, and verifying the processor architecture. And screening the register combination meeting the architecture description rule to obtain instruction set architecture data. According to the method, the framework description document information is analyzed, effective application of framework description rules is ensured, test codes are more targeted, verification effectiveness is improved, instruction combinations which cannot be logically executed are eliminated, coverage rate calculation precision is optimized, and invalid test data interference is reduced; through improvement of instruction analysis, accessibility analysis, coverage rate optimization, execution adjustment and the like, it is ensured that the execution condition of an instruction set is comprehensively evaluated, the test efficiency is improved, and the completeness and reliability of processor verification are enhanced.

The invention provides an artificial intelligence chip and a collaborative thread bundle calculation method. The cooperative thread bundle calculation method comprises the following steps of: initializing a plurality of thread bundle units by a thread bundle resource allocation unit, so that the plurality of thread bundle units have the same initial vector register base address to form a group of cooperative thread bundles; the thread beam resource allocation unit notifies a thread beam scheduling and instruction transmitting unit to send a plurality of execution instructions to an execution unit; running a plurality of thread bundles of the plurality of thread bundle units by the execution unit according to the plurality of execution instructions; reading different scalar parameters from the respective scalar registers of the plurality of thread bundle units by the plurality of thread bundles; and accessing, by the plurality of thread bundles, the same register space of the vector register according to the same initial vector register base address. According to the artificial intelligence chip and the cooperative thread beam calculation method, the efficient cooperative thread beam calculation function of the cross-thread beam sharing vector register block can be achieved.

The invention provides a large language model operator compiling method oriented to a GPU platform, and belongs to the field of GPU operator compilation. A large language model operator is compiled through a Python interface to obtain a Python code; performing lexical analysis and grammatical analysis on the Python code to generate an abstract syntax tree; mapping the abstract syntax tree into an MMIR extension intermediate representation; tensor layout in the MLIR extension intermediate representation is uniformly converted into a binary linear mapping matrix, and optimization problems of global memory layout, shared memory layout and register block layout are analyzed based on the binary linear mapping matrix; automatically deducing a non-key tensor layout based on a program control flow diagram, generating a global optimal layout scheme, and obtaining an optimized MMIR extension intermediate representation; enabling the optimized MLIR extension intermediate representation to pass through a GGPU (Graphics Graphics Processing Unit) target code generator of the MLIR, and generating a PTX code adaptive to the NVIDIA GPU; the PTX code is loaded to a GPU, and an operator calculation result is output; the invention further provides a compiling system. The problem that the current large language model operator compiling efficiency is low is solved.

A method for obtaining a row hammer refresh address, including: after a row hammer refresh signal arrives, obtaining a current sampling address, and determining whether a high address is locked in a current row hammer refresh cycle; in response to the high address being locked, determining whether a high address of the current sampling address is identical to the locked high address; in response to being identical, updating an access frequency of the locked high address, and updating access frequencies of low addresses with a low address of the current sampling address; and when a next row hammer refresh signal arrives, using a low address with a highest access frequency stored in the group of low registers as a low address of the row hammer refresh address, and using the locked high address as a high address of the row hammer refresh address.