292 results about "Register bank" patented technology

The invention discloses an attention mechanism calculation method and device, a storage medium and a product, and the method comprises the steps: carrying out matrix multiplication operation through employing a query matrix block of a first register block and a key matrix block of a shared memory, obtaining a first product matrix block, and writing the first product matrix block into a second register block; performing exponential operation by using the first product matrix blocks to obtain sub-matrix blocks, writing the sub-matrix blocks into a second register block in a covering manner, and writing the sub-matrix blocks into a third register block in the form of a target precision type; performing matrix multiplication operation by using the sub-matrix blocks of the third register block and the value matrix blocks of the shared memory to obtain second product matrix blocks, and writing the second product matrix blocks into a second register block; performing softmax operation by using the second product matrix blocks to obtain attention result matrix blocks, and writing the attention result matrix blocks into a fourth register block; and writing the attention result matrix of the fourth register group into the shared memory in blocks. According to the embodiment of the invention, overflow of the register can be avoided, and the utilization of hardware resources is maximized.

The invention discloses an attention calculation implementation method and device, a medium, equipment and a product, and the method comprises the steps: loading the current to-be-calculated ith query block from a shared memory to a first register group of a consumer thread group, and carrying out the internal splitting calculation of the query block and a key block, so as to obtain corresponding attention score blocks; sequentially obtaining MK attention score blocks, and executing attention fusion calculation of mixing precision with the corresponding value blocks to obtain an attention output block corresponding to the ith query block; and after the attention output blocks are logically divided into N2 batches, a specified register group for storing target precision type data in the fusion calculation process is multiplexed and executed according to batches, target precision type conversion is carried out, and an output result after conversion of each batch is written back to a shared memory. According to the method, the existing hardware resources can be efficiently utilized to improve the calculation performance, and the method is particularly suitable for large-size query block and key block scenes.

The invention discloses a depth operation implementation method and device for parallel pixels in the vertical direction, a medium, equipment and a product. The method comprises the following steps: mapping each channel group with a thread bundle containing NT threads; acquiring jumping step length of vertical direction access and parameter configuration of a sliding window operator; performing register resource allocation for each thread to form a sliding window data cache region; determining NH row starting point coordinates of the current scanning round; when the current scanning round is executed, in each column slice participating in calculation, pixel groups at NT row and column positions are scanned from each row starting point coordinate with the jump step length as the span, and the pixel groups are loaded to register groups of all threads in corresponding thread bundles in sequence, so that each thread can process the calculation task of the corresponding local sliding window view. According to the method, thread-level independent calculation task allocation is realized through a pixel parallel strategy among threads, and allocated hardware resources can be utilized to the maximum extent.

The invention discloses a server slot resource allocation system and method, a server, equipment and a medium, and relates to the technical field of servers, the system comprises at least one physical slot of the server, a register component and a firmware component, the register component comprises a first register and a second register, the first register is used for storing a global identifier of a physical slot position, determining a resource allocation mode of the physical slot position, configuring a second register at each physical slot position to store a resource allocation parameter of the physical slot position, and reading the first register and the second register by utilizing a firmware component after the server is powered on, according to the resource allocation mode and the resource allocation parameters, resources are allocated to at least one physical slot, on-demand allocation and safe management and control of the resources are achieved, the method is not limited by the slots, the technical problems of resource waste and slot limitation caused by static allocation in related technologies are solved, and the resource allocation efficiency is improved. The technical effects of dynamically allocating resources, remarkably improving the resource utilization rate and deployment flexibility and the like are achieved.

The invention discloses a pixel parallel depth operation implementation method and device, a medium, equipment and a product, and the method comprises the steps: dividing an input tensor into m channel groups, and distributing the channel groups to a thread bundle containing NT threads for independent processing; obtaining the number of elements, participating in coverage operation, of a sliding window operator in a two-dimensional plane, a sliding step length and row and column starting point coordinates of initial coverage of each element; allocating register groups with the same number as the elements for each thread; each register group is used for storing a pixel group of a corresponding element; in the channel group, NT row and column positions are scanned by rows from each row and column starting point coordinate according to the sliding step length, and corresponding pixel groups are loaded to register groups of corresponding threads in sequence, so that each thread can process a calculation task of a local sliding window view. According to the method, thread-level independent calculation task allocation is realized through a pixel parallel strategy among threads, and allocated hardware resources can be utilized to the maximum extent.

The embodiment of the invention discloses a cross-level gating conversion method and device, equipment and a storage medium, and the method comprises the steps: obtaining a target gating circuit diagram; identifying a connection relationship between devices in the target gating circuit diagram, and determining at least one clock path according to the connection relationship; wherein the clock path is used for representing a signal transmission path from the register to the top port; compiling a device in the clock path into a corresponding integrated unit so as to complete a conversion process of the target gating circuit diagram; wherein the integrated unit represents a device set composed of at least one register. According to the technical scheme, the clock paths in the circuit diagram can be automatically recognized, the devices in the clock paths are compiled into the corresponding integrated units, a large number of fan-out devices do not need to be processed in the conversion process, the logic copy amount is reduced, system resource consumption is reduced, and the device compiling efficiency is improved by conducting device compiling based on the clock paths. Original hierarchical structures between devices can be retained.

The invention discloses an embedded SoC-level real-time monitoring and analyzing device. The embedded SoC-level real-time monitoring and analyzing device is composed of a bus comparator, a system event counter and a control register set. The bus comparator collects access signals of an address bus, a data bus and an instruction bus in real time, compares the access signals with a preset matching rule, generates a trigger signal for driving the event state register to record and output an interrupt signal or a debugging signal during matching, and takes the trigger signal as an input event of the system event counter; the system event counter monitors various events generated in the operation process, and when the monitoring result is equal to a preset reference value, a trigger signal is generated; and the control register group configures the matching condition of the bus comparator, sets the counting mode of the system event counter, and reads the comparison state, the event counting result and related monitoring information through the bus interface. According to the method, a configurable event capture mechanism and multiple counting modes are introduced in a hardware level, so that the dependence on software debugging is reduced, and the real-time performance of monitoring and analysis is improved.

The invention discloses an attention mechanism calculation method and device, a storage medium and a product, and the method comprises the steps: carrying out the matrix multiplication operation of a query matrix block and a key matrix block, obtaining a first product matrix block of a first precision type, writing the first product matrix block into a second register group, and then carrying out the index operation, and obtaining a molecular matrix block; writing the quantized sub-matrix blocks into a third register block according to a second precision type; writing the sub-matrix blocks into a fourth register block according to a third precision type, and performing layout conversion through a shared memory; performing softmax operation by using the molecular matrix blocks and the value matrix blocks after layout conversion to obtain attention result matrix blocks of a first precision type, and writing the attention result matrix blocks into a fifth register block; and writing the attention result matrix blocks into the shared memory according to the third precision type. The embodiment of the invention can reduce the accumulative error of the intermediate operation result.

The invention provides a memory access system oriented to vector and matrix calculation, the system comprises a vector memory access unit, a matrix memory access unit, a vector register group and a matrix register group, the vector memory access unit is connected with a memory interface and the vector register group, reads elements of a one-dimensional data structure or a two-dimensional data structure from a memory, and stores the elements of the one-dimensional data structure or the two-dimensional data structure; vector data are generated through data reorganization operation, a matrix access unit is connected with a memory interface and a matrix register set, matrix block data of a two-dimensional data structure are read from a memory together with the matrix access unit, matrix data are generated after data reorganization, and the matrix data are broadcasted to one or more computing units according to rows or columns. And performing calculation on the matrix data and the vector data. In the memory access system, the vector memory access unit and the matrix memory access unit can load data in parallel, and the utilization rate is improved through a plurality of computing units, so that the problems of low memory access efficiency and low memory bandwidth utilization rate are solved.

The invention discloses a storage resource allocation method and device, a computing device and a storage medium. The storage resource allocation method is used for allocation of shared registers in a processor and comprises the steps that a discontinuous register block list is added into an available register block list, the discontinuous register block list comprises a plurality of discontinuous register blocks with the interval step length being M, and M is a positive integer larger than 1; in response to an allocation request that the current instruction occupies K discontinuous registers, allocating a discontinuous register group to the current instruction, K being a positive integer greater than 1; and updating the state of the distributed discontinuous register block in the discontinuous register block list. According to the storage resource allocation method, the utilization rate of the register can be improved, so that the number of synchronously executed threads is increased, and the program execution parallelism is improved.

The invention discloses a device and a method for realizing a register block shared by a general-purpose computing core and a tensor core, a tensor core read request unit sends a read request and stores the read request in a tensor core read request queue, and a life cycle counter and a clock cycle counter are triggered to start counting; the life cycle counter records life cycle values of read requests in the tensor core read request queue; the tensor core read request scheduler transmits a to-be-executed read request to the register block when the life cycle value of the to-be-executed read request reaches a preset value, so as to read a tensor core operand from the register block and store the tensor core operand in a tensor core operand cache; the priority of the general calculation core is higher than that of the tensor core before the life cycle value of the to-be-executed read request reaches a preset value; the clock period counter triggers the tensor core operand cache to send the tensor core operand to the tensor core execution unit when the count value reaches a preset trigger value. According to the invention, the read bandwidth of the register block can be utilized to the maximum extent, and the overall performance is effectively improved.

The invention provides a task scheduling method, a task scheduling device and electronic equipment, and aims to solve the problem that the real-time performance of a system can be improved while the load of a CPU (Central Processing Unit) is increased by accelerating the interruption period of the system. The task scheduling method comprises the steps that a special register block is configured for each created task, and the special register block is used for dynamically storing scheduling parameters of the tasks; updating the expiration times of the tasks according to the system reference time through hardware logic; generating a ready state of the task based on the expiration times and the task type through hardware logic; the priorities and the ready states of all the tasks are compared through hardware logic, and the ready task with the highest priority is screened out; and comparing the priority of the ready task with the highest priority with the priority of the currently executed task through hardware logic, and when the priority of the ready task with the highest priority is higher than that of the currently executed task, triggering task switching interruption to an operating system, so that the operating system performs task switching according to the information of the ready task with the highest priority.

The invention provides an FIFO (First In First Out) data reading method, device, system, equipment and medium, the method comprises the following steps: when a data reading request is triggered, calculating a read address according to a data reading address carried in the data reading request; the read address is used for representing a value when the read address register is about to be updated in the previous clock period; selecting target data from the next beat of data of the register file or the beat-to-write data through the multiplexer according to the beat-to-read address; the next beat of data of the register file refers to data stored in the register file in the next clock period; the current data are data which are currently written into a first-in first-out (FIFO) queue; and performing a beating operation on the target data through a register, and performing a reading operation through a data reading interface of the FIFO queue. According to the scheme, the overall delay of data reading is reduced, the running speed and performance of the whole system are improved, and then the running speed of a chip is increased.

The invention discloses a data processing device, a data processing method, a chip and electronic equipment, and relates to the technical field of data processing. The data processing device comprises a storage module which is configured to store x groups of original data vectors, the original data vectors comprise m data elements, and x and m are positive integers; the calculation module is configured to access the original data vectors stored in the storage module, and reconstruct the x groups of original data vectors into one or more intermediate matrixes according to the parallel processing capability of the single-instruction multi-data execution unit and a target value k of a Top-k operator; loading the intermediate matrix into a vector register block according to columns, carrying out odd-even merging sorting by utilizing a single-instruction multi-data execution unit, and realizing in-line sorting on the intermediate matrix; and loading the intermediate matrix subjected to in-line sorting into a vector register block according to columns, and performing one or more rounds of merging sorting by utilizing a single-instruction multi-data execution unit to obtain top-k data elements in x groups of original data vectors.

The invention provides an AXI bus monitoring system and method, the system comprises a host side monitor, a slave side monitor and an error summarization processing module, and the error summarization processing module is respectively connected with the host side monitor and the slave side monitor; a plurality of register groups are arranged in each monitor, and each register group corresponds to one timer and one state machine and is used for monitoring one read or write transaction; the timer is used for carrying out timeout counting on the read / write transaction, and when the count exceeds a preset value, a timeout error is triggered to be reported to the error summarization processing module; the state machine is used for tracking which stage the read or write transaction is performed in real time; the register block is used for latching an AXI bus signal so that a monitor constructs data to complete access; and the error summarization processing module is used for executing corresponding processing according to the error codes reported by the host side monitor and / or the slave side monitor and the information latched by the register block. The system can effectively avoid system deadlock.

The invention provides a matrix multiplication operation method and device and a matrix transposition operation method and device of a processor. The matrix multiplication operation method of the processor comprises the following steps: taking a first matrix of which the storage sequence is inconsistent with the loading sequence for carrying out element-by-element multiplication operation as a second matrix, loading the second matrix through a register set in the processor, and dividing the second matrix into a plurality of third matrixes, replacing elements in a plurality of nth register groups included in the register set; for each nth register group, reading elements in the nth register group according to an alternating sequence of the elements of the first register and the elements of the second register through the (n + 1) th register group; when iteration is carried out for n to N-1, the obtained sixth matrix is stored in the memory; and performing element-by-element multiplication and accumulation on the elements at each position of the first matrix and the sixth matrix. According to the invention, the time required by matrix multiplication operation can be reduced.

The invention provides an RISC-V tensor instruction set extension method based on an intelligent processor. The method comprises the steps that a special tensor configuration register set is introduced to store tensor element information and operation element information; encoding a tensor extension instruction by adopting a 64-bit fixed-length instruction encoding format; and setting high-capacity on-chip tight coupling storage with uniform addressing in a processor core, and taking the high-capacity on-chip tight coupling storage as a direct operation space of all tensor expansion instructions. The invention further provides an intelligent processor-based RISC-V tensor instruction set extension device, a storage medium and electronic equipment. According to the method, the RISC-V tensor instruction set extension which supports high-dimensional tensor operation, is dense in calculation and is friendly to hardware can be realized.

The invention relates to the technical field of processor function verification, in particular to a processor architecture verification method, which comprises the following steps of: based on architecture description document information, analyzing an instruction name, an operand attribute and a register state, screening instruction set structure information according to an operand definition rule through an architecture document, judging the availability of register calling, and verifying the processor architecture. And screening the register combination meeting the architecture description rule to obtain instruction set architecture data. According to the method, the framework description document information is analyzed, effective application of framework description rules is ensured, test codes are more targeted, verification effectiveness is improved, instruction combinations which cannot be logically executed are eliminated, coverage rate calculation precision is optimized, and invalid test data interference is reduced; through improvement of instruction analysis, accessibility analysis, coverage rate optimization, execution adjustment and the like, it is ensured that the execution condition of an instruction set is comprehensively evaluated, the test efficiency is improved, and the completeness and reliability of processor verification are enhanced.

The invention provides an artificial intelligence chip and a collaborative thread bundle calculation method. The cooperative thread bundle calculation method comprises the following steps of: initializing a plurality of thread bundle units by a thread bundle resource allocation unit, so that the plurality of thread bundle units have the same initial vector register base address to form a group of cooperative thread bundles; the thread beam resource allocation unit notifies a thread beam scheduling and instruction transmitting unit to send a plurality of execution instructions to an execution unit; running a plurality of thread bundles of the plurality of thread bundle units by the execution unit according to the plurality of execution instructions; reading different scalar parameters from the respective scalar registers of the plurality of thread bundle units by the plurality of thread bundles; and accessing, by the plurality of thread bundles, the same register space of the vector register according to the same initial vector register base address. According to the artificial intelligence chip and the cooperative thread beam calculation method, the efficient cooperative thread beam calculation function of the cross-thread beam sharing vector register block can be achieved.

The invention provides a large language model operator compiling method oriented to a GPU platform, and belongs to the field of GPU operator compilation. A large language model operator is compiled through a Python interface to obtain a Python code; performing lexical analysis and grammatical analysis on the Python code to generate an abstract syntax tree; mapping the abstract syntax tree into an MMIR extension intermediate representation; tensor layout in the MLIR extension intermediate representation is uniformly converted into a binary linear mapping matrix, and optimization problems of global memory layout, shared memory layout and register block layout are analyzed based on the binary linear mapping matrix; automatically deducing a non-key tensor layout based on a program control flow diagram, generating a global optimal layout scheme, and obtaining an optimized MMIR extension intermediate representation; enabling the optimized MLIR extension intermediate representation to pass through a GGPU (Graphics Graphics Processing Unit) target code generator of the MLIR, and generating a PTX code adaptive to the NVIDIA GPU; the PTX code is loaded to a GPU, and an operator calculation result is output; the invention further provides a compiling system. The problem that the current large language model operator compiling efficiency is low is solved.

A method for obtaining a row hammer refresh address, including: after a row hammer refresh signal arrives, obtaining a current sampling address, and determining whether a high address is locked in a current row hammer refresh cycle; in response to the high address being locked, determining whether a high address of the current sampling address is identical to the locked high address; in response to being identical, updating an access frequency of the locked high address, and updating access frequencies of low addresses with a low address of the current sampling address; and when a next row hammer refresh signal arrives, using a low address with a highest access frequency stored in the group of low registers as a low address of the row hammer refresh address, and using the locked high address as a high address of the row hammer refresh address.

The embodiment of the invention discloses a chip debugging method, which comprises the following steps that: after a chip is electrified, when the voltage of a DP pin is detected to meet a first preset condition, the chip enters a debugging mode, and the DP pin establishes a relation with a plurality of groups of registers; the register writes a to-be-burnt signal with a preset sequence through a DP pin, and burning information in the to-be-burnt signal is associated with the register group number; when the register receives a burning instruction, the chip enters a burning mode, the DP pin establishes connection with the memory, the burning instruction is a first-class register trigger signal, and the first-class register trigger signal comprises register address information and register data; and in the burning mode, when the burning enable signal is valid, burning the burning information in one group of registers to the memory, then the burning enable signal is invalid, and the burning enable signal is in the valid stage again until the burning is finished. Through the implementation of the embodiment, chip pin resources can be reduced, and the chip debugging speed is improved.

Embodiments of the present disclosure relate to applications, platforms, architecture, etc. for using a master test image that may be used for multiple different tests. For example, a testing system may include a register bank that may be loaded with test configurations corresponding to one or more tests. The test configurations may respectively correspond to sets of control packets included in the master test image that may be used or executed for corresponding tests. The test configurations may indicate execution orders of their respective sets of control packets in which the execution order of one or more of the control packets included in the sets of control packets may differ from a default execution order of such control packets as indicated in the master test image. Such a configuration may accordingly allow for the flexibility of performing many different tests using a single master test image.

The invention relates to the related technical field of reasoning calculation, in particular to an AI chip reasoning acceleration method and system and a medium, and the method comprises the steps of collecting adaptive scheduling parameters, setting a hierarchical pipeline response gradient under a reasoning acceleration framework, loading the optimized scheduling parameters to a configuration register group, and setting reasoning self-driven circulation. The technical problems that load feature perception is one-sided, scheduling parameters are statically solidified, dynamic adjustment along with reasoning tasks cannot be achieved, adaptability to feature graph structure changes and activation mode updating in the reasoning process is poor, and reasoning stability is insufficient are solved, and a tracing strategy based on a three-dimensional load feature vector and attention guidance is achieved. The method has the technical effects that the matching degree of scheduling parameters and task states is improved, the scheduling parameters and model compression granularity are dynamically adjusted in combination with real-time energy consumption constraints, a federated on-chip learning architecture enables the parameter iteration updating efficiency of a layer sensitivity analysis unit to be improved, the reasoning stability and the continuous operation reliability are enhanced, and the method adapts to end side complex dynamic scene requirements.

The application discloses a message encryption method and device, and relates to the technical field of data encryption. The message encryption method comprises the following steps of: in a previous clock cycle of processing adjacent first and second message words, a first hash module calculates a first e value and a first a value according to the first message word, a hash register value and a hash constant; a second hash module calculates a second e value and a second a value according to the second message word, the hash register value, the first e value, the first a value and the hash constant; and the second a value, the first a value, the second e value and the first e value are sequentially cached into a third hash register, a fourth hash register, a seventh hash register and an eighth hash register of a hash register group. Two hash modules are adopted to process two message words in the same clock cycle, the clock cycle used for calculating the message word digest value in the message encryption process is reduced, and therefore the user experience can be obviously improved.

The invention provides a processor, a method for executing an instruction on a processor and a computer. The processor comprises at least one single-instruction multiple-thread processing units. The single-instruction multiple-thread processing unit includes a plurality of warps for executing an instruction; a shared register group, which includes a plurality of general-purpose registers shared by the plurality of warps; and a predicate base address register, which is configured to: correspond to the plurality of warps; and indicate a base address for a subset of the plurality of general-purpose registers that serves as a predicate register for the warp in the shared register group, wherein: the warp performs a predicated execution for an instruction in view of a predicate value in the subset of the plurality of general-purpose registers that serves as the predicate register for the warp.

The invention discloses an area-optimized DI circuit asynchronous serial register block, a chip and electronic equipment. The serial register block comprises a plurality of DI-latches, a Mux component, two Demux components and a Fork component, a DI-latch for storing Null is connected in front of each DI-latch for storing Data, two DI-latches for storing Data and Null respectively serve as a register unit, and all register units are connected in series to form a register unit string; the front end of the register unit string is connected with a Mux component with the same width as the register, and the rear end of the register unit string is provided with two Demux components with the same width as the register and a Fork component; and the register unit strings form a register unit loop through a rotation path. According to the DI circuit asynchronous serial register block with the optimized area, only two DI-latches are needed on the register unit, selective access can be achieved on the periphery of the register unit without large-scale Demux components and Mux components, and the design area of the register block is effectively reduced.

The present invention provides a physical signal monitoring-based transmission link fault location method and system in the technical field of transmission link fault location. The method comprises: step S1, a layer 2 switching chip creating a register group, and an MCU creating a MAC address table; step S2, when a new network device is accessed, the MCU performing anomaly verification on a new MAC address by means of the MAC address table and then updating the MAC address table; step S3, performing fault location by means of a queue controller watchdog event, and updating an event register on the basis of a fault type; step S4, the MCU reading the fault type from the event register to match a fault handling measure from a fault management table; and step S5, when a fault handling measure is found, executing a transmission link recovery operation on the basis of the fault handling measure, and when no fault handling measure is found, reading switch data from the register group and uploading the switch data to a server for fault location, or executing fault location on the basis of a console command inputted from a Console interface. The present invention has the advantage that the convenience and timeliness of transmission link fault location are greatly improved.

The invention discloses a multichannel LED digital control system and method. The system comprises a main controller which generates an LED control instruction and sends a data frame through a differential bus; the plurality of LED driving modules are connected with the main controller through a differential bus, and each LED driving module comprises a differential receiver for receiving a differential signal of the differential bus; the UART communication module is connected with the differential receiver and converts the differential signal into serial data; the data processing state machine module is connected with the UART communication module and is used for analyzing the received data frame, and the data frame comprises a synchronous byte, a device address / command composite byte, a register address byte, a data byte and a CRC (Cyclic Redundancy Check) check byte; the digital logic counter is used for measuring the bit width of each data bit in the synchronous bytes and calibrating the sampling time sequence of the UART communication module based on a measurement result; the register group is used for storing LED control parameters; and the multi-path PWM generator is connected with the register block and generates multi-path PWM signals according to the LED control parameters so as to drive the LEDs. The power consumption is reduced.

The present disclosure provides a digital shaping filter with a dynamically reconfigurable folding circuit structure and a design method. The digital shaping filter includes: a data redefinition logic unit for performing bit width conversion; a data shift register unit for storing output data of the data redefinition logic unit; a first adder unit for performing addition operations according to the folding circuit structure; an impulse response coefficient register stack unit for writing impulse response coefficients; a reconstruction completion flag register unit for issuing a reconstruction completion signal; a multiplier unit for performing multiplication operations and receiving the output signal of the reconstruction completion flag register unit; a second adder unit for performing addition operations on the output data of the multiplier unit; an order reconstruction register unit for writing the order of the digital shaping filter; a timing control logic unit for selecting result data; and a selection output logic unit for outputting the result data.