143 results about "Thread scheduling" patented technology

The invention relates to a world model construction method, in particular to a high-fidelity lightweight world model construction method for an end-to-end automatic driving test, which is used for constructing a high-fidelity world model and performing knowledge distillation on the world model to solve the problems of huge parameters, low reasoning efficiency and the like of the world model. Model parameters are reduced on the basis of reserving the world model generation capability, and the reasoning efficiency is improved; a CUDA operator is developed in a user-defined mode for the bottleneck part of world model calculation, video memory allocation is optimized, and the reasoning efficiency of a high-fidelity world model is improved based on a single-device multi-thread scheduling and multi-device cooperative calculation method. According to the method, the high-fidelity lightweight world model for the end-to-end automatic driving test can be constructed, the problems that an existing world model is low in multi-modal information alignment precision, poor in cross-view and cross-frame consistency, low in reasoning efficiency and the like are effectively solved, the confidence coefficient of the end-to-end automatic driving system test process is improved, and the test efficiency of the end-to-end automatic driving system is improved. And the testing efficiency of the end-to-end automatic driving system is greatly improved.

The invention relates to the technical field of intelligent monitoring, in particular to a multi-thread low-power-consumption intelligent monitoring system based on an AI processor. The method has the advantages that aiming at the problems of unbalanced computing power and power consumption, high multi-task processing delay and strong hardware dependence in the prior art, the NPU module of the RK3588 processor is combined with the INT8 quantitative model, so that the power consumption is lower than 10W under the 6TOPS computing power; a dynamic multi-thread scheduling mechanism is designed, parallel processing of more than eight paths of video streams is supported through binding of a priority queue and an NPU core, and end-to-end delay is compressed to be within 200 ms; a zero-copy video stream architecture is constructed, data transfer is eliminated through memory mapping, and preprocessing time consumption is reduced by 90%; an energy efficiency control module is integrated, the NPU voltage frequency is dynamically adjusted according to the load, and the energy efficiency ratio reaches 0.83 TOPS / W; space-time alignment of multi-model reasoning results is realized by adopting a frame ID synchronization technology, and the mismatching rate is lower than 0.1%.

The invention discloses a national secret algorithm data encryption transmission method and system. The method comprises the steps of obtaining to-be-encrypted data and network parameters, establishing a Bayesian network probability ablation model, performing Monte Carlo sampling ablation national secret encryption and evaluating attack risks, and generating a probability security encryption strategy; and extracting a Brinell feature set, constructing a long and short-term memory network time prediction model, and optimizing by using a simulated annealing algorithm to obtain an optimal encryption parameter configuration sequence. Generating a key pair according to the sequence and SM2, establishing a shared key by means of an elliptic curve Diffie-Hellman protocol, deriving an SM4 session key through SM3, and establishing a hybrid encryption key system; constructing a teacher and student network model, optimizing multi-thread scheduling through adversarial distillation training and a retrieval enhancement technology, and generating a multi-thread parallel encryption architecture; and network parameters are monitored in real time, a reinforcement learning adaptive decision engine is constructed, a strategy is dynamically adjusted, and adaptive encryption transmission is completed. According to the invention, the optimal balance between the security and the efficiency in the data encryption transmission process is realized.

One embodiment provides a multi-chiplet graphics processor comprising a plurality of chiplets, where a chiplet of the plurality of chiplets comprise a memory interface, processing resources configured to execute threads of a kernel, and thread dispatch circuitry to facilitate dispatch of threads of the kernel to the processing resources. The processing resources are configured to execute threads of a first kernel, receive dispatch of threads of a second kernel for execution before completion of the first kernel as threads of the first kernel retire, execute a first phase of the second kernel during completion of execution of the first kernel, via a thread of the first kernel, signal an event via an uncached write to a global memory, and execute a second phase of the second kernel based on detection of the event via an uncached read from the global memory.

The invention provides an edge heterogeneous Internet of Things operation and maintenance chassis data processing method and system. The method comprises the following steps: firstly, according to the types of the multi-source heterogeneous terminals, formulating a unified data acquisition scheme, defining a unified acquired data format, respectively managing and executing a data acquisition task of each multi-source heterogeneous terminal by adopting an asynchronous multi-thread scheduling mechanism, and acquiring and generating corresponding acquired original data; and performing standardization processing on the collected original data in the normal sampling state to generate a multi-source collected data set. And then, according to the type of each multi-source heterogeneous terminal, for the corresponding multi-source acquisition data set, calculating a standardized anomaly score, performing weighted comprehensive processing, generating a comprehensive anomaly score, and determining an anomaly level according to the comprehensive anomaly score. And finally, correspondingly matching the exception level of the multi-source heterogeneous terminal with a preset local protection strategy, executing a local exception protection action based on a matching result, recording exception information and reporting exception alarm information to a remote center platform.

The invention relates to a self-adaptive optical matrix calculation acceleration method based on an ARM framework, and belongs to the field of self-adaptive optical wavefront correction technology and embedded parallel calculation. The method comprises the following steps: analyzing a mathematical mapping relationship between a microlens array and wavefront phase distribution in a Hartmann sensor image, and constructing a wavefront matrix operation model based on an ARM multi-core architecture; designing a Hartmann image data rearrangement strategy, dividing a single-frame Hartmann image into multiple task calculation units, and realizing parallelization processing of wavefront slope calculation; a wavefront matrix operation kernel is optimized according to ARM NEON instruction set characteristics, and vectorization calculation of multi-channel wavefront reconstruction is realized by adopting an SIMD parallelization technology; and computing resource allocation is coordinated through a dynamic thread scheduling algorithm, and the task allocation proportion among multiple cores is adjusted according to the real-time load condition. According to the method, the wavefront calculation efficiency is remarkably improved, so that the overall bandwidth of the adaptive optical system is greatly improved.

The invention relates to the technical field of state recognition, in particular to an Android device remote state monitoring and intelligent operation and maintenance system which comprises an event trigger analysis module, a state feature classification module, a state section plotting module, a state fragment packaging module and a state level response module. In the method, a state path set is constructed through time label alignment of broadcast and thread events, an access source mark and a network return parameter are combined to generate a multi-dimensional state label sequence, a thread scheduling track and a memory block are mapped to form a state section structure, and an active boundary area is positioned in combination with power consumption change. Path numbers and permission information are combined, screened and packaged into a structured state unit, response level zones are divided through the number depth and the repetition rate, and complete restoration of behavior paths and accurate recognition of state nodes under the scenes of concurrent calling, complex event chains and the like are supported. And the granularity of terminal state analysis, the traceability continuity and the hierarchical adaptation capability of operation and maintenance response are remarkably improved.

The invention discloses a method for ensuring hard real-time in a Linux user mode based on a multi-core CPU, and belongs to the technical field of embedded systems. According to the method, a Linux kernel is configured to be in a completely preemptable mode, user threads with the number equal to that of CPU kernels are created and bound to different kernels, a real-time scheduling kernel is selected, the thread scheduling strategy of the real-time scheduling kernel is set to be SCHEDFIFO, the priority of the real-time scheduling kernel is equal to that of the lowest-priority soft interrupt, the thread stack space is locked, the real-time kernel is isolated through kernel parameters isolcplus and nohzfull, and the cost of tick is avoided. Finally, the real-time core is exclusively used for executing the real-time task. According to the scheme, the problem that the real-time performance of the Linux user state task is poor due to the fact that a kernel cannot be preempted, scheduling delay, memory page changing, system interference and the like is effectively solved, and extremely low delay and high certainty of user state task response are ensured through multi-level collaborative optimization.

The invention discloses a memory key value storage system thread scheduling method and device and a medium. According to the method, a system is organized into a two-layer architecture of a cache resident CR layer and a memory resident CR layer. Uniformly receiving and shunting all the requests by the CR layer; quickly processing the cached requests in the CR layer in a non-blocking manner; and the missed requests are forwarded to the MR layer in a non-blocking manner through the efficient communication queue. And after the MR layer processes the request, the completion signal is efficiently synchronized back to the CR layer by updating an implicit notification mechanism of the queue state identifier. According to the method, by effectively isolating tasks with different access characteristics, the CPU cache utilization rate is remarkably improved, load balance and low synchronization overhead under high concurrency are taken into account, and the overall performance and expandability of the system are improved.

The invention discloses an electric connector detection system and method based on vision, and belongs to the field of machine vision and industrial detection, and the system comprises a large constant water star series industrial camera, a multi-angle and high-uniformity adjustable light source system, a product feeding moving and packaging mechanism, a computer control system and UI software. Wherein the computer control system adopts multi-thread scheduling, a modular architecture and a sub-pixel-level algorithm, and supports high-throughput processing of 3-6 4024 * 3036 pixel industrial cameras, an image acquisition module of the computer control system can uniformly manage multiple models of cameras, and a UI (User Interface) is a drag-and-drop interface and integrates debugging tools such as OpenGL (Open Graphics Library) and parameter hot loading; the method comprises the steps of hardware configuration, trigger starting, image acquisition, positioning correction, ROI drawing, detection, reference line determination, size measurement and sorting control, ROI drawing can adapt to regular and irregularly arranged pins, the adaptability is high, the precision is high, operation is convenient and fast, full-process automatic detection can be achieved, and the requirement of a high-speed production line is met.

The invention discloses a thread scheduling method and device, electronic equipment and a storage medium, and belongs to the technical field of operating systems. The method comprises the steps that a DSM PF event of a virtual machine is monitored, and the DSM PF event is triggered when a plurality of threads access the same shared memory page in a cross-node mode; according to the DSM PF events, an inter-thread incidence matrix is constructed, and the inter-thread incidence matrix is used for quantifying the number of times of triggering the DSM PF events between any two threads; the thread graph structure is divided to generate a thread grouping scheme with the aim of minimizing the number of DSM PF events between different grouping threads, the vertex of the thread graph structure represents the threads, and the adjacency matrix of the thread graph structure is the incidence matrix between the threads.

The invention discloses a thread scheduling method, electronic equipment, a storage medium and a program product, and relates to the technical field of computers, security check is performed on a source thread and a target thread through a thread switching request initiated by the source thread, an allocatable time period of the source thread allocated to the target thread is calculated according to a security detection result, and the allocatable time period of the source thread allocated to the target thread is sent to the electronic equipment. Bypassing a processing mechanism of a completely fair scheduler, updating the virtual running time of a source thread, distributing an allocable time period to a target thread, calling a context switching function to execute thread switching operation on the source thread and the target thread, and synchronously updating the virtual running time of the target thread when the target thread consumes the allocable time period. According to the thread scheduling method and device, the problem that in the related technology, when a complete fair scheduler processes high-frequency and collaborative thread tasks, due to the indirect handover mechanism and fair scheduling characteristics of the complete fair scheduler, the delay of thread scheduling is improved is solved, and the delay of thread scheduling is reduced.

The invention relates to the technical field of data communication, and discloses a data communication method and device for a robot system and a robot. The method comprises the following steps: when a data acquisition agent module monitors that business data is written into a shared memory area, acquiring the business data from the shared memory area; caching the business data according to the data type of the business data; and acquiring a network state of the robot system, and uploading the cached service data to a server or locally storing the cached service data according to the network state and the data type of the service data. Through a data acquisition and cache uploading separation mechanism, the problems of high occupation of data communication bandwidth, conflict between real-time performance and flexibility, high thread scheduling load and the like in an existing robot system are solved, and the communication efficiency and the data management capability of the system are remarkably improved.

Bank aware thread scheduling and early dependency clearing techniques are described herein. In one example, bank aware thread scheduling involves arbitrating and scheduling threads based on the cache bank that is to be accessed by the instructions to avoiding bank conflicts. Early dependency clearing involves clearing dependencies for cache loads in a scoreboard before the data is loaded. In early dependency clearing for loads, delays in operation can be reduced by clearing dependencies before data is required from the cache.

The invention relates to the technical field of laboratory control, in particular to a multitask parallel experiment system and method for a laboratory, and the system comprises a task management module which is used for receiving and splitting a plurality of experiment plans submitted by a user, and obtaining a plurality of experiment tasks corresponding to the experiment plans; the task constraint module is used for performing condition constraint on the experiment task according to the constraint rule to obtain a constraint experiment task with a constraint condition; the material detection module is used for acquiring material container resource information of the experiment platform, performing material container resource detection on the constraint experiment task according to the material container resource information, and generating a resource satisfaction signal; and the multi-task scheduling module is used for constructing a multi-thread scheduling strategy based on the thread pool management mechanism and the resource satisfaction signal, and scheduling the execution module to execute a plurality of experiment plans according to the multi-thread scheduling strategy. The utilization rate of experimental resources can be optimized, so that the execution efficiency of experimental tasks and the stability of experimental operation are improved.

The invention relates to the technical field of medical information parallel computing, in particular to a multi-thread parallel computing method and system for Brucella spondylitis diagnostic parameters, and the method comprises the following steps: a diagnostic task dependency graph construction step: constructing a directed acyclic graph based on the computing dependency relationship of the diagnostic parameters and determining the task priority; a self-adaptive thread scheduling step: adopting a work stealing strategy and a lock-free concurrent queue to realize dynamic load balancing; a vectorization parallel computing step: performing batch computing on the diagnosis parameters by using a single-instruction multi-data-stream instruction; and a feedback driving optimization step: dynamically adjusting a scheduling strategy according to performance indexes to form closed-loop optimization, and deeply coupling the four core modules to realize synergistic interaction.

The application relates to a world model construction method, in particular to an end-to-end automatic driving test high-fidelity lightweight world model construction method, which constructs a high-fidelity world model, solves the problems of large world model parameters and low inference efficiency, performs knowledge distillation on the world model, reduces model parameters on the basis of retaining world model generation capacity, and improves inference efficiency; a CUDA operator is self-defined for a world model calculation bottleneck part, memory allocation is optimized, and a single-device multi-thread scheduling and multi-device cooperative calculation method are used to improve the inference efficiency of the high-fidelity world model. The application can construct an end-to-end automatic driving test high-fidelity lightweight world model, effectively solve the problems of low multi-modal information alignment accuracy, poor cross-view and cross-frame consistency, and low inference efficiency of the existing world model, improve the confidence of an end-to-end automatic driving system test process, and greatly accelerate the test efficiency of the end-to-end automatic driving system.

The invention discloses a reconciliation statement generation task scheduling system, a reconciliation statement generation method, equipment and a medium, and relates to the technical field of financial services, and the disclosed reconciliation statement generation task scheduling system comprises a task pool module used for storing to-be-executed tasks, the to-be-executed tasks are divided into a transaction data acquisition task, a transaction data integration task and a statement generation task according to processing stages, and each to-be-executed task takes a customer dimension as a minimum scheduling unit; the thread scheduling module is used for scheduling the execution sequence of the to-be-executed tasks according to a preset scheduling rule; and the working thread module is used for executing each task to be executed according to the execution sequence and a specified scheduling dimension, and the specified scheduling dimension is at least one of a client dimension, a space dimension or a time dimension. According to the invention, the generation efficiency of the account statement can be improved to guarantee the timeliness of the account statement.

Devices and techniques for thread scheduling control and memory splitting in a processor are described herein. An apparatus includes a hardware interface configured to receive a first request to execute a first thread, the first request including an indication of a workload; and processing circuitry configured to: determine the workload to produce a metric based at least in part on the indication; compare the metric with a threshold to determine that the metric is beyond the threshold; divide, based at least in part on the comparison, the workload into a set of sub-workloads consisting of predefined number of equal parts from the workload; create a second request to execute a second thread, the second request including a first member of the set of sub-workloads; and process a second member of the set of sub-workloads in the first thread.

This invention provides a graphics processing unit (GPU) resource management method, apparatus, electronic device, and readable medium. The method includes: detecting whether there is a stagnant streaming multiprocessor in the GPU; if there is a stagnant streaming multiprocessor, merging the remaining memory resources of the stagnant streaming multiprocessor with the remaining memory resources of at least one other streaming multiprocessor; determining at least one thread bundle to be executed in the stagnant streaming multiprocessor as a target thread bundle; and allocating memory resources to the target thread bundle based on the merged remaining memory resources using a preset thread scheduler in the GPU, so that the target thread bundle executes preset instructions based on the reallocated memory resources. This method allows for the rational allocation of remaining memory resources in the streaming multiprocessor, enabling the thread bundles in the streaming multiprocessor to run efficiently and improving the resource utilization efficiency of the streaming multiprocessor in the GPU.

This application provides a thread scheduling method, apparatus, electronic device, and storage medium, relating to the field of hardware testing technology. The specific solution is as follows: Obtaining the importance representation information of each target LLC to a target process, where the target LLC is the LLC occupied by threads running in the target process; determining the recommended LLC corresponding to the target process from the obtained importance representation information; in response to scheduling the target threads in the target process, determining the CPU core based on the load state of the CPU cores sharing the recommended LLC, and scheduling the target threads to the determined CPU cores for execution. Applying the solution provided in this application can improve the cache hit rate for scheduling threads in the same process to CPU cores sharing the same LLC and improve the operating efficiency of multi-core CPUs.

The invention discloses an automatic simplification and lightweight processing system for massive three-dimensional grid models, which relates to the technical field of mineral product screening and comprises a time sequence dependence index construction module, a nonlinear aggregation detection module, a memory remapping correction module, a time sequence playback adaptive control module and a phase conjugate self-correction mistake proofing module. And the time sequence dependency index construction module is used for acquiring a time sequence baseline and memory access mapping of multi-thread cache release, constructing a dynamic dependency index table according to a thread scheduling sequence, identifying a release path triggered in advance under the constraint of the dynamic dependency index table, extracting corresponding cache node information and generating a memory fragment distribution initial mapping. According to the method, accurate alignment of multi-thread memory release is achieved through the time sequence base line and the dynamic dependency index, the consistency and stability of memory management are improved, memory self-adaptive correction and error-proofing control are achieved through a closed-loop mechanism of remapping, playback and regulation, and efficient and reliable operation of the batch three-dimensional grid simplification process is ensured.

The application discloses a multimedia file storage method, device, equipment and medium, wherein the multimedia file storage method comprises the following steps: obtaining a live stream of a multimedia file; converting the live stream into a plurality of block files in a target format, wherein the size of the block files changes with the length of a cache queue and / or the number of writable disks; sequentially writing the plurality of block files into the cache queue, and scheduling a plurality of threads in a thread pool to write the block files in the cache queue into the writable disks in parallel, the optimal block file size can be calculated according to the length of the cache queue and the number of the writable disks, then the block files are read from the cache queue and written into the writable disks in parallel through thread scheduling, so that the threads reach the optimal scheduling frequency and the disks reach the optimal writing speed, and the efficiency of writing the live stream into a disk is effectively improved.

Provided in the embodiments of the present disclosure are an instruction scheduling method and apparatus for a simultaneous multithreading processor, and a processor, an electronic apparatus and a non-transitory storage medium. The instruction scheduling method comprises: in response to there being a plurality of instructions belonging to a plurality of threads in a current pipeline stage and a priority thread scheduling policy being enabled, acquiring a priority thread from among the plurality of threads; and on the basis of the priority thread, selecting a target instruction from among the plurality of instructions of the plurality of threads to enter the current pipeline stage.

The application provides a tile production real-time monitoring and integrity checking system, belonging to the technical field of geographic information systems and computer graphics processing, comprising a production task registration module, a tile integrity detection module, a message communication module and a browser rendering module; the production task registration module is used for collecting, analyzing and storing tile production task information; the tile integrity detection module is used for checking the integrity of tile data; the message communication module is used for pushing the tile production task state and the checking result from the server end to the browser end in real time; and the browser rendering module generates a tile production progress monitoring multi-dimensional view and a tile data health degree analysis view according to the received tile production task state and tile integrity checking result. The application proposes a tile production monitoring system integrating multi-thread scheduling, asynchronous message communication and rendering technology, and realizes full-link optimization of the tile production progress.

A thread scheduling method, a processor, and an electronic device are disclosed. The thread scheduling method includes: performing a pre-release operation of shared memory resources for a first thread group. Performing the pre-release operation of shared memory resources for the first thread group includes: when it is determined that the thread subgroup currently running in the processing unit is the last thread subgroup in the first thread group, releasing the shared memory resources occupied and available for release by the first thread group. This thread scheduling method can release the shared memory resources occupied by the current thread group while it is still running, thereby allowing the released resources to be allocated to other thread groups, achieving the purpose of pre-allocating resources, thus improving running efficiency and shortening the overall task completion time.

The embodiment of the invention provides a method and equipment for adjusting a thread scheduling strategy, a medium and a product. Comprising the steps that the running state of a first thread in a thread scheduling strategy mapping table is obtained, and the mapping table comprises thread information of a key scene influencing user experience; if the first thread is in the runnable state, obtaining the duration of the first thread in the runnable state; when the duration exceeds the tolerable waiting duration preset by the first thread in the mapping table, obtaining the scheduling type and priority of the second thread; the second thread is a thread preempting the first thread; and when the second thread cannot be found according to the mapping table, or the scheduling type and the priority of the second thread do not accord with the preset scheduling type and the preset priority corresponding to the second thread found through the mapping table, adjusting the scheduling type and / or the priority of the second thread. According to the scheme, the thread execution reliability is improved by optimizing the thread scheduling strategy.

The invention discloses a thread scheduling method, device and equipment based on an RISC-V framework. The method is applied to the electronic equipment based on the RISC-V architecture, an operating system kernel of the electronic equipment runs in a supervision mode of the RISC-V architecture, a user program of the electronic equipment runs in a user mode of the RISC-V architecture, and the method comprises the steps that the user program is analyzed, and a user mode stack, a kernel mode stack and a thread control block are created according to an analysis result; writing the entry address of the user program in the analysis result into an abnormal program counter in a supervision mode; and executing the supervision mode exception return instruction, switching the processor of the electronic equipment from the supervision mode to the user mode, jumping to the entry address of the user program, and starting to execute the user mode thread. The thread scheduling method based on the RISC-V architecture provided by the invention can be high in safety.

Techniques related to multi-stage thread scheduling are disclosed. In some embodiments, a processor circuit includes a plurality of lane pipelines for a plurality of lanes and a plurality of execution pipelines shared by the lane pipelines and configured to perform different types of operations provided by the lane pipelines. A first scheduler circuit can arbitrate among threads to assign threads to lanes. A second scheduler circuit can arbitrate among lanes to assign operations from a given lane to a given execution pipeline. The execution pipeline can provide backpressure information to the first scheduler circuit based on an execution state, and the first scheduler circuit can adjust a priority of threads for assignment to a lane based on the backpressure information. The disclosed techniques can reduce lane contention and starvation for execution resources.