175 results about "Thread scheduling" patented technology

The invention relates to a world model construction method, in particular to a high-fidelity lightweight world model construction method for an end-to-end automatic driving test, which is used for constructing a high-fidelity world model and performing knowledge distillation on the world model to solve the problems of huge parameters, low reasoning efficiency and the like of the world model. Model parameters are reduced on the basis of reserving the world model generation capability, and the reasoning efficiency is improved; a CUDA operator is developed in a user-defined mode for the bottleneck part of world model calculation, video memory allocation is optimized, and the reasoning efficiency of a high-fidelity world model is improved based on a single-device multi-thread scheduling and multi-device cooperative calculation method. According to the method, the high-fidelity lightweight world model for the end-to-end automatic driving test can be constructed, the problems that an existing world model is low in multi-modal information alignment precision, poor in cross-view and cross-frame consistency, low in reasoning efficiency and the like are effectively solved, the confidence coefficient of the end-to-end automatic driving system test process is improved, and the test efficiency of the end-to-end automatic driving system is improved. And the testing efficiency of the end-to-end automatic driving system is greatly improved.

The invention relates to the technical field of intelligent monitoring, in particular to a multi-thread low-power-consumption intelligent monitoring system based on an AI processor. The method has the advantages that aiming at the problems of unbalanced computing power and power consumption, high multi-task processing delay and strong hardware dependence in the prior art, the NPU module of the RK3588 processor is combined with the INT8 quantitative model, so that the power consumption is lower than 10W under the 6TOPS computing power; a dynamic multi-thread scheduling mechanism is designed, parallel processing of more than eight paths of video streams is supported through binding of a priority queue and an NPU core, and end-to-end delay is compressed to be within 200 ms; a zero-copy video stream architecture is constructed, data transfer is eliminated through memory mapping, and preprocessing time consumption is reduced by 90%; an energy efficiency control module is integrated, the NPU voltage frequency is dynamically adjusted according to the load, and the energy efficiency ratio reaches 0.83 TOPS / W; space-time alignment of multi-model reasoning results is realized by adopting a frame ID synchronization technology, and the mismatching rate is lower than 0.1%.

The invention discloses a national secret algorithm data encryption transmission method and system. The method comprises the steps of obtaining to-be-encrypted data and network parameters, establishing a Bayesian network probability ablation model, performing Monte Carlo sampling ablation national secret encryption and evaluating attack risks, and generating a probability security encryption strategy; and extracting a Brinell feature set, constructing a long and short-term memory network time prediction model, and optimizing by using a simulated annealing algorithm to obtain an optimal encryption parameter configuration sequence. Generating a key pair according to the sequence and SM2, establishing a shared key by means of an elliptic curve Diffie-Hellman protocol, deriving an SM4 session key through SM3, and establishing a hybrid encryption key system; constructing a teacher and student network model, optimizing multi-thread scheduling through adversarial distillation training and a retrieval enhancement technology, and generating a multi-thread parallel encryption architecture; and network parameters are monitored in real time, a reinforcement learning adaptive decision engine is constructed, a strategy is dynamically adjusted, and adaptive encryption transmission is completed. According to the invention, the optimal balance between the security and the efficiency in the data encryption transmission process is realized.

One embodiment provides a multi-chiplet graphics processor comprising a plurality of chiplets, where a chiplet of the plurality of chiplets comprise a memory interface, processing resources configured to execute threads of a kernel, and thread dispatch circuitry to facilitate dispatch of threads of the kernel to the processing resources. The processing resources are configured to execute threads of a first kernel, receive dispatch of threads of a second kernel for execution before completion of the first kernel as threads of the first kernel retire, execute a first phase of the second kernel during completion of execution of the first kernel, via a thread of the first kernel, signal an event via an uncached write to a global memory, and execute a second phase of the second kernel based on detection of the event via an uncached read from the global memory.

Techniques are provided to enable mid-thread (instruction level) preemption in a graphics processor without requiring software intervention by a graphics driver associated with the graphics processor. Hardware based mid-thread preemption is facilitated using the thread dispatch hardware of the graphics processor to trigger execution of a kernel program by the graphics processor that saves the thread state of preempted processing resources and facilitates the subsequent restoration of that thread state to the same or a different set of processing resources.

The invention provides an edge heterogeneous Internet of Things operation and maintenance chassis data processing method and system. The method comprises the following steps: firstly, according to the types of the multi-source heterogeneous terminals, formulating a unified data acquisition scheme, defining a unified acquired data format, respectively managing and executing a data acquisition task of each multi-source heterogeneous terminal by adopting an asynchronous multi-thread scheduling mechanism, and acquiring and generating corresponding acquired original data; and performing standardization processing on the collected original data in the normal sampling state to generate a multi-source collected data set. And then, according to the type of each multi-source heterogeneous terminal, for the corresponding multi-source acquisition data set, calculating a standardized anomaly score, performing weighted comprehensive processing, generating a comprehensive anomaly score, and determining an anomaly level according to the comprehensive anomaly score. And finally, correspondingly matching the exception level of the multi-source heterogeneous terminal with a preset local protection strategy, executing a local exception protection action based on a matching result, recording exception information and reporting exception alarm information to a remote center platform.

Embodiments of the present disclosure provide a thread scheduling method, apparatus, processor, and computer-readable storage medium. The thread scheduling method includes: obtaining a plurality of threads to be scheduled for object resources in a processor, and obtaining the current occupation quantity and reservation quantity of each of the plurality of threads for the object resources respectively; based on the current occupation quantity and reservation quantity of each of the plurality of threads for the object resources respectively, selecting a target thread that meets the scheduling conditions from the plurality of threads for scheduling. The thread scheduling method and apparatus can, on the premise of ensuring fairness among multiple threads, prevent a certain thread from starving and improve the overall design robustness.

The invention discloses an NUMA (Non Uniform Memory Access) architecture perceived high-scalability learning index construction method and system and an operation method. According to the construction method, a mixed node tree structure is adopted to organize data, the structure comprises internal nodes accurately searched by a linear model and leaf nodes for storing data, the leaf nodes are composed of ordered gap nodes and segment nodes, and the segment nodes support dynamic evolution from an ordered stage to a semi-ordered stage based on data density. Conflict data is managed using hierarchical benchmark buckets. According to the system, a self-adaptive node evolution mechanism based on an operation cost model is realized, index performance is optimized through node reconstruction triggered by foreground write operation and background hot and cold node compression, a multi-thread concurrency control strategy is adopted, and a memory management and thread scheduling framework perceived by NUMA is adopted. The operation method provides an efficient point query and point insertion operation process. The data layout can be dynamically optimized, the operation cost is reduced, and the method is suitable for high-performance database and memory management scenes.

The invention relates to a self-adaptive optical matrix calculation acceleration method based on an ARM framework, and belongs to the field of self-adaptive optical wavefront correction technology and embedded parallel calculation. The method comprises the following steps: analyzing a mathematical mapping relationship between a microlens array and wavefront phase distribution in a Hartmann sensor image, and constructing a wavefront matrix operation model based on an ARM multi-core architecture; designing a Hartmann image data rearrangement strategy, dividing a single-frame Hartmann image into multiple task calculation units, and realizing parallelization processing of wavefront slope calculation; a wavefront matrix operation kernel is optimized according to ARM NEON instruction set characteristics, and vectorization calculation of multi-channel wavefront reconstruction is realized by adopting an SIMD parallelization technology; and computing resource allocation is coordinated through a dynamic thread scheduling algorithm, and the task allocation proportion among multiple cores is adjusted according to the real-time load condition. According to the method, the wavefront calculation efficiency is remarkably improved, so that the overall bandwidth of the adaptive optical system is greatly improved.

The invention relates to the technical field of state recognition, in particular to an Android device remote state monitoring and intelligent operation and maintenance system which comprises an event trigger analysis module, a state feature classification module, a state section plotting module, a state fragment packaging module and a state level response module. In the method, a state path set is constructed through time label alignment of broadcast and thread events, an access source mark and a network return parameter are combined to generate a multi-dimensional state label sequence, a thread scheduling track and a memory block are mapped to form a state section structure, and an active boundary area is positioned in combination with power consumption change. Path numbers and permission information are combined, screened and packaged into a structured state unit, response level zones are divided through the number depth and the repetition rate, and complete restoration of behavior paths and accurate recognition of state nodes under the scenes of concurrent calling, complex event chains and the like are supported. And the granularity of terminal state analysis, the traceability continuity and the hierarchical adaptation capability of operation and maintenance response are remarkably improved.

The invention discloses a method for ensuring hard real-time in a Linux user mode based on a multi-core CPU, and belongs to the technical field of embedded systems. According to the method, a Linux kernel is configured to be in a completely preemptable mode, user threads with the number equal to that of CPU kernels are created and bound to different kernels, a real-time scheduling kernel is selected, the thread scheduling strategy of the real-time scheduling kernel is set to be SCHEDFIFO, the priority of the real-time scheduling kernel is equal to that of the lowest-priority soft interrupt, the thread stack space is locked, the real-time kernel is isolated through kernel parameters isolcplus and nohzfull, and the cost of tick is avoided. Finally, the real-time core is exclusively used for executing the real-time task. According to the scheme, the problem that the real-time performance of the Linux user state task is poor due to the fact that a kernel cannot be preempted, scheduling delay, memory page changing, system interference and the like is effectively solved, and extremely low delay and high certainty of user state task response are ensured through multi-level collaborative optimization.

The present disclosure provides a runtime virtualization method and apparatus. A specific implementation of the method includes: constructing a dynamic runtime library based on the native runtime library of an application, where the dynamic runtime library simulates threads implemented in the native runtime library in a coroutine manner; loading the dynamic runtime library when starting the application to generate a runtime virtualization environment and a coroutine scheduling thread running in the runtime virtualization environment, where the coroutine scheduling thread is used to schedule coroutines, and the runtime virtualization environment is an environment after replacing the native runtime library with a generated runtime environment; receiving a task request of the application in the runtime virtualization environment; and scheduling coroutines using the coroutine scheduling thread based on the task request and the dynamic runtime library so that the coroutines complete the tasks corresponding to the task request. This implementation improves the concurrency performance of the application, reduces resource consumption and resource scheduling pressure without making any modifications or recompiling to the application in the target operating system.

The invention belongs to the technical field of computer operation scheduling, and particularly relates to a GPGPU thread scheduling method and system, a terminal and a storage medium, and the method comprises the steps that an external host ranks calculation tasks according to the priorities of the calculation tasks, and sends a scheduling instruction to a GPGPU according to the ranking; the GPGPU divides a calculation task corresponding to each calculation core into a plurality of task blocks according to the scheduling instruction; the GPGPU configures a main thread bundle and a plurality of slave thread bundles for each task block according to the scheduling instruction, the main thread bundles are used for scheduling and activating the slave thread bundles, and the slave thread bundles are used for executing the computing tasks scheduled in the scheduling instruction after being activated. According to the method, parallel processing of tasks and effective utilization of resources are achieved, and the situation that the resources are idle is avoided.

The invention provides a real-time high-frequency sensor data acquisition system, which comprises an acquirer firmware program and an upper computer software program, and is characterized in that the acquirer firmware program acquires sensor data according to set integral time, encapsulates data acquired in a single or segmented manner into a private message format, and sends the data to an upper computer in real time through a communication module. The upper computer software is provided with a high-priority communication receiving thread and is used for receiving the segmented data messages, splicing the segmented data messages into complete frame data and storing the complete frame data into a first-level cache region; the system further comprises a plurality of data processing threads and corresponding second-level cache regions, and the data processing threads are used for processing frame data in parallel. The system supports sensors in different acquisition modes, has high-frequency data acquisition capability, improves data processing efficiency through dynamic thread scheduling, and solves the problems of data frame loss and incapability of real-time processing in a traditional architecture.

The invention discloses a memory key value storage system thread scheduling method and device and a medium. According to the method, a system is organized into a two-layer architecture of a cache resident CR layer and a memory resident CR layer. Uniformly receiving and shunting all the requests by the CR layer; quickly processing the cached requests in the CR layer in a non-blocking manner; and the missed requests are forwarded to the MR layer in a non-blocking manner through the efficient communication queue. And after the MR layer processes the request, the completion signal is efficiently synchronized back to the CR layer by updating an implicit notification mechanism of the queue state identifier. According to the method, by effectively isolating tasks with different access characteristics, the CPU cache utilization rate is remarkably improved, load balance and low synchronization overhead under high concurrency are taken into account, and the overall performance and expandability of the system are improved.

The invention discloses an electric connector detection system and method based on vision, and belongs to the field of machine vision and industrial detection, and the system comprises a large constant water star series industrial camera, a multi-angle and high-uniformity adjustable light source system, a product feeding moving and packaging mechanism, a computer control system and UI software. Wherein the computer control system adopts multi-thread scheduling, a modular architecture and a sub-pixel-level algorithm, and supports high-throughput processing of 3-6 4024 * 3036 pixel industrial cameras, an image acquisition module of the computer control system can uniformly manage multiple models of cameras, and a UI (User Interface) is a drag-and-drop interface and integrates debugging tools such as OpenGL (Open Graphics Library) and parameter hot loading; the method comprises the steps of hardware configuration, trigger starting, image acquisition, positioning correction, ROI drawing, detection, reference line determination, size measurement and sorting control, ROI drawing can adapt to regular and irregularly arranged pins, the adaptability is high, the precision is high, operation is convenient and fast, full-process automatic detection can be achieved, and the requirement of a high-speed production line is met.

The invention discloses a smart city data processing method based on Beidou positioning, which relates to the technical field of electric digital data processing, and comprises the following steps: collecting data from a Beidou positioning module and an auxiliary sensor, and preprocessing the collected data; and performing event detection on the preprocessed data, and executing intelligent response operation according to an event detection result. And performing data integrity verification and privacy protection based on a cryptographic algorithm on the data. A data processing task is divided into a plurality of sub-tasks, parallel processing is carried out on the sub-tasks at the same time on a multi-core processor or a distributed computing platform through a multi-thread scheduling algorithm, and processing resources are distributed to the sub-tasks according to a dynamic scheduling strategy. And performing time sequence analysis on the historical data and the real-time data, and constructing a prediction decision model. According to the method, on the basis of a traditional data processing technology, comprehensive analysis and prediction of various sensor data of a city are realized by introducing multi-model hybrid prediction, meta-model dynamic weight calculation and residual correction.

The invention discloses a thread scheduling method and device, electronic equipment and a storage medium, and belongs to the technical field of operating systems. The method comprises the steps that a DSM PF event of a virtual machine is monitored, and the DSM PF event is triggered when a plurality of threads access the same shared memory page in a cross-node mode; according to the DSM PF events, an inter-thread incidence matrix is constructed, and the inter-thread incidence matrix is used for quantifying the number of times of triggering the DSM PF events between any two threads; the thread graph structure is divided to generate a thread grouping scheme with the aim of minimizing the number of DSM PF events between different grouping threads, the vertex of the thread graph structure represents the threads, and the adjacency matrix of the thread graph structure is the incidence matrix between the threads.

Techniques are provided to enable mid-thread (instruction level) preemption in a graphics processor without requiring software intervention by a graphics driver associated with the graphics processor. Hardware based mid-thread preemption is facilitated using the thread dispatch hardware of the graphics processor to trigger execution of a kernel program by the graphics processor that saves the thread state of preempted processing resources and facilitates the subsequent restoration of that thread state to the same or a different set of processing resources.

The invention discloses a thread scheduling method, electronic equipment, a storage medium and a program product, and relates to the technical field of computers, security check is performed on a source thread and a target thread through a thread switching request initiated by the source thread, an allocatable time period of the source thread allocated to the target thread is calculated according to a security detection result, and the allocatable time period of the source thread allocated to the target thread is sent to the electronic equipment. Bypassing a processing mechanism of a completely fair scheduler, updating the virtual running time of a source thread, distributing an allocable time period to a target thread, calling a context switching function to execute thread switching operation on the source thread and the target thread, and synchronously updating the virtual running time of the target thread when the target thread consumes the allocable time period. According to the thread scheduling method and device, the problem that in the related technology, when a complete fair scheduler processes high-frequency and collaborative thread tasks, due to the indirect handover mechanism and fair scheduling characteristics of the complete fair scheduler, the delay of thread scheduling is improved is solved, and the delay of thread scheduling is reduced.

The invention discloses a DCU architecture-oriented sparse triangle solution dynamic load balancing method and device and a medium, and relates to the technical field of high-performance computing. The method comprises the following steps: rearranging a row sequence of a sparse matrix according to a dependency relationship; wherein the dependency relationship is determined according to an external dependency item and an internal dependency item of the thread block; and based on the sparse matrix of the rearranged row sequence, dividing the sparse matrix into a plurality of sub-matrixes according to the size of a thread scheduling unit, and determining a solving strategy according to the number of average non-zero elements in each sub-matrix. On one hand, the line dependency relationship of the sparse matrix is analyzed and rearranged in the preprocessing stage, so that calculation tasks are more uniformly distributed among DCU threads, and the situation that part of threads enter a waiting state due to the fact that data dependency is not met is reduced. On the other hand, the most suitable solving mode is dynamically selected according to the number of the non-zero elements in each row, and the calculation efficiency of overall solving is greatly improved.

The invention discloses an intelligent interconnection system based on multiple communication modes, and relates to the field of communication, the intelligent interconnection system comprises a sensing layer, a network layer and an application layer, LiteOS is a real-time operating system and supports thread scheduling, multiple communication protocols support mainstream protocols such as CoAP, MQTT, LoRa and NB-IoT, and the intelligent interconnection system has relatively high performance in the aspect of connection stability and can be applied to the field of communication. According to task management and communication scheduling, access of multiple types of equipment is completed through task management and communication scheduling, and efficient transmission and processing of data are ensured. According to the intelligent interconnection system based on the multi-communication mode, the designed multi-protocol gateway system is oriented to sensor data acquisition in automatic scenes such as a production automatic control workshop, a machine tool detection technology and information processing, and gateway equipment can be used as a data acquisition terminal and also can be used as an edge gateway; modularized development is adopted, a lightweight real-time operating system LiteOS is used, log export is supported, and a user can remotely control equipment and locally operate the equipment.

The invention relates to the technical field of data communication, and discloses a data communication method and device for a robot system and a robot. The method comprises the following steps: when a data acquisition agent module monitors that business data is written into a shared memory area, acquiring the business data from the shared memory area; caching the business data according to the data type of the business data; and acquiring a network state of the robot system, and uploading the cached service data to a server or locally storing the cached service data according to the network state and the data type of the service data. Through a data acquisition and cache uploading separation mechanism, the problems of high occupation of data communication bandwidth, conflict between real-time performance and flexibility, high thread scheduling load and the like in an existing robot system are solved, and the communication efficiency and the data management capability of the system are remarkably improved.

The data processing method comprises the steps that a consumer thread in N consumer threads processes data sent by at least one producer in M producers; wherein the data sent by one producer is processed by one consumer thread, and M is an integer greater than or equal to N; when the processing unit corresponding to the first consumer thread for processing the data sent by the first producer in the M producers meets the condition, the second consumer thread in the N consumer threads takes over the first consumer thread to process the data sent by the first producer. The method can save thread scheduling overhead.

The invention discloses a thread scheduling priority processing method and display equipment, and the method comprises the steps: marking a key thread corresponding to a target method under the condition that the target method is detected to be called in the operation process of the display equipment; obtaining an execution state of the marked key thread; under the condition that execution of the marked key thread is completed, obtaining a thread wake-up chain where the marked key thread is located, and performing priority improvement on threads behind the marked key thread in the wake-up chain; and under the condition that the marked key thread is not executed completely, acquiring a lock queue of data resources operated by the marked key thread, and performing priority improvement on threads ranked in front of the marked key thread in the lock queue. And the response speed of the interaction operation corresponding to the target method is improved.

The present disclosure provides a database thread pool control method and apparatus. A specific implementation of the method includes: loading a dynamic runtime library capable of replacing threads with coroutines in the operating system of the database to generate at least one coroutine scheduling thread; receiving a connection request sent by a client to the database; detecting whether a request for the database to create a new thread is a request for processing the connection request; in response to detecting that the request for the database to create a new thread is a request for processing the connection request, creating a coroutine corresponding to the connection request, and scheduling the coroutine through at least one coroutine scheduling thread to complete the access task corresponding to the connection request. In this implementation, the coroutine scheduling thread serves as the working thread of the database thread pool, and the task "starvation" problem of the traditional multithreaded scheduling model and its related task response speed jitter problem are avoided by using the coroutine swap-in and swap-out mechanism. While improving the database concurrency performance, the resource consumption of concurrent scheduling is reduced.

Devices and techniques for thread scheduling control and memory splitting in a processor are described herein. An apparatus includes a hardware interface configured to receive a first request to execute a first thread, the first request including an indication of a workload; and processing circuitry configured to: determine the workload to produce a metric based at least in part on the indication; compare the metric with a threshold to determine that the metric is beyond the threshold; divide, based at least in part on the comparison, the workload into a set of sub-workloads consisting of predefined number of equal parts from the workload; create a second request to execute a second thread, the second request including a first member of the set of sub-workloads; and process a second member of the set of sub-workloads in the first thread.

Bank aware thread scheduling and early dependency clearing techniques are described herein. In one example, bank aware thread scheduling involves arbitrating and scheduling threads based on the cache bank that is to be accessed by the instructions to avoiding bank conflicts. Early dependency clearing involves clearing dependencies for cache loads in a scoreboard before the data is loaded. In early dependency clearing for loads, delays in operation can be reduced by clearing dependencies before data is required from the cache.

The invention relates to the technical field of laboratory control, in particular to a multitask parallel experiment system and method for a laboratory, and the system comprises a task management module which is used for receiving and splitting a plurality of experiment plans submitted by a user, and obtaining a plurality of experiment tasks corresponding to the experiment plans; the task constraint module is used for performing condition constraint on the experiment task according to the constraint rule to obtain a constraint experiment task with a constraint condition; the material detection module is used for acquiring material container resource information of the experiment platform, performing material container resource detection on the constraint experiment task according to the material container resource information, and generating a resource satisfaction signal; and the multi-task scheduling module is used for constructing a multi-thread scheduling strategy based on the thread pool management mechanism and the resource satisfaction signal, and scheduling the execution module to execute a plurality of experiment plans according to the multi-thread scheduling strategy. The utilization rate of experimental resources can be optimized, so that the execution efficiency of experimental tasks and the stability of experimental operation are improved.

The invention relates to the technical field of medical information parallel computing, in particular to a multi-thread parallel computing method and system for Brucella spondylitis diagnostic parameters, and the method comprises the following steps: a diagnostic task dependency graph construction step: constructing a directed acyclic graph based on the computing dependency relationship of the diagnostic parameters and determining the task priority; a self-adaptive thread scheduling step: adopting a work stealing strategy and a lock-free concurrent queue to realize dynamic load balancing; a vectorization parallel computing step: performing batch computing on the diagnosis parameters by using a single-instruction multi-data-stream instruction; and a feedback driving optimization step: dynamically adjusting a scheduling strategy according to performance indexes to form closed-loop optimization, and deeply coupling the four core modules to realize synergistic interaction.