121 results about "Load instruction" patented technology

The invention provides an RISC-V vector data loading instruction processing method and a processor, and relates to the technical field of processors. When a vector loading instruction is transmitted, memory access address calculation and memory access can be started in advance only by making a source operand ready, and waiting for an old value of a target vector register is not needed, so that transmission blocking caused by dependence of the old value is avoided; by temporarily storing loaded data in a vector data buffer area, memory access operation and subsequent merging write back are decoupled, and memory access delay and old value ready waiting time are overlapped; and when the instruction becomes the oldest to-be-written-back instruction and an old value is ready, the merging unit merges new and old data element by element according to the mask and vector configuration to ensure correct implementation of RISC-V vector extension complex semantics. On the premise of not influencing the function correctness, the memory access delay is effectively hidden, the instruction level parallelism is improved, and the processing efficiency of the vector loading instruction is remarkably improved.

The invention provides a supercritical unit low-load deep peak regulation system and method, and relates to the field of thermal generator sets, and the supercritical unit low-load deep peak regulation system comprises an instruction analysis and pre-control module, an energy redistribution module, a combustion steady-state module, a parameter cooperation module and a state backtracking and self-gain module. According to the application, through the arranged instruction parsing and pre-control module, the power grid load instruction is parsed and converted into a set of accurate equipment action time sequence list, the instruction feature recognition unit in the instruction parsing and pre-control module performs mode recognition on the load instruction, and the strategy generation unit calls the preset strategy template according to the mode, so that the power grid load instruction is analyzed and converted into the accurate equipment action time sequence list. Action instructions which face all execution units of the whole system and are arranged in a wrong sequence on a time axis are generated, and conversion from passive response to active pre-control is achieved.

The invention relates to the technical field of resource cache management, and discloses a page cache-based page loading method and device, electronic equipment and system.The method comprises the steps that after it is detected that a network agent tool meets a preset operation condition, a network request is intercepted through a capture event monitor of the network agent tool, and the network request is loaded to the electronic equipment; if the network request does not meet the special processing condition, judging whether the network request contains a target resource request, and if so, executing a resource response operation according to a resource loading strategy corresponding to the target resource request contained in the network request to obtain a first resource; otherwise, loading a second resource required by the network request through the network based on a preset network loading instruction; and displaying the target resource obtained by loading on the current page. Therefore, by implementing the method and the device, different resource loading and caching strategies can be adopted for different types of page resources, adaptive page caching is realized, the loading efficiency and stability of the page resources are improved, and the page browsing experience is improved.

A widening vector load instruction specifies at least one address operand and two or more vector destination registers, e.g. Z1 and Z2, each for specifying a vector operand having a given vector lengt

The invention relates to a low-overhead processor cache micro-architecture defense method and device and computer device.The low-overhead processor cache micro-architecture defense method comprises the steps that when a missing state keeping register module takes out a loading instruction waiting for data from a replay queue, a target branch mask of the loading instruction is obtained; the replay queue is used for storing an instruction which is stagnated due to miss of the cache; judging whether the loading instruction is in a speculative execution state or not according to the target branch mask; and when the loading instruction is in the speculative execution state, stopping a cache write-in operation corresponding to the loading instruction. Through the method and the device, the problem of sensitive information leakage caused by incapability of defending against the cache side channel attack is solved, defending against the cache side channel attack is realized, and sensitive information leakage is prevented.

The invention relates to a multi-core processor memory consistency verification method and device, the method is executed by a memory model in a processor co-simulation verification architecture, and the method comprises the following steps: monitoring a storage instruction of each processor core in an RTL, and maintaining a storage queue for each processor core based on the storage instruction; in response to a data request initiated when the ISS executes the loading instruction, speculating a set of compliance values possibly read by the loading instruction based on the storage queue and the visible relation of the storage instructions between the maintained different processor cores; comparing the actual read data of the loading instruction obtained from the RTL with the set of compliance values; and if the actually read data is in the set of compliance values, determining that the memory consistency verification of the multi-core processor is compliant. Therefore, an RISC-V multi-core processor memory consistency verification scheme which can be integrated in a front simulation environment, supports real-time accurate verification and has high coverage is provided.

The invention relates to a processor and a memory access method. The processor comprises a UAV instruction sending unit, a UAV register management unit, a general register unit, a UAV data caching unit and a loading storage unit; the loading storage unit is configured to receive an SIMD instruction; reading resource information of the target UAV register from the UAV register management unit according to the address information of the target UAV register; under the condition that the SIMD instruction is determined to be a loading instruction according to the operation code, reading channel logic address information of each channel from the general register unit; under the condition that the memory addresses to be accessed by the multiple channels of the SIMD instruction are judged to be continuous, calculating the memory access address of the first channel, and calculating the memory access addresses of the other channels based on the memory access address of the first channel; and generating a memory access request based on the memory access address of each channel. According to the method, the throughput rate of the loading storage instruction of the continuous address is improved, the number of ALUs calculated by the memory address is reduced, and meanwhile, the power consumption is reduced.

The application discloses a control system for improving load response rate of a coal-fired thermal power unit under an ACE mode, which comprises a PID controller with feedforward, a first adder, a first analog AI input module, a second analog AI input module, a first analog AO output module, a second adder, a third analog AI input module, a fourth analog AI input module and a fifth analog AI input module; the output end of the fourth analog AI input module and the output end of the fifth analog AI input module are connected with the input end of the second adder, the output end of the third analog AI input module and the output end of the second adder are connected with the input end of the first adder, and the output end of the first analog AI input module, the output end of the second analog AI input module and the output end of the first adder are connected with the input end of the PID controller with feedforward; the system can realize the purpose of fast response of the coal-fired thermal power unit to load instruction change.

The invention relates to the technical field of power system automation and control, in particular to an automatic load adjusting system and method suitable for power spot transaction. The invention relates to an automatic load adjustment system suitable for electric power spot transaction and a power generation spot transaction platform system, which are used for providing real-time clearing results and pre-clearing results including a plurality of time points in the future. The data acquisition and release system is used for converting the clearing result into a power value per minute of a time sequence; the centralized control center computer monitoring system is used for generating a load set value; the power station control unit is used for automatically adjusting the output of the corresponding power generation unit; and the security I area communication gateway is used for realizing data communication with the data acquisition and release system in the security II area. The electric power spot transaction platform is deeply integrated with the power plant monitoring system and the AGC system, so that the whole process automation from acquisition of clearing results to issuing of load instructions and final execution is realized, the labor intensity of operators is greatly reduced, and the overall operation efficiency is improved.

A method of an aspect includes predicting a value that a load instruction of a first iteration of a loop would load and executing a plurality of instructions occurring after the load instruction in the first iteration of the loop to generate a plurality of results. Each of the plurality of results depends only on the value, one or more constant values, values derived from the value and / or the one or more constant values, or any combination thereof. The method also includes producing the plurality of results for the plurality of instructions during each of one or more iterations of the loop after the first iteration without re-executing the plurality of instructions. Other methods, apparatus, and systems are also disclosed.

A processor includes a time counter and issuing instructions and executing instructions at a future time, which is based on the time counter. The execution times are based on fixed latency times of instructions, with the exception of the load instruction, which is based on the data cache hit latency time. A data cache miss causes the load instruction to fetch data from the level 2 cache, wherein a time tracker unit adjusts the level 2 cache latency time based on a counter.

An apparatus and method for eliminating load instruction execution. For example, one embodiment includes: circuitry to track execution of a plurality of load instructions and responsively update tracking tables; allocation circuitry to allocate a first source register to an instance of the first load instruction and to identify locations of the corresponding data elements in the cache line based on the tracking tables; execution circuitry to load data corresponding to the instance of the first load instruction from the cache line and to load the data elements corresponding to instances of the subsequent load instructions to the same source register; the allocation circuitry to indicate the first source register to the instances of the subsequent load instructions and respective locations of the data elements in the first source register, the instances of the subsequent load instructions to move the respective data elements from the first source register to destination registers.

This invention discloses a BIM building model construction method for architectural engineering design, specifically relating to the field of electronic digital data processing technology. First, based on spatial boundary vertices, a mapping table is established between memory page identifiers and physical addresses for each node. Based on this mapping table, a dynamic preloading instruction set is generated using a viewpoint prediction algorithm. Based on the mapping table and the dynamic preloading instruction set, a dynamic attribute graph model is generated, followed by another dynamic attribute graph model. Based on the dynamic attribute graph model, a final optimized attribute graph model is obtained, and finally, a BIM building model is constructed. This invention utilizes graph neural network semantic mapping to achieve unified attribute graph representation of heterogeneous data from multiple disciplines, improving the accuracy of semantic mapping. Simultaneously, it uses graph convolutional networks to achieve real-time detection of design conflicts, combined with a bidirectional feedback mechanism to achieve real-time conflict correction, solving the problem of lagging offline detection in existing methods.

A method for processing tasks in parallel is performed by at least one processor, and includes performing a first task associated with a first instruction, determining whether the first instruction is a burst load instruction, in response to determining that the first instruction is the burst load instruction, acquiring a second instruction, and performing a second task associated with the acquired second instruction, in which the first task and the second task are performed in parallel.

The application discloses a steam turbine main control auxiliary pressure regulating control system and control method under variable load conditions, which comprises a unit load instruction forming loop, a steam turbine main control load set value forming loop and a steam turbine main control instruction forming loop; the steam turbine main control load set value forming loop is composed of a primary frequency modulation load instruction input, a main steam pressure deviation correction loop and a steam turbine load instruction forming loop; the main steam pressure deviation correction loop and the steam turbine main control load set value forming loop together with the primary frequency modulation load instruction constitute a steam turbine main control regulator set value; the steam turbine main control regulator performs PID operation according to the set value and an actual load to obtain a steam turbine main control instruction; and the unit load instruction forming loop independently acts on a boiler side control system. The application improves the unit load change rate and reduces the main parameter fluctuation of the unit under the premise of ensuring the stability of the main steam pressure by means of fuzzy control and predictive control technology, and meets the requirement of the power grid for fast response to the load.

The invention discloses an SNCR regulation and control method adaptive to flexible peak regulation operation, and the method comprises the steps: monitoring the load instruction change of a thermal power generating unit, and starting a control strategy in advance according to a preset time threshold value after a target load instruction is detected; calculating the total reducing agent output adjustment amount of the SNCR system according to a preset proportional relation in a control strategy based on the target load variation; according to the corresponding relation between the target load value and a preset load interval, the output proportion of spray guns in the separator inlet flue side wall area A1, the separator inlet flue top area A2 and the separator and tail flue area B is dynamically distributed; and combining the total output adjustment amount with the subarea output proportion, generating a flow set value of each spray gun, driving an adjusting valve to execute accurate spraying, and recovering a monitoring state after control circulation is completed. According to the method, a set of multi-dimensional cooperative control strategy is formed through advanced intervention in time and partition differentiation adjustment in spatial position, and the problem that the denitration efficiency is reduced when the load of the traditional SNCR is dynamically changed can be solved.

The application relates to the field of boiler combustion technology, in particular to a combustion and water supply control method suitable for load change. The method comprises the following steps: obtaining a load instruction, setting a control mode and a boiler load change value according to the load instruction and a real-time load value; setting a boiler water supply parameter and a boiler coal feeding parameter according to the control mode and the boiler load change value; obtaining a steam turbine pressure fluctuation value, and correcting the real-time water supply parameter and the coal feeding parameter according to the steam turbine pressure fluctuation value. Different control modes are set through the boiler load change value, so that the operation parameters of the boiler can be corrected in time when the load instruction suddenly decreases or suddenly increases, the problems of underpressure or overpressure caused by long adjustment time are avoided, and the problem that the stable operation of the boiler is affected is solved.

The invention discloses a processor and a data processing method, and relates to the technical field of data processing.The processor comprises a processor core, a first-level cache unit and a data rapid obtaining module; the processor core is used for obtaining an instruction for accessing the first-level cache unit and determining the number of times of accessing the first-level cache unit based on the access data volume; the instruction and the number of times are sent to the data rapid acquisition module; the data rapid acquisition module is used for receiving instructions and times sent by the processor core; generating a virtual cache block based on the number of times and an access initial address in the instruction; the virtual cache block comprises a plurality of cache blocks which are continuous with the target cache block corresponding to the access head address; and based on the instruction, synchronously accessing a plurality of cache blocks in the virtual cache block, so as to synchronously write the first target data into the plurality of cache blocks when the instruction is a storage instruction, or synchronously read the second target data from the plurality of cache blocks when the instruction is a loading instruction, and send the second target data to the processor core.

[Problem] To provide an InO processor with which it is possible to improve processing performance.. [Solution] According to one aspect of the present invention, there is provided a processor for executing sequentially issued instructions through pipelining, the processor comprising: a fetch unit for fetching an instruction from a memory that is set to a program counter; a decoding unit for decoding the instruction fetched by the fetch unit; a speculative issuance prediction unit for predicting, on the basis of reference information including a correlation between information for identifying a load instruction and speculative issuance possibility, whether the load instruction fetched by the fetch unit is can be speculatively issued; a queue control unit for holding instructions decoded by the decoding unit in an instruction queue, and, while sequentially issuing the instructions held in the instruction queue, performing advance issuance to issue a speculatable load instruction that is predicted to be speculatively issuable by the speculative issuance prediction unit prior to an instruction held in the instruction queue earlier than the speculatable load instruction; and a computation execution unit for executing the instructions issued by the queue control unit and writing the execution results to a register.

The present disclosure provides a data loading method, device, processor, electronic equipment and storage medium. The method comprises: obtaining a loading instruction for loading a to-be-processed tensor from a first memory to a second memory; determining a shape size of the to-be-processed tensor and an initial starting coordinate in a coordinate system determined by the to-be-processed tensor; starting from the initial starting coordinate, executing the loading instruction by sequentially executing Z sub-instructions, wherein for the i-th sub-instruction in the Z sub-instructions, the following operations are performed: returning data of the i-th data block starting from the data block starting coordinate, so that the data in the i-th data block is stored continuously in the second memory, and determining the data block starting coordinate of the i+1-th sub-instruction based on the data block starting coordinate of the i-th sub-instruction, the size of the data block in each block dimension, and the remaining size of the to-be-processed tensor in the corresponding each tensor dimension.

The present application belongs to the technical field of man-machine interaction of numerical control machine tools, and relates to a monitoring method and system for IO point state of a Siemens numerical control machine tool, which comprises the following steps: exporting a point information table from an electrical design software, screening out target points and corresponding point descriptions related to numerical control machine tool monitoring; performing preprocessing and sorting; grouping according to grouping rules, generating a number and writing into a text file; calling a loading instruction to read the text file during the loading process of a man-machine interface, and performing page binding; and displaying and refreshing according to the state of a page register during running. The technical scheme of the present application realizes unified management and dynamic display of point data by preprocessing, grouping numbering and external file loading, in combination with page binding and register control, and can meet the needs of efficient implementation of point data standardization processing, dynamic page display and refreshing of a man-machine interface.

The invention discloses a radar signal processing instruction data parallel processing method based on a super-long instruction word, and aims to solve the problems of resource waste and insufficient real-time performance caused by an NOP instruction. According to the method, an algorithm instruction loop structure is analyzed, and a data dependency relationship and an instruction delay depth are identified; segmenting continuous radar data and distributing an independent base address register for each segment to realize parallel processing; loading instructions of other segments are executed in a delay period waiting for loading of one data segment through interleaving scheduling of the data loading instructions; performing cross-segment interleaving arrangement on the processing instructions of the plurality of data segments, inserting the processing instructions of the subsequent segments into the delay waiting period of the instructions of the previous segments for execution, and packaging the plurality of instructions without the dependency relationship into the same VLIW instruction packet; and a pipeline closed loop of loading, calculation, comparison and storage is maintained through cycle control. According to the method, the instruction transmitting efficiency, the hardware resource utilization rate and the data processing throughput are remarkably improved.

This disclosure relates to methods and apparatus for computational processing. For example, the disclosed techniques facilitate improved performance of matrix multiplication in streaming processors. Aspects of this disclosure may utilize a load control unit to execute a first load instruction to load an input dataset of an input matrix from a first memory to a second memory. Aspects of this disclosure may also utilize a load control unit to execute a second load instruction to load a weight dataset of a weight matrix from the first memory to the second memory. Furthermore, aspects of this disclosure may utilize an ALU component to perform matrix multiplication operations using the input dataset and the weight dataset to generate an output matrix. Additionally, aspects of this disclosure may store the output matrix in a general-purpose register accessible to the ALU component.

The present application relates to the technical field of thermal automatic control, and particularly relates to a kind of auxiliary machine fault load reduction test method, device, computer equipment and medium.Method includes: when unit auxiliary machine fault load reduction occurs, generating control load instruction;Target load ratio is generated based on the ratio of load instruction and boiler load instruction at the moment before unit auxiliary machine fault load reduction occurs;Boiler target load is determined based on the product of control load instruction and target load ratio.In the present application, the ratio of load instruction and boiler load instruction at the moment before RB occurs is calculated to generate target load ratio, then when auxiliary machine fault load reduction occurs, the generated control load instruction and target load ratio are multiplied to obtain boiler target load, so that the target load of RB realizes undisturbed switching to fuel master control, ensures that coal feeder combustion instruction does not jump greatly, and further ensures that each main parameter remains stable under the adverse conditions of unit RB, and the unit does not trip.

The invention discloses a page loading method and device, electronic equipment and a storage medium, and belongs to the technical field of Internet. Comprising the steps that a to-be-called control of a preset control type is determined from a page source code, and the to-be-called control is incompatible with a browser kernel displaying a to-be-loaded page; an extended control object compatible with the interface of the to-be-called control is created, and the extended control object is used for analyzing the calling behavior of the to-be-called control into a loading instruction of page metadata so as to achieve semantic-level replacement of the function of the to-be-called control; in the execution process of the page source code, the extension control object is utilized to respond to a calling request for the to-be-called control, and corresponding page metadata are loaded based on the calling request to complete page rendering. According to the method and the device, the to-be-called control which cannot be originally supported by the local browser is replaced, so that the local browser can normally load the page source code containing the preset control type.

The present disclosure relates to a metadata node upgrading method and device in a distributed cluster, equipment and medium. The method comprises: in response to an upgrading instruction of a metadata node to be upgraded, sending a first loading instruction to a target metadata node; the first loading instruction is used to instruct the target metadata node to load read-only segment metadata in the metadata node to be upgraded at a first loading rate; determining whether the read-only segment metadata is loaded completely, and in the case of determining that the loading is completed, sending a second loading instruction to the target metadata node; the second loading instruction is used to instruct the target metadata node to load read-write segment metadata in the metadata node to be upgraded at a second loading rate, the first loading rate is less than the second loading rate; after receiving a loading completion notification of the read-write segment metadata, upgrading the metadata node to be upgraded. The present disclosure can realize smooth upgrading of the metadata node without affecting the business performance, and improve the user experience.

Provided are systems, methods, and apparatuses for secure in-memory data prefetch for wide-IO NAND memory. In one or more examples, the systems, devices, and methods include allocating a memory region of a first memory type based on an allocation command; receiving, at a controller of the first memory type and from an application of a host, a load instruction configured for a second memory type different from the first memory type; converting a memory address, of the second memory type, from the second memory type to a converted memory address of the first memory type; determining the converted memory address matches a memory address of the memory region; fetching prefetch data from the memory region based on predicting that the application will use the data based on the load instruction; and providing the prefetch data to the application of the host based on the load instruction.

This invention discloses an Aware+Fuzz method for enhancing processor data prefetch security to mitigate cache side-channel attacks, belonging to the field of processor chip microarchitecture design. This method includes an attack awareness module and an observation obfuscation module. During program execution, the attack awareness module dynamically detects key load instructions that may belong to the first stage of a cache side-channel attack and activates the observation obfuscation module. In subsequent program execution, the observation obfuscation module dynamically detects key load instructions that may belong to the third stage of the attack, records and learns the memory addresses probed by the attacker, triggers corresponding prefetching, and obfuscates the attacker's memory observations. The prefetched data disrupts the attacker's judgment of the victim program's memory usage, thereby significantly reducing the attacker's success rate and improving the security performance of the processor system.

A technique for speculatively executing load-dependent instructions includes detecting that a memory sorting consistency queue is full for a completed load instruction. The technique further includes storing data loaded by the completed load instruction into a storage location when the memory sorting consistency queue is full. The technique also includes speculatively executing instructions dependent on the completed load instruction. The technique further includes replaying the load instruction in response to a time slot becoming available in the memory sorting consistency queue. The technique further includes testing for incorrect speculation of data by comparing the load data for the replayed load instruction with the data loaded by the completed load instruction stored in the storage location in response to receiving load data for the replayed load instruction.