23 results about "Cache access" patented technology

This invention discloses an intelligent resource allocation method for energy-aware partitions, belonging to the field of computer architecture and operating system task scheduling technology. The method divides computing resources into multiple independent energy-aware partitions based on the processor cores. It then monitors the energy status parameters of each partition in real time. By parsing the instruction code stream of the tasks to be assigned, the proportion of arithmetic and logical instructions is extracted as instruction mixing features, and the address span of memory access instructions is analyzed to obtain cache access density features. Based on the energy status of the partitions and the computation and memory access characteristics of the tasks, a suitability score for the task relative to each partition is generated, comprehensively reflecting the energy matching degree and hardware resource matching degree. Based on the suitability score and the remaining task acceptance capacity of the partitions, a two-dimensional assignment strategy is used to dynamically map tasks to the core execution in the optimal energy-aware partition. This invention achieves fine-grained matching of computing resources and energy status, optimizing system energy utilization efficiency.

This invention relates to a dynamic voltage and frequency adjustment method for a RISC-V processor core. The method includes: monitoring and recording the critical path time of memory access requests for each missing state processing register to update the global critical path counter; monitoring prefetch instructions and extracting their delay parameters; collecting cache access events based on a time window to calculate bandwidth utilization and dynamically determining a bandwidth threshold according to preset performance parameters; and correcting the global critical path counter value by combining the prefetch delay and the bandwidth threshold, thereby triggering a dynamic voltage and frequency adjustment instruction. This method achieves fine-grained adaptive DVFS for the RISC-V processor core under complex loads, significantly improving energy efficiency and performance stability.

The application relates to a dynamic cache sharding method and device, a storage medium and an electronic device. The method comprises the following steps: when it is detected that a cache system adds or removes a cache shard for capacity expansion or contraction, a cache SDK running in an application program continues to perform a cache access operation on cache data according to an original cache shard rule; a cache management component independently set performs a rehashing calculation based on a target cache shard rule after the capacity expansion or contraction, so as to perform asynchronous migration of the cache data to the target cache shard after the capacity expansion or contraction; and after the asynchronous migration is completed, the cache management component sends a shard rule switching instruction to the cache SDK, so that the cache SDK switches to the target cache shard rule to perform the cache access operation. The application solves the technical problems that cache shards are static and are prone to cause cache break-in and service fluctuation during capacity expansion or contraction.

The embodiment of the present specification provides a cold and hot page statistics method and device, which is applied to a cold and hot page identification module of a memory controller, wherein the cold and hot page statistics method comprises: in response to a memory access instruction sent by a processor, generating an access record for an initial memory page according to the memory access instruction, updating the access times of the initial memory page in a data list according to the access record, and determining a cold memory page or a hot memory page according to the access times of the initial memory page in the data list. By obtaining the memory access instruction sent by the processor, the real memory access can be detected, the cache access is avoided from being regarded as the memory access to perform false statistics, and since each memory access can be recorded by the access record, the probabilistic error in the sampling statistics is avoided, and the accuracy of the cold and hot page identification is improved.

A system for context-sensitive distributed processing and memory optimization in a multi-core computer architecture, wherein the system comprises: a plurality of processor cores arranged within a processor structure and configured to perform computational tasks in parallel; a linking network that operationally connects the plurality of processor cores for data communication; a context capture unit connected to each of the plurality of processing cores and configured to monitor execution parameters such as instruction throughput, cache access behavior, memory latency, and data exchange characteristics between the cores, wherein the context capture unit generates context descriptors that are representative of the runtime execution conditions;a scheduling processor operationally connected to the context capture unit and configured to distribute computational tasks across the multitude of processor cores based on the generated context descriptors; and a memory management unit operationally connected to a hierarchical memory arrangement comprising multiple cache levels and main memory, the memory management unit being configured to dynamically allocate and migrate data segments across the hierarchical memory arrangement according to the context descriptors, thus achieving alignment between task execution and data locality.

The application provides a cache access method, a DRAM cache, a cache management system and a computing device. The cache access method comprises receiving a memory access request, the request specifying a data size to be accessed; determining a corresponding granularity cache area in the DRAM cache according to the data size; and the granularity cache area is obtained by dividing the DRAM cache area according to different granularity sizes. Thus, the corresponding granularity cache area is selected according to the data size of the request, the appropriate cache block can be positioned more accurately, the opportunity of DRAM cache hit is increased, and the memory access delay is reduced. The proportion of useful data in the DRAM cache is improved, and the cache space utilization is improved.

Embodiments of this disclosure provide an instruction processing method and apparatus, a processor, an electronic device, and a storage medium. The instruction processing method includes, in response to identifying a first conditional branch instruction with a back jump from an instruction stream, recording instruction information of the first conditional branch instruction; in response to identifying the first conditional branch instruction with a back jump at least once more, determining that the first conditional branch instruction is an end branch instruction in a loop body instruction and performing a backfilling operation on the loop body instruction, the loop body instruction including at least one second branch instruction other than the first conditional branch instruction; performing the backfilling operation on the loop body instruction includes: backfilling the instruction information of the second branch instruction into an instruction information cache; invoking a branch predictor to obtain first prediction information of the second branch instruction, and backfilling the first prediction information into a branch instruction information cache. This instruction processing method expands the scope of loop body instruction recognition and reduces cache access power consumption.

The application discloses a cache access method and system, a medium and a product, and applies to the technical field of processors, and comprises the following steps: monitoring the memory access behavior of each processor core to a shared cache, each cache line in the shared cache is divided into a preset number of data subsegments, for each processor core, a unique corresponding state identifier is arranged for each data subsegment; after any processor core performs data writing on a target data subsegment of a target cache line in the shared cache, the target data subsegment is written back to a memory, and is loaded from the memory to a private cache of the any processor core, the state identifier of the target data subsegment of the any processor core is determined as a shared state, and the state identifier of the target data subsegment of a first processor core is determined as an invalid state. In this way, unnecessary memory data loading can be reduced, and the overall performance of a multi-core processor is improved.

Techniques are provided for managing a cache using one or more linked list data structures for each scheduling unit. One method comprises receiving, by a cache management system that manages a cache memory, a cache access request comprising a target address for accessing data; managing, by the cache management system, at least one linked list data structure for each scheduling unit of a storage server; initiating, by the cache management system, a cache access operation to determine whether the target address corresponds to a cache entry; and in response to determining that the target address corresponds to a cache entry, (i) accessing, by the cache management system, the cache entry to obtain cache data from the cache memory, (ii) returning the obtained cache data to a requesting cache client and (iii) updating the at least one linked list data structure.

An instruction cache, a circular buffer and a method for controlling access of the instruction cache are provided. The instruction cache includes an instruction cache bank, a circular buffer and a selection circuit, where the selection circuit is coupled to the instruction cache bank and the circular buffer. The instruction cache bank is configured to store instructions for a processor. The circular buffer is configured to store a portion of the instructions, where access speed of the circular buffer is faster than access speed of the instruction cache bank. The selection circuit is configured to select one of a first instruction from the instruction cache bank and a second instruction from the circular buffer to be output as an output instruction for the processor according to whether a read address is found in the circular buffer or not.

Managing data stored in a cache using a reinforcement learning agent may include: determining a set of current state observations with respect to a cache, wherein the set of current state observations is determined based on historical cache accesses to the cache; inputting the set of current state observations into an actor network of a reinforcement learning (RL) agent to obtain an action output by the actor network, wherein the RL agent is configured to manage data stored at the cache; inputting the set of current state observations and the action into a critic network of the RL agent to obtain a score corresponding to the action from the critic network; causing the RL agent to perform the action with respect to managing the data stored at the cache; using the score to update the actor network; and using a reward corresponding to the action to update the critic network.

This disclosure provides a cache including at least two layers. Each layer includes a first cache unit and a second cache unit. First cache access instructions from different layers enter different pipelines to access the first cache unit within the corresponding layer, and second cache access instructions from different layers enter different pipelines to access the second cache unit within the corresponding layer. The cache in this embodiment includes multiple layers, which can expand cache capacity, improve data hit rate, and enhance overall CPU performance. Moreover, cache access instructions from each layer independently access their respective cache units, ensuring cache processing efficiency. This disclosure also provides a data processing apparatus and chip.

This application discloses a memory access method, a multi-core system, a processor, and a system-on-a-chip, relating to the field of processors. The method includes: in response to a received atomic operation, determining the memory address carried in the atomic operation; based on the memory address, determining the address layout state of first data in memory, wherein the address layout state characterizes whether the memory address crosses the cache line boundary or data page boundary of any processing unit; if the address layout state characterizes that the memory address crosses the cache line boundary or data page boundary, splitting the atomic operation into multiple first sub-operations, wherein different first sub-operations carry different sub-addresses; and based on the sub-addresses carried by the multiple first sub-operations, accessing the first data stored in memory through the cache of any processing unit. This application solves the technical problem of low processing efficiency in multi-core systems caused by improper control of unaligned atomic operations.

This application relates to the field of chip design technology, and in particular to a cache access method during the GPU primitive assembly stage. It includes: after receiving a vertex data access request from a primitive assembly unit, the cache performs a matching verification between the high-order address of the request and a tag stored in the cache. If a match is found, the counter of the cache line corresponding to the matching tag is incremented by 1, and the vertex data in the cache line corresponding to the matching tag is returned to the primitive assembly unit. Furthermore, after the primitive assembly unit completes processing the primitive processing request, the counter of the cache line corresponding to the matching tag is decremented by 1. This invention improves the efficiency of reading vertex data, thereby improving the processing efficiency of the GPU primitive assembly stage.

Embodiments of the present application provide a reasoning method, a computing cluster and a computing device. The method is applied to a first computing node in a plurality of computing nodes connected with a shared memory device based on a cache consistency protocol, and includes: in response to a reasoning request, obtaining a first historical key-value cache in a local cache of the first computing node; in a case where the first historical key-value cache needs to be obtained, sending a first read request to a control node; receiving a second historical key-value cache read from the shared memory device and returned by a second computing node in response to the first read request; and performing a reasoning task based on the first historical key-value cache and the second historical key-value cache. In the above manner, by reusing the local cache and obtaining the missing historical key-value cache based on the computing node currently having access rights on demand, efficient reuse of the historical key-value cache can be achieved, thereby significantly reducing cache access latency and improving overall reasoning performance.

The application provides a block device layer differentiated admission control method and system, the method comprises: obtaining input and output request characteristic data of the block device layer, the input and output request characteristic data is obtained by feature extraction on the input and output request; identifying the key value cache access mode according to the input and output request characteristic data; according to the identified key value cache access mode, the corresponding token bucket resource is allocated to the input and output request, and the differentiated admission control is executed. Without modifying the upper reasoning engine, the application realizes the differentiated block device layer admission control of the key value cache flow and the conventional data flow in the large model reasoning, and reduces the delay of the key value cache reading.

The application relates to the technical field of graph neural networks, in particular to a multi-tenant vector cache replacement strategy optimization method based on a graph neural network, which comprises the following steps: collecting cache access track data and related metadata of a multi-tenant vector database in real time; based on the cache access track data and related metadata, a multi-tenant cache access heterogeneous graph is constructed; the multi-tenant cache access heterogeneous graph is input into a graph neural network model to determine the importance of each vector data node in the multi-tenant cache access heterogeneous graph; based on the importance of each vector data node, in combination with a current cache occupation capacity and a preset cache occupation capacity threshold, one or more vector data nodes that need to be evicted are determined; the application realizes more accurate identification of high-value cache data in a multi-tenant environment by constructing a heterogeneous graph that fuses multi-tenant access modes and time sequence characteristics and dynamically evaluating node importance by using a graph attention network.

A computing system comprising: a cache, comprising a virtual tag storage and a physical tag storage, where each cache line is identified for load operations by a virtual tag and for store operations by a physical tag; a cache access controller; a snoop access circuitry; and a miss controller; wherein, in response to receiving a load operation comprising a virtual address, the cache access controller: accesses the cache to perform the load operation comprising looking up a virtual tag computed using the virtual address; and upon failing to identify the virtual tag value in the virtual tag storage, provides the load operation to the miss controller; and wherein the miss controller in response to receiving the load operation from the access controller, initiates an aliasing snoop to the cache by the snoop access circuitry, the aliasing snoop comprising looking up a physical tag computed using a corresponding physical address.

This application provides a block device layer differentiated admission control method and system. The method includes: acquiring input / output request feature data of the block device layer, wherein the input / output request feature data is obtained by feature extraction of input / output requests; identifying key-value cache access patterns based on the input / output request feature data; allocating corresponding token bucket resources to input / output requests according to the identified key-value cache access patterns; and performing differentiated admission control. This application achieves differentiated block device layer admission control between key-value cache traffic and regular data flow in large model inference without modifying the upper-layer inference engine, reducing the latency of key-value cache reads.

A data storage management device and processing core, the device comprising: at least two random access memories (RAM); a control unit receiving instructions, generating and sending control signals (S101) according to the instructions; a direct memory access controller (DMAC) realizing access to data in the random access memories (RAM) according to the control signals (S102). The data storage management device receives and responds to instructions sent from an external processing unit, reads data from an external storage unit, so that the external processing unit can directly read the data required for executing a program from the data storage management device when executing the program, and the external processing unit does not need to take data from the external storage unit through a cache (Cache), eliminating the decline in computing efficiency caused by Cache access invalidation, and improving the controllability of program efficiency.

The application relates to a cache access command processing system, method, device and medium. The system comprises a cache queue management module and a cache pipeline. The cache queue management module is used for obtaining a cache access command to be processed and a corresponding cache access address; cache access commands with the same cache access address are input into the same queue, and in a clock cycle, a current cache access command is scheduled from multiple non-idle queues to enter the cache pipeline; the cache pipeline is used for processing the current cache access command in the cache pipeline and returning response data corresponding to the current cache access command; the cache queue management module is used for obtaining a to-be-scheduled cache access command in the current cache access queue; and according to the command type of the to-be-scheduled cache access command, the next cache access command scheduled to enter the cache pipeline is determined. The method can improve the processing efficiency of access commands.

The application discloses a data access method and device, computer equipment and a storage medium. The method is executed by an interconnection device arranged between a single host and multiple slaves, and comprises the following steps: replacing source identification in an access request sent by the host with mapping identification of a slave to which the access request points, and then sending each access request to each slave; maintaining in real time the sending order of the access request corresponding to each source identification respectively, the sending order of each access request sent to the same slave, and the access request to which the next access response to be fed back by each slave points; and feeding back the access response fed back by each slave to the host according to the sending order of the access request according to the real-time maintenance result. By using the above technical scheme, when the single host sends multiple access requests with the same source identification to the multiple slaves, the multiple access requests with the same source identification can be processed in parallel, so that the cache access performance of the chip is improved.