155 results about "Cache access" patented technology

The invention provides a cache architecture and method of an AXI interconnection module, electronic equipment and a storage medium, and relates to the technical field of storage, the cache architecture comprises an index cache region, a shared cache region and a shared cache access controller, the index cache region comprises an index entry list, and the shared cache region comprises an instruction cache region and a data cache region; each index cache region corresponds to one main device, the shared cache region corresponds to all the main devices, and the index entry list is used for recording index information of access transactions of the corresponding main devices; each index entry in the index entry list corresponds to one access transaction; and the shared cache access controller is used for storing instruction information corresponding to the access transaction in the instruction cache region based on the index information and storing data information corresponding to the access transaction in the data cache region. By applying the scheme of the invention, the utilization efficiency of on-chip resources can be improved on the basis of ensuring the transaction processing performance.

The invention relates to the technical field of data processing, and particularly discloses an intelligent cache replacement method and system based on application awareness, and the method comprises the steps: sensing a cache state of an application scene, and determining a candidate cache replacement strategy according to a cache replacement strategy matching rule; the method comprises the following steps: collecting data of a storage node data access mode, a cache access state, a capacity state and a power consumption state of an application scene, and preprocessing the data to generate historical data; according to historical data, training a GRU model to predict future cache hit information, and determining a cache hit rate of the application scene; calculating strategy benefits according to the cache hit rate and the evaluation index of the cache hit rate, and comparing the candidate cache replacement strategy with the current cache replacement strategy; and when the cache hit rate is lower than a preset threshold value and a strategy benefit comparison result exceeds a set value, configuring the candidate cache replacement strategy as a current cache replacement strategy.

The invention belongs to the field of integrated circuits and computer system structures, and provides a caching method and system for a memory access unit of a superscalar processor, and the method comprises the steps: receiving a plurality of memory access instructions in the same period, and determining a corresponding Bank in a to-be-accessed cache through the memory access instructions; after the memory access instruction obtains a cache access permission, if cache line missing occurs, generating a missing request, merging all the missing requests, and performing parallel prefetching training on the merged missing requests by utilizing a mode of fusing a constant step length prefetching mode and a complex step length prefetching mode to obtain a prefetching request and a prefetching cache address corresponding to the prefetching request; requesting a missing cache line from the first-level cache to the second-level cache based on the missing queue, and writing the missing cache line back to the cache line of the corresponding data cache in the first-level cache; and storing the bus consistency request by using the sniffing queue, judging whether the data in the multi-core cache are consistent or not by using the consistency request, and performing consistency modification according to a judgment result. The cache hit rate and the bandwidth utilization rate are improved.

The invention discloses a database access parameter real-time cooperative processing method and device based on multi-level cache, and belongs to the technical field of computer data caching. The method comprises the steps that a version number management table is configured; establishing a four-level cache architecture of a transaction-level cache layer, a process-level cache layer, a distributed cache layer and a database cache layer; receiving a transaction request, creating a transaction level cache layer and loading current version number information; comparing the version number in the transaction level cache layer with the version number in the process level cache layer; according to the version number comparison result, obtaining parameter data from the corresponding cache level according to a preset cache access priority strategy; and when the parameter change is detected, updating the corresponding version number in the version number management table, and updating the cache layer data as required. According to the method, real-time global effectiveness of parameter change is realized, parameter consistency of in-transit transaction is guaranteed, system processing performance and throughput are improved, system reliability and fault-tolerant capability are enhanced, and system resource utilization rate is optimized.

A computer-implemented method for testing an instruction cache logic circuit of an integrated circuit, comprising: storing in the cache logic circuit a sequence of instructions including M instructions; reading an initial counter value of a cache access counter; executing the sequence of instructions and, for each instruction executed from the cache logic circuit, incrementing the current counter value of the counter; reading a final counter value of the counter; blocking an execution of instructions unintended by the test for a period lasting from reading the initial counter value until reading the final counter value; subtracting the initial counter value from the final counter value, and comparing the result of said subtraction with the value M.

An apparatus has cache data storage, and tagged-data prediction circuitry to generate a tagged-data prediction in response to a streaming-write request requesting that write data corresponding to a target address which missed in a previous level of cache is written to the cache data storage for the given level of cache without being allocated into the previous level of cache. The tagged-data prediction is indicative of whether a target cache data entry corresponding to the target address of the streaming-write request is predicted to be a tagged cache data entry that stores cached data associated with the target address and a valid memory safety check tag corresponding to the target address, or an untagged cache data entry that stores the cached data but does not store a valid memory safety check tag. Cache access scheduling circuitry selects, based on the tagged-data prediction generated by the tagged-data prediction circuitry for the streaming-write request, how to schedule access to the cache data storage in response to the streaming-write request.

The invention relates to the technical field of integrated circuits, and discloses a data transmission method and device for interconnection between core particles, the core particles and a processing system.The method is applied to a first core particle and comprises the steps that a protocol layer of the first core particle receives to-be-transmitted data sent by a processor of the first core particle; a protocol layer carries out protocol layer overall packing on data to be transmitted to obtain a protocol layer packet, the protocol layer packet comprises a packet header field and a load area, the packet header field is used for identifying a channel type and a channel signal field of the load area, the channel type comprises at least one monitoring channel used for monitoring cache consistency between core particles, and the monitoring channel is used for monitoring cache consistency between the core particles. The packet header field is used for identifying a channel type and a channel signal field of the load area; and the protocol layer sends the to-be-transmitted data to the second core grain through the link layer and the physical layer of the first core grain based on the protocol layer packet. The problem of cache access consistency of processors among core particles is effectively solved.

Methods and systems for cache miss monitoring and fulfillment are disclosed. A disclosed method comprises receiving, from a processing unit, a cache access request, determining, based on a cache failing to fulfill the cache access request, that a cache miss has occurred, populating a request buffer based on the cache miss and the cache access request, populating a transaction buffer with a transaction entry for the request buffer based on the cache miss request and the cache access request, determining by the request buffer, that information requested in the cache access request should be retrieved from main memory, determining, by the transaction buffer if information was not retrieved, that the cache access request satisfies criteria for creating a cache miss tag, creating the cache miss tag based on the cache access request, and storing the cache miss tag in a portion of the cache.

The invention provides a cache replacement method and device, equipment and a storage medium, a cache is formed by connecting n paths of groups, and n is 4 or 8; if n is 4, dividing every two paths into one group to obtain a first group and a second group; 4-bit access information is recorded; if n is 8, every two paths are divided into one group, and a third group, a fourth group, a fifth group and a sixth group are obtained; every two groups are divided into a large group, and a first large group and a second large group are obtained; 10 bit access information is recorded; the method comprises the following steps: acquiring cached access information; determining a cache line which is not accessed for the longest time according to the access information; and replacing the cache line which is not accessed for the longest time. According to the method provided by the invention, the cache line can be quickly replaced through the access information.

The invention relates to the field of computer storage, and provides a cache space capacity adjusting method and computer device.The method comprises the steps that cache access information of a processor executing cache access operation is obtained; performing feature extraction on the cache access information to obtain data feature information corresponding to the cache access information; predicting the space size of a data cache space required by a processor according to the data feature information to obtain the predicted capacity of the cache space; determining an adjustment strategy for adjusting the space size of the data cache space based on the cache space prediction capacity; and adjusting the space size of the data cache space according to the adjustment strategy. Due to the fact that the size of the cache space needed by the equipment is predicted, and the space size of the cache space is adjusted according to the prediction result, the size of the cache space can adapt to the requirements of the equipment, the flexibility of the size of the cache space is improved, and the utilization rate of hardware is improved.

The invention provides a data cache access method and device of a multi-core processor, and relates to the technical field of computer processors. The method comprises the following steps: accessing a data cache according to an access instruction, and responding to the access instruction to hit access data and write back the access data, or responding to the access instruction to not hit the access data, fetching back-filling data from a memory access failure queue and forwarding the back-filling data to the access queue. Accessing the data cache according to the data storage instruction, writing the stored data into the data cache in response to the access hit of the data cache, or calling a stored data retransmission unit in response to the access miss of the data cache; and sending a data storage failure request to the memory access failure queue, and taking back the backfill data and / or authority by the memory access failure queue. According to the method, the flexibility of the processing mode of the data cache access pipeline on the memory access instruction and the external consistency request can be improved, the access parallelism degree is improved, and the hardware resource utilization rate of the processor is increased.

The invention discloses a buffer, an instruction processing method, a processor and computer equipment, and relates to the technical field of chips. The buffer is an L2-level buffer in a processor and comprises a request distribution circuit and a buffer circuit, the request distribution circuit is connected with the cache circuit; the cache circuit comprises a cache unit and an operation unit; the operation unit is connected with the cache unit; the request distribution circuit is used for receiving the cache access request and sending the cache access request to the cache circuit; the cache unit is used for reading source data corresponding to the cache access request under the condition that the cache access request is a write request corresponding to the atomic operation, and inputting the read source data into the operation unit; and the arithmetic unit is used for executing atomic operation corresponding to the cache access request on the source data to obtain operation result data and writing the operation result data into the cache unit.

The invention discloses an optimization method and system for direct I / O read performance under a Linux system. The method comprises the steps that a cache control mark used for controlling cache access is introduced; in the file opening stage, whether a cache mechanism is started or not is judged, if yes, whether a cache is hit or not is detected when direct I / O reading operation is executed, data are directly read from the cache and returned when the cache is hit, standard direct I / O reading and data returning are called when the cache is not hit, meanwhile, asynchronous caching is conducted on the data, and a cache mark is set; when the direct I / O write operation is executed, whether a cache mechanism is started or not is judged, if yes, whether the cache is hit or not is detected firstly, when the cache is hit, original cache data is set to be invalid, asynchronous caching is conducted on the data, meanwhile, standard direct I / O write-in data is called, and after asynchronous caching and data write-in operation are completed, the cache data is set to be valid. According to the invention, the reading performance of direct I / O can be improved.

The embodiment of the invention provides a multi-level cache access method, system and device and a storage medium, and relates to the technical field of data cache access, and the method comprises the following steps: obtaining a key field in a user auditing request, and converting the key field into a feature vector; searching whether a reasoning result corresponding to the feature vector exists in a first preset cache or not; if yes, a reasoning result is returned to the user; if not, a corresponding semantic partition is found in a second preset cache, and a historical cache vector with the highest similarity and a corresponding reasoning result are determined from the semantic partition; and determining a reasoning result corresponding to the feature vector according to the feature vector, a historical cache vector and a reasoning result corresponding to the historical cache vector. In this way, a two-stage cache mechanism based on the feature vector is constructed, a corresponding reasoning result is found in combination with semantic partition, the cache hit rate is increased, repeated reasoning of a large model is reduced, response delay is reduced, and therefore the requirements for high redundancy and high real-time performance of cache data reasoning are met.

The invention discloses a system memory peak bandwidth measurement method and electronic equipment, and relates to the technical field of bandwidth measurement, the memory bandwidth measurement process is optimized through cooperation of dynamic selection of a maximum width vector instruction, forced non-cache access and NUMA perception binding, and the bandwidth measurement efficiency is improved by utilizing the vector processing capacity of a CPU (Central Processing Unit). The data throughput of a single operation is improved to 512 bits or even higher, through cooperation of a non-temporary instruction and a memory barrier instruction, a cache level is bypassed, interference of cache hit or jitter on a measurement result is eliminated, it is ensured that the measurement result truly reflects the performance of a memory system, and the measurement accuracy is improved. Through an automatic NUMA binding mechanism, delay and congestion caused by cross-node access are avoided, and the accuracy, stability and repeatability of a test result are improved.

The invention discloses a virtual machine monitor system for a resource-limited persistent memory server, which comprises a configuration file module, a CPU (Central Processing Unit) management module, a memory management module, a cache management module, an interrupt management module, a cross-partition communication module and a virtual machine management module. The CPU management module is used for binding a virtual CPU to a physical CPU core, so that computing resources of the virtual machines are dedicated, and meanwhile, the virtual machines are prevented from competing for the CPU; the memory management module is used for dividing a physical memory region according to a configuration file and realizing address space isolation between virtual machines by utilizing two-stage address translation; the cache management module is used for performing isolation control on cache access of a plurality of virtual machines through a coloring mechanism of the last-level cache; and the interrupt management module is used for simulating the universal interrupt controller, and the virtual machine monitor re-injects the interrupt into the target virtual machine according to the configuration file after capturing the hardware interrupt.

The invention discloses an edge computing driven wild animal image compression and encryption transmission method, which relates to the technical field of image processing, and comprises the following steps of: constructing a cache access density curve based on task triggering frequency and cache calling times of edge computing equipment in unit time, recording a time sequence of the maximum available space and the current available space of the cache region, and extracting a cache fluctuation period and an instantaneous compression amplitude; and calculating a difference value between the cache allocation duration and the release delay, and constructing a cache response lag index. According to the method, the multi-dimensional cache state indexes are constructed, and the cache resource pressure bearing coefficients are generated, so that the quantitative perception and prediction of the cache risk are realized. When the cache resource pressure bearing coefficient exceeds the overvoltage risk threshold value, the system automatically executes image frame self-adaptive deletion, the load is relieved, the event continuity is kept, and the stability and the resource utilization efficiency of edge equipment in a high-density image processing scene are effectively improved.

The embodiment of the invention provides a multi-core processor system and a cache line locking control method, and the multi-core processor system comprises a plurality of cores and a cache line locking control unit, each core comprises at least one level of cache; each level of cache is used for identifying a cache access request in the received monitoring information; when it is identified that the cache access request is a request for accessing the cache line locked by the cache at the same level and the locked cache behavior core has the cache line under the use condition, a delay signal is sent out, and processing of the monitoring information is paused; when the execution signal is obtained, processing of the monitoring information is recovered, and the locked cache line is released; the cache line locking control unit is used for receiving the delay signal and sending out an execution signal at a preset delay moment; the locked cache line is realized on the basis of a lock obtained by a core execution lock grabbing mechanism. According to the technical scheme provided by the embodiment of the invention, the efficiency of executing a lock grabbing mechanism can be improved, and the overall performance of a multi-core processor system is improved.

The invention provides a cache access method and device, equipment and a storage medium, the method is applied to a QPC cache, and the method comprises the following steps: receiving a read request and a first update signal sent by an RDMA network card; the first update signal is used for indicating an operation type of an update operation performed on the target data by the QPC cache; the target data is the data requested by the read request; under the condition that the QPC cache is hit, sending target data to the RDMA network card in response to the read request, and determining a target field for updating in the target data based on preset arbitration logic; and updating the target data according to the operation type and the target field. According to the invention, the working efficiency of cache access can be improved.

This invention discloses an intelligent resource allocation method for energy-aware partitions, belonging to the field of computer architecture and operating system task scheduling technology. The method divides computing resources into multiple independent energy-aware partitions based on the processor cores. It then monitors the energy status parameters of each partition in real time. By parsing the instruction code stream of the tasks to be assigned, the proportion of arithmetic and logical instructions is extracted as instruction mixing features, and the address span of memory access instructions is analyzed to obtain cache access density features. Based on the energy status of the partitions and the computation and memory access characteristics of the tasks, a suitability score for the task relative to each partition is generated, comprehensively reflecting the energy matching degree and hardware resource matching degree. Based on the suitability score and the remaining task acceptance capacity of the partitions, a two-dimensional assignment strategy is used to dynamically map tasks to the core execution in the optimal energy-aware partition. This invention achieves fine-grained matching of computing resources and energy status, optimizing system energy utilization efficiency.

This invention relates to a dynamic voltage and frequency adjustment method for a RISC-V processor core. The method includes: monitoring and recording the critical path time of memory access requests for each missing state processing register to update the global critical path counter; monitoring prefetch instructions and extracting their delay parameters; collecting cache access events based on a time window to calculate bandwidth utilization and dynamically determining a bandwidth threshold according to preset performance parameters; and correcting the global critical path counter value by combining the prefetch delay and the bandwidth threshold, thereby triggering a dynamic voltage and frequency adjustment instruction. This method achieves fine-grained adaptive DVFS for the RISC-V processor core under complex loads, significantly improving energy efficiency and performance stability.

The application relates to a dynamic cache sharding method and device, a storage medium and an electronic device. The method comprises the following steps: when it is detected that a cache system adds or removes a cache shard for capacity expansion or contraction, a cache SDK running in an application program continues to perform a cache access operation on cache data according to an original cache shard rule; a cache management component independently set performs a rehashing calculation based on a target cache shard rule after the capacity expansion or contraction, so as to perform asynchronous migration of the cache data to the target cache shard after the capacity expansion or contraction; and after the asynchronous migration is completed, the cache management component sends a shard rule switching instruction to the cache SDK, so that the cache SDK switches to the target cache shard rule to perform the cache access operation. The application solves the technical problems that cache shards are static and are prone to cause cache break-in and service fluctuation during capacity expansion or contraction.

A cache storage device is disclosed, including a cache circuit and a path prediction circuit. The cache circuit generates a cache hit signal indicating whether target data corresponding to an accessed address is stored in a cache line, and in path prediction mode, performs the current cache access operation primarily on candidate paths based on candidate path signals indicating candidate paths. The path prediction circuit stores accumulated information based on cache hit signals provided during previous cache access operations, by accumulating cache hit results indicating whether target data is stored in a path and path prediction hit results indicating whether target data is stored in a candidate path. In path prediction mode, the path prediction circuit generates candidate path signals based on the accumulated information by determining candidate paths for the current cache access operation.

A data processor includes a data fabric, a memory controller, a last level cache, and a traffic monitor. The data fabric is for routing requests between a plurality of requestors and a plurality of responders. The memory controller is for accessing a volatile memory. The last level cache is coupled between the memory controller and the data fabric. The traffic monitor is coupled to the last level cache and operable to monitor traffic between the last level cache and the memory controller, and based on detecting an idle condition in the monitored traffic, to cause the memory controller to command the volatile memory to enter self-refresh mode while the last level cache maintains an operational power state and responds to cache hits over the data fabric.

The embodiment of the present specification provides a cold and hot page statistics method and device, which is applied to a cold and hot page identification module of a memory controller, wherein the cold and hot page statistics method comprises: in response to a memory access instruction sent by a processor, generating an access record for an initial memory page according to the memory access instruction, updating the access times of the initial memory page in a data list according to the access record, and determining a cold memory page or a hot memory page according to the access times of the initial memory page in the data list. By obtaining the memory access instruction sent by the processor, the real memory access can be detected, the cache access is avoided from being regarded as the memory access to perform false statistics, and since each memory access can be recorded by the access record, the probabilistic error in the sampling statistics is avoided, and the accuracy of the cold and hot page identification is improved.

Examples described herein relate to a cache fabric that includes a set of routers of a first tier and a plurality of cache controller clusters of a second tier. A router of the set of routers is accessible via an interface to receive a memory access request from a processor and select from a set of cache controllers based on a cluster identifier and a memory address, and provide the memory access request to the selected set of cache controllers. The selected set of cache controllers may receive memory access requests and serve memory access requests from the cache device, or forward memory access requests to a second cache controller or second cache device associated with the cache device.

The present invention discloses a dynamic adaptive sampling simulation preheating optimization method and a high-performance CPU simulator. The method prepares an instruction stream and extracts the dynamic features of each program fragment in real time. The dynamic features include an instruction mixing ratio vector, branch history entropy, and a cache access time-space matrix. The method obtains a preheating distance error curve for each program fragment and calculates the curvature parameter of the preheating distance error curve. A preheating sensitivity prediction model is constructed using a deep learning model. The model input is the dynamic features of step 1, and the output is the curvature parameter of the preheating distance error curve. The preheating sensitivity prediction model is trained to obtain the curvature parameter of the preheating distance error curve of the sampled program fragment. A preheating distance allocation strategy is formulated based on a reinforcement learning framework to allocate preheating distances for the sampled program fragments. The method has good dynamic adaptability, high simulation accuracy, high efficiency, and is widely applicable to various high-performance processors.

Provided in the embodiments of the present disclosure are a cache management method, a cache management apparatus, a processor, and an electronic apparatus. The cache management method comprises: acquiring a cache access preference of a first thread for a first cache of a multi-thread processor, which first thread is among a plurality of threads running in the multi-thread processor; and in response to the cache access preference of the first thread for the first cache meeting a cache replacement condition, preferentially replacing from the first cache a data block, which is loaded into the first cache by the first thread. In the method, by means of acquiring cache access preferences of different threads for at least one cache, during cache replacement, a data block from a thread with a low cache access preference is preferentially replaced, thereby resolving the contention and collision of threads for a cache, improving the utilization efficiency of the cache, and realizing low overheads and low power consumption of hardware storage.

A system for context-sensitive distributed processing and memory optimization in a multi-core computer architecture, wherein the system comprises: a plurality of processor cores arranged within a processor structure and configured to perform computational tasks in parallel; a linking network that operationally connects the plurality of processor cores for data communication; a context capture unit connected to each of the plurality of processing cores and configured to monitor execution parameters such as instruction throughput, cache access behavior, memory latency, and data exchange characteristics between the cores, wherein the context capture unit generates context descriptors that are representative of the runtime execution conditions;a scheduling processor operationally connected to the context capture unit and configured to distribute computational tasks across the multitude of processor cores based on the generated context descriptors; and a memory management unit operationally connected to a hierarchical memory arrangement comprising multiple cache levels and main memory, the memory management unit being configured to dynamically allocate and migrate data segments across the hierarchical memory arrangement according to the context descriptors, thus achieving alignment between task execution and data locality.

The application provides a cache access method, a DRAM cache, a cache management system and a computing device. The cache access method comprises receiving a memory access request, the request specifying a data size to be accessed; determining a corresponding granularity cache area in the DRAM cache according to the data size; and the granularity cache area is obtained by dividing the DRAM cache area according to different granularity sizes. Thus, the corresponding granularity cache area is selected according to the data size of the request, the appropriate cache block can be positioned more accurately, the opportunity of DRAM cache hit is increased, and the memory access delay is reduced. The proportion of useful data in the DRAM cache is improved, and the cache space utilization is improved.