Speculative hybrid branch direction predictor

Abstract

An apparatus for speculatively predicting the direction of a branch instruction in a pipelined microprocessor in a hybrid fashion. A branch target address cache (BTAC) stores a direction prediction about executed branch instructions. The BTAC is indexed by an instruction cache fetch address. The BTAC is accessed in parallel with the instruction cache access, such that the direction prediction is provided before the actual instruction is decoded which is presumed to be a branch instruction corresponding to the direction prediction stored in the BTAC. In parallel with the BTAC access, a branch history table (BHT) is accessed to provide a second speculative direction prediction. The BHT is indexed with a gshare function of the instruction cache fetch address and a global branch history stored in a global branch history register. The BTAC also provides a selector that selects between the two speculative direction predictions.

Description

CROSS REFERENCE TO RELATED APPLICATIONS [0001] This application is related to the following U.S. patent applications, having a common filing date and a common assignee. Each of these applications is hereby incorporated by reference in its entirety for all purposes: Docket #Serial #TitleCNTR: 2021SPECULATIVE BRANCH TARGET ADDRESSCACHECNTR: 2022APPARATUS, SYSTEM AND METHOD FORDETECTING AND CORRECTINGERRONEOUS SPECULATIVE BRANCHTARGET ADDRESS CACHEBRANCHESCNTR: 2050DUAL CALL / RETURN STACK BRANCHPREDICTION SYSTEMCNTR: 2052SPECULATIVE BRANCH TARGET ADDRESSCACHE WITH SELECTIVE OVERRIDE BYSECONDARY PREDICTOR BASEDON BRANCH INSTRUCTION TYPECNTR: 2062APPARATUS AND METHOD FORSELECTING ONE OF MULTIPLETARGET ADDRESSES STORED IN ASPECULATIVE BRANCH TARGETADDRESS CACHE PER INSTRUCTIONCACHE LINECNTR: 2063APPARATUS AND METHOD FOR TARGETADDRESS REPLACEMENT INSPECULATIVE BRANCH TARGETADDRESS CACHEFIELD OF THE INVENTION [0002] This invention relates in general to the field of branch prediction in micr...

AI Technical Summary

Benefits of technology

This approach reduces branch penalty by enabling early and accurate branching, improving direction prediction accuracy and reducing chip real estate usage, while avoiding the inefficiencies of integrated BTACs and maintaining fast data access times.

Problems solved by technology

The change in the value of the program counter because of the execution of a branch instruction causes a break in the sequence of instruction execution.

Modern microprocessors are not so simple.

Throwing out the intermediate instructions and fetching the instruction at the target address creates processing delays in such microprocessors, referred to as a branch penalty.

Although the prior methods provide branch prediction improvements, there are disadvantages to the prior methods.

A disadvantage of both the prior methods discussed above is that the instruction pre-decode information, and in the case of Athlon the branch target addresses, substantially increase the size of the instruction cache.

A disadvantage of the Athlon integrated BTAC is that the integration of the BTAC into the instruction cache causes space usage inefficiency.

Much of the space taken up inside the Athlon instruction cache by the additional branch prediction information is wasted since the instruction cache has a relatively low concentration of branch instructions.

For example, a given instruction cache line may have no branches in it, and thus all the space taken up by storing the target addresses and other branch prediction information in the line are unused and wasted.

Another disadvantage of the Athlon integrated BTAC is that of conflicting design goals.

Requiring the BTAC to be the same size as the instruction cache, in terms of cache lines, which is inherent in the Athlon scheme, may not optimally meet both sets of design goals.

In the case of the relatively large Athlon instruction cache, the access time may be relatively long.

However, because the Pentium II / III BTB is indexed with the instruction pointer of an already decoded instruction, rather than the instruction cache fetch address, the Pentium II / III solution potentially may not be able to branch as early as the Athlon solution, and therefore, may not reduce the branch penalty as effectively.

However, a disadvantage of the Pentium II / III method is that some amount of branch prediction accuracy is sacrificed by using the instruction pointer of a previous instruction, rather than the actual branch instruction pointer.

Additionally, because using a prior instruction pointer introduces the possibility of multiple paths to the same branch instruction, it potentially takes the Pentium II / III direction predictor in the BTB longer to “warm up”.

When a new branch instruction is brought into the processor and cached, the multiple paths to the branch instruction potentially cause the branch history to become updated more slowly than would be the case if only a single path to the branch instruction were possible, resulting in less accurate predictions.

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