7347 results about "Semiconductor" patented technology

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

The invention discloses a forming method of a flash memory unit. The forming method comprises the following steps: providing a semiconductor substrate; forming a tunneling oxide layer on the semiconductor substrate; forming nanocrystalline silicon particles on the tunneling oxide layer; forming an isolation insulating layer on the tunneling oxide layer and the nanocrystalline silicon particles; and forming a control grid on the isolation insulating layer, wherein the step of forming the nanocrystalline silicon particles on the tunneling oxide layer comprises: forming an amorphous silicon layer on the tunneling oxide layer; and performing repeated seed crystal particle forming processes on the amorphous silicon layer, wherein surface annealing treatment is performed between two adjacent seed crystal particle forming processes, and an annealing process is performed after the last seed crystal particle forming process. The flash memory unit can be used for storing a large quantity of electrons, and has high performance.

Provided is a semiconductor apparatus comprising a semiconductor substrate, and an additional layer provided on a front surface of the semiconductor substrate, including: a drift region of a first conductivity type provided in the semiconductor substrate; a base region of a second conductivity type provided above the drift region in the semiconductor substrate; a gate trench portion provided on an upper surface of the additional layer; an emitter region of the first conductivity type that is provided above the base region and is in contact with the gate trench portion; and a conductive trench contact portion provided from the upper surface of the additional layer to a position deeper than an upper end of the base region, wherein the emitter region includes: a contact emitter portion provided on the upper surface of the additional layer; a resistance emitter portion provided in the additional layer; and an additional emitter portion.

A method of manufacturing a semiconductor device having a combination structure of a horizontal oxide layer structure and a vertical oxide layer structure, can include: etching from an upper surface of the semiconductor substrate to inside of the semiconductor substrate to form a trench; depositing oxides in the trench to form the vertical oxide layer structure; etching the vertical oxide layer structure from an upper surface thereof to decrease height of the vertical oxide layer structure, and to make a top surface of the vertical oxide layer structure be below the upper surface of the semiconductor substrate, in order to expose side surfaces of the trench; and forming, by an oxidation process, the horizontal oxide layer structure to cover part of the upper surface of the semiconductor substrate and the upper surface of the vertical oxide layer structure.

A semiconductor device is provided in which an emitter region includes a first emitter portion which is in contact with a front surface of a semiconductor substrate, a second emitter portion which is provided below the first emitter portion and has a doping concentration lower than that of the first emitter portion, and a third emitter portion which is provided below the second emitter portion and has a doping concentration higher than that of the second emitter portion, and a gate trench portion includes a dummy conductive portion at an emitter potential, which is provided above the gate conductive portion, in a trench.

A device structure includes a pair of vertical layer stacks containing alternating insulating and electrically conductive layers that laterally extend along a first horizontal direction and are laterally spaced apart from each other along a second horizontal direction by a lateral isolation trench that is filled with a lateral isolation trench fill structure, memory openings vertically extending through a respective vertical layer stack within the pair of vertical layer stacks, memory opening fill structures located in the memory openings, where each of the memory opening fill structures includes a respective vertical stack of memory elements and a vertical semiconductor channel, and support pillar structures vertically extending through the pair of vertical layer stacks. Dielectric bridges connect a first subset of the support pillar structures with the lateral isolation trench fill structure.

A sensor includes an anode; a cathode; an organic photoelectric conversion layer between the anode and the cathode; and a first organic auxiliary layer between the anode and the organic photoelectric conversion layer, the organic photoelectric conversion layer includes a p-type semiconductor and an n-type semiconductor, and the first organic auxiliary layer includes a first singlet fission material represented by Chemical Formula 1 and satisfying Relation Formula 1:E⁡(S1)+0.5 eV≥2×E⁡(T1)[Relation⁢ Formula⁢ 1]wherein, Chemical Formula 1 and Relation Formula 1 are the same as described in the specification.

A semiconductor device includes a substrate, a lower power wire provided in a lower portion of the substrate, a rear surface active contact on the lower power wire, a rear surface separation pattern separating the rear surface active contact on the lower power wire, a channel pattern on the rear surface separation pattern, the channel pattern including a plurality of semiconductor patterns stacked spaced apart from each other, a source / drain pattern connected to the channel pattern, a gate electrode between the rear surface separation pattern and one of the plurality of semiconductor patterns, and a pillar protection pattern interposed between the gate electrode and the rear surface separation pattern. The pillar protection pattern and the rear surface separation pattern respectively include different insulating materials.

This invention relates to the field of oil and gas field development, and discloses a full-scale DAS (Digital Angiography and Semiconductor) device and method for monitoring the integrity of hydrate development wellbore. The device includes a formation simulation device, a wellbore simulation device, and a monitoring device. The formation simulation device comprises a temperature control system, a pressure control system, and a simulated formation. The temperature control system, pressure control system, and simulated formation are connected to the wellbore simulation device. The temperature control system and pressure control system are used to simulate the actual temperature and pressure of the hydrate formation. The simulated formation is prepared according to the actual mineral composition and grain size distribution of the hydrate reservoir. The monitoring device is located outside the wellbore simulation device and works in conjunction with the formation simulation device to perform real-time, full-well-section monitoring during hydrate development. This invention can simulate real wellbore conditions and perform real-time, continuous monitoring of the entire wellbore to meet the needs of dynamic downhole monitoring in actual production.

This application provides a lithography system and semiconductor manufacturing equipment. The lithography system includes: a lithography machine for exposing a photoresist-coated wafer; a spin coater / developer for coating photoresist on the wafer surface and performing development; the spin coater / developer includes a multi-functional module, including a wafer imaging system located in the wafer imaging area of ​​the spin coater / developer, for photographing the wafer before and after lithography; the wafer imaging system includes: an imaging stage for holding the wafer; before lithography, a robotic arm transfers the pre-lithography wafer from the spin coater / developer to the imaging stage; after lithography, the robotic arm transfers the post-lithography wafer from the spin coater / developer to the imaging stage; a camera for photographing the wafer before and after lithography, obtaining pre-lithography and post-lithography images for identifying whether there are lithography abnormalities on the wafer. The lithography system can assist in the detection of lithography abnormalities and improve detection efficiency.

The utility model provides a kind of durability test testing machine of automobile sealing strip, it belongs to automobile sealing strip durability test technical field, it includes fixed frame and fixed plate, the top of the fixed frame is fixedly connected with fixed plate, the top of the fixed plate is fixedly connected with shelter frame.The utility model adds temperature table, semiconductor refrigeration piece cold end and electric heating tube by fixed plate, temperature table detects the temperature of the environment where the sealing strip to be tested is located, when it is needed to test sealing strip in low-temperature environment, semiconductor refrigeration piece cold end absorbs heat, when it is needed to test sealing strip in high-temperature environment, resistance wire inside electric heating tube continuously delivers heat to the inside of sealing strip via electrothermal effect, and then the test effect of testing machine is improved.

This invention discloses a personalized and adaptable spot positioning and filter integration design method. Addressing the technical problems of uneven film thickness and poor film formation consistency in existing large-area coating processes, it constructs a dynamic-static synergistic coating control system by combining the dynamic motion mode of the coating target with the static positioning optimization of the substrate and the precise control of static parameters of the coating environment. Simultaneously, it introduces zoned coating compensation, real-time film thickness monitoring feedback, and dynamic trajectory adaptation strategies to achieve uniform deposition of coating materials on large-area substrate surfaces, effectively improving the film thickness consistency, film formation uniformity, and film performance stability of large-area coatings. This invention is convenient to operate, provides precise control, and is compatible with various coating processes such as magnetron sputtering, vacuum evaporation, and ion plating. It can be widely applied to large-area coating production in fields such as flat panel displays, photovoltaic glass, semiconductor wafers, and large-area optical devices.

The present technology relates to a chuck structure and a semiconductor test method using same. The chuck structure according to the present technology may comprise: a film on which a plurality of dies are disposed; and a chuck having the film disposed on one surface thereof and a plurality of grooves for adsorbing the film, the grooves being formed in the one surface.

The application discloses a continuous resonator network computing method based on a resistive memory array, and belongs to the fields of semiconductors, analog computing and integrated circuits. The application sequentially decomposes resonator network computing into three parts of logic computing, matrix-matrix-vector multiplication operation and sign taking computing, and sequentially connects a feedback loop formed by a logic element, a resistive memory array and an operational amplifier to realize hardware, takes a voltage corresponding to a to-be-decomposed hyper vector as input, and obtains a voltage of a corresponding decomposition signal at an output end after the circuit is stable, so that self-convergent resonator network computing in a continuous time domain is realized. Compared with existing resonator network computing implementation schemes, the application can fully exert the performance advantages of analog computing, does not need discrete iteration and data transfer, thereby reducing hardware overhead and operation complexity, and greatly improving speed, energy efficiency and area efficiency.

This invention discloses an intelligent filtering and completion method and system based on a large language model and hierarchical mapping, relating to the fields of artificial intelligence and semiconductor manufacturing execution and data retrieval. The method includes initialization configuration, slot extraction and preprocessing, hierarchical mapping loading and candidate replacement, core filtering key verification and device retrieval, filter combination determination and automatic completion, missing data detection and interactive action determination, response construction and return, and exception handling steps. The system includes a front-end dialogue and interface, a large language model service module, a site-factory-region caching module, a device retrieval and verification module, a strategy engine, and a response generation module. This invention tightly integrates the natural language understanding capabilities of a large language model with back-end structured resource verification, supporting multi-turn dialogue and fine-grained automatic completion, significantly reducing invalid queries, improving retrieval hit rate and user experience, adapting to complex multi-site semiconductor manufacturing scenarios, and featuring a modular design with strong scalability.

In low-energy electron diffraction (LEED), electron diffraction patterns are detected, and images can be formed based on electrons reflected and diffracted from a sample surface. Diffraction patterns can be generated by the interaction of relatively localized coherent electron beams incident on the sample surface (e.g., a selected region of the sample surface). Information from the diffraction patterns can be used to determine (or reconstruct) the structure on the sample surface. Advantageously, selected-area LEED (SA-LEED) or a combination of LEED and stacked imaging (to generate a series of diffraction patterns, each associated with a given particle beam position, wherein particle beams centered at adjacent positions partially overlap) can be used to determine the surface structure of semiconductor wafers via lensless imaging for defect inspection and / or other purposes.

The present application relates to the technical field of semiconductor electrostatic chuck, in particular to an electrostatic chuck ceramic plate with microelectrode and a processing method. In the processing, the electrode forming surface of the ceramic layer is first determined, photoresist is coated and dried, and the photoresist reserved area and the exposed area are formed through exposure and development. The exposed area is subjected to metal plating, and then the photoresist in the reserved area is removed. After cleaning, the exposed area is plated with a metal layer to form a microelectrode. The electrostatic, temperature sensing and heating layer plates are independently manufactured into microelectrodes through the process, and then are bonded to form a ceramic plate. The present application replaces the traditional process with the precision process of photoetching and development combined with plating, improves the forming precision and layout density of the microelectrode, realizes independent manufacturing and high-density integration of the microelectrodes of the three types of layer plates, solves the problem of integration of functional electrodes in the prior art, can realize accurate control of multiple temperature zones, has a mature and coherent process, guarantees the forming quality of the microelectrode, improves the chucking and temperature control performance, meets the needs of semiconductor process, and has practicality and mass production value.

This product is an orthogonal robot that enables automated processing of coating processes such as bonding, coating, sealing, and potting in the manufacturing processes of semiconductor products such as printed circuit boards, electronic equipment, precision instruments, and optical instruments. As shown in the reference diagram illustrating the state in which the dispensing unit is set, when used in a coating process, the liquid dispensing conditions are precisely controlled by a liquid precision dispensing control unit. The movement of the head unit, which is mounted on the base so as to be movable in the X direction, the dispensing unit, which is set in a dispensing unit mounting holder mounted on the head unit so as to be movable in the Z direction, and the work base, which is mounted on the upper surface of the base so as to be movable in the Y direction are controlled to perform relative positioning between the workpiece and the dispensing unit, and then the liquid can be accurately dispensed to the desired position on the workpiece.

This invention relates to the field of vapor phase etching (VPE) apparatus technology, specifically a double-sided VPE apparatus for semiconductor silicon wafers. The apparatus includes a VPE apparatus body, a silicon wafer transfer mechanism at the upper end of the apparatus body, an etching chamber fixedly mounted on the outer side of the apparatus body, and a mounting base fixedly mounted on the upper end of the etching chamber. By combining the VPE mechanism with a central air-guiding mechanism, stable adsorption of the semiconductor silicon wafer is ensured during the etching process, avoiding vibration and improving etching efficiency and precision. A Bernoulli-style chuck structure is formed by the cooperation of the air-guiding support stage and the central stage, stably "fixing" the silicon wafer above the air-guiding support stage, minimizing contact with the semiconductor silicon wafer, avoiding physical damage and contamination, and simultaneously enabling multi-directional airflow distribution to meet auxiliary heat dissipation needs for the semiconductor silicon wafer, further improving the accuracy and etching efficiency of the VPE process.

A semiconductor light-emitting device includes a light-transmissible substrate, and a semiconductor light-emitting stack. The light-transmissible substrate is made of a first material, and has a first surface and a second surface opposite to the first surface. The first surface has a first region, and a second region which is formed with a plurality of protruding portions and a plurality of recessed portions formed therebetween. The recessed portions are disposed at a level lower than that of the first region relative to the second surface. The semiconductor light-emitting stack is disposed on the first region of the first surface along a stacking direction.

The application provides an integrated circuit, comprising: a first metal oxide semiconductor field effect transistor (FET), wherein a first effective gate and a second effective gate are arranged in the first FET, and a first redundant gate is arranged between the first effective gate and the second effective gate; the first effective gate, the second effective gate and the first redundant gate surround a first channel; the first effective gate and the second effective gate are connected to a gate end of the first FET; the first channel on both sides of the first effective gate and the first channel on both sides of the second effective gate are respectively connected to a source end and a drain end of the first FET; and the first redundant gate is connected to a redundant potential or is suspended. Through the structure of the redundant gate arranged between the two effective gates, the current density of the GAA tube can be reduced, and the heat dissipation performance of the GAA tube is further improved.

To provide a manufacturing method for semiconductor devices with enhanced reliability. [Solution] The method for manufacturing a semiconductor device comprises: a pad formation step of forming a connecting electrode pad 14, an inspection electrode pad 18, and an electrode pad connection portion 16 on a first substrate 11; an inspection step of performing an electrical inspection by bringing an inspection probe P into contact with the inspection electrode pad 18 after the pad formation step; a removal step of removing at least the area on the inspection electrode pad 18 that was in contact with the inspection probe P during the inspection step after the inspection step; a connection step of electrically connecting the connecting electrode pad 14 to a second element via a bump 17 after the removal step; and a coating step of covering at least the bump 17 with an insulating coating portion after the removal step.

This invention provides a shipment control method and apparatus, belonging to the field of semiconductor manufacturing technology. The shipment control method includes: acquiring first processing information sent by a processing device, the first processing information being processing information of a wafer cassette loaded by the processing device; acquiring second processing information sent by a MES client for a second wafer cassette, the second processing information including: an identifier of the second wafer cassette, a processing recipe identifier, the location information of the wafer stored in the second wafer cassette, and an identifier of the processing device; comparing the first processing information and the second processing information; if the first processing information and the second processing information are consistent, sending a first instruction to the processing device, instructing the processing device to move the wafer cassette to the wafer cassette storage area; if the first processing information and the second processing information are inconsistent, sending a second instruction to the processing device, instructing the processing device to return the wafer cassette to the wafer cassette loading port. The technical solution of this invention can improve equipment utilization.

This invention relates to the field of semiconductor lithography error correction technology, specifically a lithography machine error correction method and system. The method includes: deploying an interferometric sampling array to capture the initial wavefront phase distribution to obtain a reference wavefront field; using a thermal drift separation operator to remove the slowly varying drift component caused by environmental thermal effects; and using multidimensional convolution matching between the residual wavefront field and a nominal lens aberration feature library to identify static aberration patterns, generating an inverse aberration compensation driving signal. A time-varying trend predictor based on a Kalman filter framework is used to continuously estimate future thermal drift, which is then superimposed with the inverse aberration compensation driving signal to synthesize a composite correction instruction set. Based on this instruction set, the workpiece stage positioning system and the projection lens focusing system are jointly kinematically adjusted to offset the overlay error jointly introduced by aberrations and thermal deformation. This method can separate the thermal drift component, improve aberration recognition accuracy, and achieve feedforward thermal drift correction and dual-system coordinated adjustment.

A semiconductor device package. The semiconductor device package may include a base plate and a substrate assembly, the base plate including at least one through-hole, and the substrate assembly including a plurality of ceramic plates attached to the base plate, wherein at least one of the plurality of ceramic plates has a trapezoidal shape. Thus, at least one of the plurality of ceramic plates has a trapezoidal shape defined in the main plane of the base plate.

A leak check is performed on a semiconductor wafer processing tool that includes a process chamber and process gas lines, and a semiconductor wafer is processed using the semiconductor wafer processing tool if the leak check passes. Each gas line includes a mass flow controller (MFC) and normally closed valves including an upstream and downstream valves upstream and downstream of the MFC. Leak checking includes: leak checking up to the downstream valves of the gas lines with the upstream valves closed and the downstream valves of the gas lines closed; and leak checking up to the upstream valve of each the process gas line with the upstream valves of the of the process gas lines closed and with the downstream valve of the of the process gas line being leak checked open and the downstream valve of every other process gas line closed.

A pixel sensor may include a vertically arranged (or vertically stacked) photodiode region and floating diffusion region. The vertical arrangement permits the photodiode region to occupy a larger area of a pixel sensor of a given size relative to a horizontal arrangement, which increases the area in which the photodiode region can collect photons. This increases performance of the pixel sensor and permits the overall size of the pixel sensor to be reduced. Moreover, the transfer gate may surround at least a portion of the floating diffusion region and the photodiode region, which provides a larger gate switching area relative to a horizontal arrangement. The increased gate switching area may provide greater control over the transfer of the photocurrent and / or may reduce switching delay for the pixel sensor.

The application relates to the technical field of semiconductor equipment, in particular to a chuck and a semiconductor equipment, which comprises a chuck body, a flow channel is arranged in the chuck body, a plurality of convex parts are arranged on the surface of the chuck body for carrying a wafer, and the plurality of convex parts are arranged at intervals, a plurality of blocking parts are arranged in the chuck body, the blocking parts are arranged between the flow channel and the convex parts, and the blocking parts are arranged along the axial direction of the chuck body, the projection of each blocking part at least partially coincides with the projection of the corresponding convex part, and the thermal conductivity of the blocking parts is lower than that of the chuck body. By arranging the blocking parts below the high-thermal-conductivity regions, i.e. the convex parts, of the chuck, the blocking parts can reduce the thermal conductivity from the wafer to the chuck cooling in the corresponding local regions, thereby targetedly compensating the heat conduction difference caused by the structural difference between the direct contact area and the non-direct contact area, so that the temperature change trend under the plasma heating condition is consistent in each region of the wafer, and the uniformity of the wafer temperature is improved.

This disclosure provides a semiconductor device including a first pixel and a second pixel. The first pixel includes a first SPAD unit capable of sensing light in a first wavelength range to determine time of flight, and the first SPAD unit includes one or more SPADs. The second pixel includes a second SPAD unit capable of sensing light in a second wavelength range to determine a structured light pattern, and the second SPAD unit includes one or more SPADs. Through embodiments of this disclosure, an integrated sensing device is provided that can be used for both Time-of-Flight (ToF) ranging and structured light sensing, combining the advantages of both systems.