42595 results about "Semiconductor" patented technology

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

The invention provides a regeneration wafer defect detection method and system based on point cloud, and belongs to the technical field of semiconductor manufacturing detection, and the method comprises the steps: carrying out the registration and fusion processing of the point cloud data of a target wafer, and obtaining the target point cloud data; performing plane fitting on the target point cloud data to determine a reference plane; performing feature extraction on the target point cloud data relative to the reference plane to obtain feature data; positioning a defect area based on the feature data, and calculating geometric parameters of the defect area; correcting the geometric parameters by using a preset error compensation model to obtain target geometric parameters; inputting the position of the defect area, the target geometric parameter and the feature data of the corresponding defect area into a defect classification model to obtain a defect type of the defect area; and generating a defect detection result of the target wafer based on the defect types, the positions, the target geometric parameters and the feature data of all the defect areas of the target wafer. According to the invention, the efficiency and reliability of regenerated wafer defect detection are improved.

The invention discloses a multi-mode end point detection system and method for a semiconductor dry process, and relates to the field of gas concentration detection. A gas absorption cell; the reference light path adjusting unit comprises an adjustable attenuator used for adjusting signals; the first photoelectric detector is used for detecting a transmission signal; the second photoelectric detector is used for detecting a reference signal; the lateral scattered light detector is used for detecting a scattered signal of the particulate matters in the gas absorption tank; and the signal processing unit is in signal connection with the first photoelectric detector, the second photoelectric detector and the lateral scattering light detector and is used for performing compensation calculation on the transmission signal based on the reference signal and the scattering signal so as to obtain a corrected gas absorption signal. By adopting the scheme, measurement signal distortion caused by optical mirror surface pollution and particulate matter scattering interference in a semiconductor tail gas optical detection technology is avoided.

The invention belongs to the technical field of semiconductor testing, and discloses a novel automatic detection system and method for the electrostatic protection performance of a power device. A distributed parasitic parameter network model is constructed by acquiring packaging structure parameters of a to-be-tested power device and physical layout data of a test fixture, key parasitic parameter distribution is identified in combination with a time domain reflection measurement technology, a waveform distortion coefficient is calculated, and a spatio-temporal evolution model of electrostatic pulse propagation is constructed. Based on the model, a compensatory predistortion waveform is generated to counteract the parasitic effect of a transmission path, a device port response signal is collected in real time, an energy dissipation characteristic spectrum is extracted through wavelet packet decomposition, and quantitative evaluation of the electrostatic protection performance is achieved. According to the invention, the test precision and repeatability are improved, and the method is suitable for electrostatic protection tests of various novel power devices, especially high-frequency wide-band gap devices.

The invention discloses a building facility detection data intelligent analysis and report system and method, and relates to the technical field of building structure health monitoring, and the method comprises the steps: achieving the high-precision data capture in a strong light dust raising environment through a laser radar and a dual-spectrum camera of a multi-mode anti-interference collection module; a millimeter wave radar array and an IMU inertial unit of the high-risk area strengthening module penetrate through severe working conditions to monitor key structure displacement; the credibility management engine is provided with an NFC timestamp chip and a double-chain block chain, and data judicial-level credibility and operation traceability are ensured; through humidity response gel packaging and Peltier semiconductor refrigeration of the self-maintenance sensing network, node environment self-adaption and drift suppression are achieved; and the multi-stage analysis center fuses edge-cloud computing power based on federal learning, generates a dynamic risk map and automatically outputs a compliance report. Accurate and timely reference is provided for operation and maintenance decisions, and the safety management level of building facilities is effectively improved.

The invention provides an engineering test method and system for a storage chip and a medium, and belongs to the technical field of semiconductor packaging. The method comprises the following steps: acquiring read-write operation data, temperature data and voltage data of a storage chip in real time through a distributed sensor network, performing dimension reduction and segmentation processing on test data by using a multi-dimensional feature extraction algorithm, extracting statistical features and correlation features, inputting a fault prediction model constructed based on a deep learning algorithm, and performing fault prediction. Fault type and probability prediction is realized; and judging whether the chip has a fault by combining a preset threshold value, if the chip has the fault, accurately positioning a fault area by adopting a dynamic probe test technology, determining a fault time point and a trigger condition through time sequence analysis, and finally generating a fault diagnosis report and providing a repair suggestion. According to the invention, the accuracy and efficiency of fault detection of the storage chip can be effectively improved.

The invention relates to the technical field of semiconductor luminescence, and discloses a manufacturing method of a lens module, a mold, the lens module and a sensor device. The manufacturing method comprises the following steps: S1, arranging at least two cavity structures with upper and lower openings in the bearing part; the upper mold and the lower mold are each internally provided with a mold cavity with an opening in one side. And mold cavities of the upper mold and the lower mold extend into the cavity structure from the upper opening end and the lower opening end of the bearing part correspondingly to be aligned and closed. And a gap is reserved between the upper mold and the lower mold in the mold closing process. And S2, a mold cavity for mold closing is filled with the light-transmitting glue, and the redundant light-transmitting glue flows out through gaps in the peripheries of the upper mold and the lower mold and adheres to the inner wall of the bearing part. And S3, after curing, the upper mold and the lower mold are moved away, and a first lens and a second lens are formed in the two cavity structures respectively. The manufacturing method is simple and high in efficiency, and the manufactured sensor device is simple and stable in structure, good in sealing performance, high in precision and easy to optically design.

The invention relates to the technical field of semiconductor photoelectronics, and discloses a multi-physics field coupling silicon-based optical interconnection chip degradation model construction method and application, and the method comprises the steps: firstly constructing a multi-physics field coupling analysis model, and quantitatively representing the coupling relation of thermodynamics, optics, electricity and material aging through an inter-field coupling equation and a material aging dynamic model; simulating field distribution of a chip key area under multi-environment stress through finite element analysis, and extracting data; then historical degradation data is collected by combining an accelerated aging test and long-term operation monitoring, and a degradation parameter prediction model is established after data processing based on machine learning; and finally, inputting a finite element result and a prediction result into a material aging dynamic model, and finally forming a multi-physics field coupling degradation model. The problems that the prior art depends on a single physical field, degradation mechanism analysis is incomplete, and service life evaluation is inaccurate are solved, and support can be provided for reliability evaluation, structure optimization and service life prediction of the silicon-based optical interconnection chip.

The invention relates to a polishing process for improving local flatness of a silicon wafer, which belongs to the technical field of semiconductor manufacturing, and comprises the following operation steps of: 1, pretreating the silicon wafer, cleaning the silicon wafer, activating the surface of the silicon wafer, removing surface impurities and an oxide layer, and preparing for subsequent polishing; secondly, partition parameter setting is conducted, the wafer is scanned, the surface of the wafer is divided into a plurality of different areas, and independent polishing parameters are set for each area according to the material characteristics, the thickness and the preset flatness target of each area; and thirdly, dynamic polishing is conducted, specifically, multi-axis linkage polishing equipment is adopted, and the movement tracks and working parameters of the polishing head in different areas are dynamically adjusted in real time according to preset partition parameters. Through silicon wafer pretreatment, partition parameter setting and dynamic polishing process monitoring and feedback adjustment mechanisms, polishing process parameters can be accurately controlled, deviation in the polishing process can be corrected in time, and stability and consistency of polishing quality are ensured.

The invention relates to the technical field of semiconductor manufacturing, in particular to an intelligent manufacturing process optimization method and system of an integrated industrial large model. Dynamic optimal combination solution of technological parameters such as photoetching dose, etching rate and film thickness is realized; an equipment operation instruction and an abnormal intervention strategy are generated in real time, and the accuracy and timeliness of operation are improved; and cross-process collaborative scheduling and bottleneck prediction are carried out, the whole production process is optimized, and finally the yield, efficiency and flexibility of semiconductor manufacturing are improved.

The invention discloses a linearity closed-loop optimization method for a semiconductor gas sensor with adjustable voltage dynamic compensation, which relates to the technical field of gas detection and comprises the following steps: controlling the semiconductor gas sensor to start in a clean air environment, outputting an initial test voltage sequence through a voltage regulator, the method comprises the steps of collecting sensor reference resistance under different voltages, screening out initial working voltage with the minimum resistance fluctuation quantity, synchronously collecting initial environment temperature and humidity, and calibrating the sensor reference resistance based on preset temperature and resistance coefficients and humidity and resistance coefficients to obtain initial reference resistance. By dynamically adjusting the working voltage and combining real-time compensation on the environment temperature and humidity, the interference of environment factor fluctuation on the resistance characteristic of the sensitive material can be continuously counteracted, so that the linear relation between the output signal of the sensor and the target gas concentration is kept stable, the dynamic optimization of the linearity in a complex environment is realized, and the sensitivity of the sensor is improved. And more reliable basic data is provided for gas concentration detection in an industrial scene.

The invention relates to the field of semiconductors, in particular to an answer generation method and device based on a semiconductor knowledge base and a medium. The method comprises the steps of performing data association on structured knowledge according to a semiconductor domain knowledge structure to construct a class of knowledge bases; performing data recombination on the unstructured knowledge according to the layout so as to construct a second-class knowledge base; a query question is received, retrieval is executed in the first-class knowledge base and the second-class knowledge base based on a preset retrieval model, and a plurality of related knowledge fragments are obtained; determining a first fusion weight between the knowledge fragments of the same knowledge type based on the relevancy between each knowledge fragment and the query question and the update time of each knowledge fragment; determining an optimal knowledge type according to the group feature information, and determining a second fusion weight between different knowledge types according to the optimal knowledge type; and based on the first fusion weight and the second fusion weight, obtaining a reference answer according to the plurality of knowledge fragments. And the requirements of the semiconductor field on information comprehensiveness and answer accuracy are considered.

The invention discloses atomic layer etching adopting single process gas and rapidly adjusting chamber pressure. The process includes a step time designed for optimizing the surface modification and sputtering process, thereby minimizing undesirable effects. The customized waveform generator enables rapid and accurate control of the substrate bias, thereby shortening the ALE cycle time. Besides, by presetting set values for the MFC and the vacuum valve, rapid adjustment of the pressure of the cavity is achieved, traditional PID control is not needed, and therefore the efficiency and precision in semiconductor manufacturing are further improved.

The invention belongs to the technical field of nondestructive testing, and discloses a gold ore and iron ore metal content detection method. The method comprises the following steps: acquiring an XRF energy spectrum by using an X-ray tube, acquiring an LIBS spectrum by using double-pulse Nd: YAG laser, and acquiring a Raman spectrum by using a semiconductor laser; performing baseline correction on the LIBS spectrum, performing Savitzky-Golay smoothing pretreatment on the Raman spectrum, and respectively extracting three types of spectrum characteristics; constructing a physical constraint network model, inputting XRF, LIBS and Raman features, and then outputting the correction content, fusion weight and LIBS dominant factors of Fe / Au elements; and finally, through a dynamic weight fusion strategy, combining XRF, LIBS fusion weights and network output parameters, calculating to obtain the content of the gold ore and the content of the iron ore. The technical breakthrough of multi-element cooperative detection and complex matrix interference suppression is realized, and the detection precision of Fe and Au is effectively improved.

The embodiment of the invention relates to the technical field of semiconductor manufacturing, in particular to a volume calibration method, a controller and a gas mass flow verification system. Obtaining an accurate second volume verification parameter of the calibration tank when the second pipeline space is in a gas stable state, and calculating an accurate and high-precision second volume of the second pipeline space by combining a first volume verification parameter and a first volume of the calibration tank when the fourth valve is in a closed state; a target mole of gas in the calibration tank is diffused to a target pipeline space, an accurate third volume verification parameter of the calibration tank is obtained when the target pipeline space is in a gas stable state, and a third volume verification parameter of the calibration tank is obtained by combining a first volume verification parameter and a first volume of the calibration tank when a fourth valve is in a closed state; the third volume of the third pipeline space is accurate and high in precision, and the requirement of the semiconductor technology for volume precision is met.

The invention relates to the technical field of AC / DC module control, and discloses an intelligent control method and system for multi-mode switching of an AC / DC module. According to the method, a dynamic topology mapping model is constructed according to an impedance spectrum matrix, and a physical connection relation is converted into a node admittance relation network; generating an energy distribution state sequence based on the power fluctuation vector, and analyzing migration constraint conditions among different operation modes by adopting an association rule mining algorithm; when an operation mode switching instruction is detected, activating a node admittance relation network in the dynamic topology mapping model, and inputting a current energy distribution state sequence to an association rule mining algorithm; according to a real-time matching result of the node admittance relation network and the migration constraint condition, generating a switching control instruction containing an impedance adjustment gradient and a power distribution weight; and the power semiconductor execution unit transmits the switching control instruction to the AC / DC module. According to the method, multi-mode intelligent switching control of the alternating-current and direct-current module can be realized.

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

Process condition management facilitates the combination of dry development and etching into a single process chamber; eliminating the necessity for a post-dry development bake step during semiconductor manufacturing. Methods and apparatuses for rapidly instituting a large drop in process chamber pressure allow thermal dry development and an O2 flash treatment or thermal dry development and plasma hardmask open operations to take place without wafer transfer.

The invention relates to the technical field of enterprise data management, in particular to a lightweight-based enterprise data dynamic integrated management system, which is characterized in that an acquisition module is used for deploying edge computing nodes, receiving multi-source heterogeneous information streams from manufacturing execution systems and equipment logs, dynamically analyzing and standardizing the information streams, and adding metadata tags; uploading is carried out in a batch processing mode; the map construction module is used for constructing a semiconductor blood relationship map by taking the standardized key information as a blood relationship clue; a graph database is used for efficient storage, and a RESTful API interface is configured to support batch import, so that data storage and relevance expression are more flexible and efficient; the prediction module performs reasoning on the atlas by adopting a graph neural network to generate predictive risk distribution, and a correlation analysis set generated by the prediction module is stored back to the atlas in a structured manner; by introducing a multi-thread concurrent write-in and lock mechanism, the atlas supports complex combination query based on a Cypher query language, and supports multi-level and traceability query.

Development of resists are useful, for example, to form a patterning mask in the context of high-resolution patterning. Development can be accomplished using a halide-containing chemistry such as a hydrogen halide. A metal-containing resist film may be deposited on a semiconductor substrate using a dry or wet deposition technique. The resist film may be an EUV-sensitive organo-metal oxide or organo-metal-containing thin film resist. After exposure, the photopatterned metal-containing resist is developed using wet or dry development.

The invention relates to the field of semiconductor optoelectronic device manufacturing, in particular to an LED epitaxial wafer growing method capable of reducing warping. Comprising the following steps of: growing a nucleating layer on a substrate at low temperature by adopting an MOCVD (Metal Organic Chemical Vapor Deposition) process, and annealing to form a three-dimensional island-shaped structure to release stress; growing an AlGaN / GaN superlattice or gradient layer as a gradient buffer layer, and adjusting lattice constants layer by layer; a heavily doped or co-doped layer is inserted before growth of n-GaN, and thermal stress is pre-compensated by using local pressure stress; and finally, continuously growing a device layer and carrying out in-situ heat treatment to obtain the LED epitaxial wafer. The method effectively counteracts the macroscopic tensile stress caused by the difference of thermal expansion coefficients in the cooling process, and greatly improves the integrity of the epitaxial wafer.

The invention relates to the technical field of semiconductor manufacturing, in particular to a wafer pre-alignment device and method, and the device comprises a mounting platform, an XY motion platform, a rotating platform, a suction cup, and an edge detection assembly. The method comprises the steps of device correction, coarse scanning and circle center positioning, fine scanning and notch accurate positioning and alignment execution. Through software and hardware cooperation, online self-correction is used for eliminating system errors, high-order fitting and feature screening algorithms are used for restraining random errors and model errors, the repeated positioning precision, notch orientation precision and equipment consistency of the wafer pre-alignment device are improved, and the high-precision requirement for a wafer transmission system under the advanced manufacturing process can be met.

Provided are a semiconductor device for changing a link speed and a link width of a peripheral component interconnect express (PCIe) link and an operating method thereof. The semiconductor device includes the PCIe link including a plurality of lanes, and a controller configured to transceive a data link layer packet (DLLP) including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state through the PCIe link, based on a first bit error rate (BER) of a data packet received through the PCIe link and a first criterion value in the L0 state, and determine whether to perform at least one of a link speed changing operation performed in a recovery state, or a link width changing operation performed in the L0p state, based on the number of times of transition and the maximum number of times of transition.

The invention belongs to the technical field of semiconductor design automation, and provides a standard cell physical layout generation method and related equipment. The method comprises the steps of obtaining design data of a standard unit to be designed and multi-patterning process constraint parameters under a target process; according to the design data and the multi-patterning process constraint parameters, a transistor in a to-be-designed standard cell is arranged, in the arrangement process, folding and / or source-drain sharing are / is dynamically carried out on the transistor in the to-be-designed standard cell, and the feasibility of a gate cutting process and a contact through hole cutting process is synchronously detected; and after the layout of the transistors in the standard unit to be designed is completed, wiring is carried out on the standard unit to be designed by adopting a multi-network synchronous optimization strategy so as to generate a standard unit physical layout, and in the wiring process, sign-off data is fused so as to optimize wiring. Through the technical scheme provided by the invention, the generation efficiency of the standard cell physical layout can be improved.

The invention belongs to the technical field of semiconductor devices, and particularly relates to an optical waveguide device based on a glass substrate, which comprises the glass substrate and a transition layer, an X silicon-based waveguide layer is arranged on the first surface of the transition layer, a heterogeneous material chip layer is integrated on the X silicon-based waveguide layer, the first surface of the X silicon-based waveguide layer is coated with a protective layer, and the protective layer is arranged on the first surface of the transition layer. The protective layer covers the glass substrate, the X silicon-based waveguide layer and the heterogeneous material chip layer at the same time; wherein the transition layer comprises an X element which is the same as that of the X silicon-based waveguide layer, through the above structure, the optical waveguide device with multiple layers of transition function areas is provided, the problems that the surface roughness of a large glass substrate is high, and the warping possibility is higher due to size effect amplification can be solved, and the optical waveguide device is suitable for large glass substrates. On the premise of fully utilizing the advantages of low cost and high performance of the glass substrate, the design of a large-size optical waveguide device for inhibiting packaging warping is realized.

The utility model discloses a back contact battery and a photovoltaic assembly, and relates to the field of photovoltaic technology. The method is used for reducing the process difficulty of forming a patterned first transparent conductive layer during mass production and is beneficial to prolonging the service life of a screen printing plate for manufacturing the patterned first transparent conductive layer. The back contact battery comprises a semiconductor substrate, a first doped semiconductor part, a second doped semiconductor part and a first transparent conductive layer. The second doped semiconductor portion is disposed on the second region and extends to cover the first doped semiconductor portion in the overlapping region. The first transparent conductive layer is disposed on the second doped semiconductor portion. A partial region in the overlapping region is a reverse electric leakage region. And a first transparent conductive layer extending from the second region is arranged in the reverse electric leakage region. The side line of the side, close to the first area, of the first transparent conducting layer is a first side line, the first side line is of a periodically repeated convex-concave alternating structure, and transition lines between convex and concave in the convex-concave alternating structure are not parallel to the first direction.

The invention relates to the technical field of semiconductor devices, in particular to a low-working-current-density green light Micro-LED epitaxial structure and a preparation method thereof. The epitaxial structure comprises a substrate, a buffer layer, an N-type semiconductor layer, a low-temperature stress release layer, a multi-quantum well light-emitting layer and a P-type semiconductor layer. The electron blocking layer is not arranged on the multi-quantum-well light-emitting layer, the multi-quantum-well light-emitting layer comprises four sub-layers including a first light blue light multi-quantum-well layer, a second blue light multi-quantum-well layer, a third green light multi-quantum-well layer and a fourth light blue light multi-quantum-well layer, and the In component content in the third green light multi-quantum-well layer is larger than that in other layers. The third cyan light multi-quantum well layer is a main light-emitting unit and is not provided with an electron blocking layer, so that the blocking effect on hole injection can be eliminated, the hole injection efficiency of the P-type semiconductor layer is remarkably improved, and the matching degree of electron hole concentration in a multi-quantum well light-emitting layer region is improved.

The utility model discloses a semiconductor device, which belongs to the field of semiconductors, and at least comprises a substrate; the well region is arranged in the substrate; the two drift regions are arranged in the well region at intervals, and shallow trench isolation structures are arranged in the drift regions; the body region is arranged in the well region between the two drift regions; the vertical grid electrode is located in the body region, and the vertical grid electrode extends into the well region from the surface of the substrate; the source doped regions are respectively arranged in the body regions on the two sides of the vertical grid electrode; the drain doping region is arranged in the drift region; and the planar grid electrode is arranged around the vertical grid electrode and the source doping region and covers part of the body region, part of the well region and part of the shallow trench isolation structure. According to the semiconductor device provided by the utility model, the characteristic on-resistance can be reduced and the performance of the semiconductor device can be improved under the condition that the breakdown voltage is not changed.

The invention discloses a semiconductor processing defect detection method based on artificial intelligence, and relates to the technical field of semiconductor processing defect detection. The method comprises the following steps: acquiring wafer position coordinates, an optical image and process equipment dynamic parameter data; generating a microdefect feature matrix by using a multi-scale Gaussian filtering model and an asymmetric convolution algorithm; converting the process parameters into a position-associated process parameter matrix through space-time mapping and a correlation matrix algorithm; performing radial pooling and multi-expansion-rate cavity convolution algorithms on the fused feature tensor, and extracting global and local feature vectors; generating a defect probability distribution diagram by adopting a polar coordinate dynamic weighted fusion algorithm; and outputting the defect coordinates and the type identifier through an adaptive threshold algorithm, and generating a process equipment control signal according to predefined logic. Through an innovative multi-source data fusion calculation model, accurate defect identification and process closed-loop control are realized, and the detection precision and efficiency are improved.

The invention belongs to the technical field of semiconductors, and discloses a method for manufacturing a sigma trench in a semiconductor device, which comprises the following steps of: providing a substrate which comprises a first device region and a second device region; a PMOS (P-channel Metal Oxide Semiconductor) region gate and a PMOS gate mask layer are formed on the first active region of the first device region; exposing the top of the PMOS gate mask layer outside the first device region photoresist layer; depositing a deposition silicon oxide layer on the top of the second device region and the top of the PMOS gate mask layer; removing the photoresist layer in the first device region; etching to remove the natural silicon oxide layer on the surface of the first active region, further etching silicon in the first active region, and forming a U-shaped groove in the semiconductor substrate in the first device region; and carrying out TMAH etching on the U-shaped groove to form a sigma groove. According to the invention, in the process of embedding germanium-silicon into the source and the drain, the height difference between the PMOS and the NMOS is avoided, and the subsequent process is not influenced.