62999 results about "Semiconductor" patented technology

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

The invention relates to the technical field of intelligent control of test equipment, and discloses a semiconductor device test equipment control system and method based on industrial data processing, and the method comprises the steps: collecting multi-source heterogeneous data of semiconductor device test equipment, and carrying out the preprocessing; constructing a structural causal model, and performing root cause identification through anti-fact reasoning by using the structural causal model; constructing an abnormal test fingerprint and a knowledge base; generating an intervention scheme, evaluating the generated intervention scheme, and selecting an optimal intervention scheme; processing the detected anomaly, and generating and implementing a preventive control strategy based on historical anomaly data and a causal analysis result; according to the invention, by introducing innovative technologies such as causal inference, anti-factual inference, abnormal test fingerprint identification and Monte Carlo tree search, intelligent control of semiconductor test equipment is realized.

The invention discloses an automatic identification method and system for a wafer internal defect image of a 3D stacked chip, and belongs to the technical field of semiconductor manufacturing and detection. According to the method, optical, X-ray and ultrasonic image data are synchronously acquired based on a multi-modal imaging technology, imaging parameters are dynamically adjusted to adapt to different wafer levels and material characteristics, multi-modal features are extracted in combination with layered filtering and denoising, multi-resolution registration and a self-supervised deep learning method, and micron-sized defects are positioned by using an attention mechanism. And further constructing a defect-process parameter correlation model through reinforcement learning, generating a closed-loop process optimization instruction, and transmitting the closed-loop process optimization instruction to an execution system. The system comprises a multi-modal imaging module, a noise suppression module, a deep learning analysis module and a process optimization module, and supports edge computing deployment. According to the invention, the internal defect detection efficiency and precision of the multi-layer stacked chip are significantly improved, real-time closed-loop control of detection-analysis is realized, the wafer manufacturing quality risk is reduced, and the method is suitable for intelligent defect detection of an advanced packaging production line.

Process condition management facilitates the combination of dry development and etching into a single process chamber; eliminating the necessity for a post-dry development bake step during semiconductor manufacturing. Methods and apparatuses for rapidly instituting a large drop in process chamber pressure allow thermal dry development and an O2 flash treatment or thermal dry development and plasma hardmask open operations to take place without wafer transfer.

The invention relates to the technical field of semiconductor lasers, in particular to a laser based on a bimetallic Bragg grating and a top surface HR reflecting film, which comprises a gain chip, a first high-reflection HR film is plated on the left end surface of the gain chip, and a first anti-reflection AR film is plated on the right end surface of the gain chip. A metal Bragg grating waveguide is arranged on the right side of the gain chip, the right end face of the gain chip and the left end face of the metal Bragg grating waveguide are aligned and attached to form an outer cavity structure, and the left end face of the metal Bragg grating waveguide is plated with a second anti-reflection AR film. The right end face of the metal Bragg grating waveguide is plated with a third anti-reflection AR film. Performance test is carried out on the laser provided by the invention, and test results show that the line width is 0.6 kHz, the SMSR is 63dB, and the threshold current is 22mA, thereby verifying the effectiveness of the laser provided by the invention.

The invention relates to a liquid medicine concentration automatic control correction method and system in the technical field of semiconductor manufacturing, and the method comprises the steps: if the concentration deviation exceeds a preset threshold value, comparing real-time monitoring data with a chemical equilibrium model, obtaining the offset of a reaction rate, and judging the specific parameters of the liquid supplementing amount and the adjustment time; a proportional-integral control algorithm is combined with a trigger condition and a liquid supplementing parameter, the liquid medicine concentration is dynamically adjusted, a compensation factor is introduced for temperature fluctuation, and an adjusted concentration control instruction is obtained; liquid level distribution data in the cleaning tank are synchronously collected through a liquid level detection device, and whether the uniformity of the liquid medicine in the tank reaches a preset standard or not is judged in combination with the adjusted concentration control instruction; and continuously acquiring a stable distribution result, comparing the stable distribution result with an initial data set, judging the optimization degree of the control precision and the response speed, and obtaining a concentration fluctuation range and a uniformity index after dynamic adjustment.

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor defect detection method and system based on deep learning. The method comprises the following steps: step 1, multiband cooperative imaging and dynamic scanning control; 2, performing multi-scale feature fusion and defect identification; 3, dynamic threshold judgment and multi-scale feature fusion network optimization: dynamically adjusting a judgment threshold according to probability distribution characteristics of a current batch defect thermodynamic diagram, applying an offset to the threshold in combination with a wafer process type, and determining the offset according to a balance relationship between a false drop rate and an omission rate in historical data; critical samples and misjudgment samples with classification confidence close to a threshold value in historical detection are periodically screened, incremental learning is performed on the last layer of the multi-scale feature fusion network, and upstream network weight is frozen to prevent feature drift. Through fine image processing, multi-band information fusion, dynamic threshold adjustment, incremental learning and other mechanisms, the defect detection efficiency and accuracy in the semiconductor manufacturing process can be effectively improved, and the detection performance is continuously optimized.

The invention provides a regeneration wafer defect detection method and system based on point cloud, and belongs to the technical field of semiconductor manufacturing detection, and the method comprises the steps: carrying out the registration and fusion processing of the point cloud data of a target wafer, and obtaining the target point cloud data; performing plane fitting on the target point cloud data to determine a reference plane; performing feature extraction on the target point cloud data relative to the reference plane to obtain feature data; positioning a defect area based on the feature data, and calculating geometric parameters of the defect area; correcting the geometric parameters by using a preset error compensation model to obtain target geometric parameters; inputting the position of the defect area, the target geometric parameter and the feature data of the corresponding defect area into a defect classification model to obtain a defect type of the defect area; and generating a defect detection result of the target wafer based on the defect types, the positions, the target geometric parameters and the feature data of all the defect areas of the target wafer. According to the invention, the efficiency and reliability of regenerated wafer defect detection are improved.

The invention discloses a semiconductor packaging test optimization method and system, and relates to the field of packaging testing, and the method comprises the steps: collecting and preprocessing a multi-dimensional abnormal signal, generating a standard data set, carrying out the feature extraction of data in the standard data set, obtaining a standard feature vector, and inputting the standard feature vector into a constructed abnormality detection model, the method comprises the steps of obtaining an abnormal signal report, distributing a test item for a chip through the abnormal signal report and a predefined mapping rule, generating a structure map and an electrical map, inputting the structure map and the electrical map into a multi-mode Transform model, outputting a fusion map, calculating a test weight according to the fusion map, and generating a test weight map and a region priority list. According to the invention, the testing efficiency, the micro defect detection precision and the boundary failure prediction of advanced packaging are improved.

The invention discloses a solar cell and a manufacturing method thereof, and a photovoltaic module, and relates to the field of photovoltaic technology. The solar cell includes: a semiconductor substrate having a first surface including a first region and a second region; the second area comprises an edge area and a middle area, each of the edge area and the middle area comprises a step structure recessed towards the second surface, and the step depth of the step structure of the edge area of the second area is larger than that of the step structure of the middle area of the second area; and the first doping layer is arranged on the first region, and the height of the bottom wall of the step structure in the middle region of the second region is lower than that of the first doping layer. The first passivation layer is arranged on the side, away from the semiconductor substrate, of the first doping layer and arranged on the second area. According to the embodiment of the invention, the thickness along the splitting direction is reduced, so that the splitting difficulty is reduced, meanwhile, the recombination of current carriers is reduced, and the passivation effect is improved.

The invention discloses a multi-AGV cooperative path planning and scheduling method for chip intelligent storage, and belongs to the field of high-precision electronic component intelligent storage. The method comprises the following steps: running according to a highway guide strategy, and pre-allocating tasks of each robot by using an MTSP problem according to different task types before path planning; an improved A * algorithm is provided, a global thermodynamic diagram congestion prediction and turning waiting heuristic method is introduced to establish a space-time joint search model, and a transportation path is optimized by greatly reducing the number of nodes needing to be searched and the turning and waiting times of the AGV, so that the efficiency is improved; in addition, a series of priority rules are also provided, and appearing conflicts are eliminated. Experiments verify the effectiveness of the method, high-reliability and low-vibration dust-free workshop AGV collaborative scheduling can be realized, and an efficient and safe warehousing automation solution is provided for semiconductor manufacturing.

The invention provides a third-generation semiconductor device multi-physical field coupling effect dynamic monitoring method and system, and relates to the technical field of semiconductors, and the method comprises the steps: collecting the data of a temperature field, an electric field, a magnetic field and a stress field through a complementary sensor array, constructing a feature tensor, inputting the feature tensor into a pre-trained graph neural network, and extracting a coupling effect dynamic evolution rule; on-line analysis and prediction are carried out by using an adaptive time window and a recurrent neural network, a multi-field coupling correlation degree evaluation model is established, an early warning level is determined according to the deviation between the coupling correlation degree and an early warning threshold value, and device risk evaluation and maintenance suggestions are generated, so that early warning of the failure risk of the semiconductor device is realized.

The invention provides a wafer edge defect detection method and system based on image recognition and a storage medium, and belongs to the technical field of semiconductor manufacturing, and the method comprises the steps: processing annular image data, and obtaining target image data; inputting the target image data into the edge defect prediction model to obtain a defect probability distribution diagram; based on the defect probability distribution diagram, identifying a pixel region with a probability value greater than or equal to a preset threshold value as a candidate defect region; performing feature extraction on the candidate defect region to obtain a target feature vector; inputting the target feature vector into a defect classification model, and determining the defect type and classification confidence of the candidate defect region; based on the defect type and / or the classification confidence, screening out a target defect area from the candidate defect areas; obtaining three-dimensional point cloud data of the target defect area, and calculating three-dimensional geometric parameters of the target defect area based on the three-dimensional point cloud data; and determining a detection result of the target wafer based on the defect type and the three-dimensional geometric parameters.

Various embodiments herein relate to methods, apparatus, and systems for baking metal-containing on a semiconductor substrate in the presence of a reactive gas species. For example, the method may include receiving the substrate in a process chamber, the substrate having a photoresist layer thereon, where the photoresist layer includes a metal-containing photoresist material; flowing a reactive gas species from a gas source, through a gas delivery line, into the process chamber, and exposing the substrate to the reactive gas species in the process chamber; and baking the photoresist layer while the substrate is exposed to the reactive gas species.

The invention provides a solar cell and a preparation method thereof, and a photovoltaic module, the rear surface of a semiconductor substrate is provided with a first region and a second region which are adjacent to each other, and the first region is provided with a first sub-region and first overlapping regions located at the two sides of the first sub-region; the first overlapping area is provided with a tunneling layer, a first doped conductive layer, a passivation layer, a second doped conductive layer and a first transparent conductive layer, the length of the first overlapping area in the first direction is D1, and the first direction is parallel to the surface where the semiconductor substrate is located; the rear surface of the semiconductor substrate is also provided with a third region and a fourth region which are adjacently arranged, and the third region is provided with a third sub-region and third overlapping regions located at the two sides of the third sub-region; the third overlapping region is provided with a tunneling layer, a first doped conductive layer, a passivation layer, a second doped conductive layer and a first transparent conductive layer, the length of the third overlapping region in the first direction is D2, and D1 is different from D2.

The invention discloses a multi-mode end point detection system and method for a semiconductor dry process, and relates to the field of gas concentration detection. A gas absorption cell; the reference light path adjusting unit comprises an adjustable attenuator used for adjusting signals; the first photoelectric detector is used for detecting a transmission signal; the second photoelectric detector is used for detecting a reference signal; the lateral scattered light detector is used for detecting a scattered signal of the particulate matters in the gas absorption tank; and the signal processing unit is in signal connection with the first photoelectric detector, the second photoelectric detector and the lateral scattering light detector and is used for performing compensation calculation on the transmission signal based on the reference signal and the scattering signal so as to obtain a corrected gas absorption signal. By adopting the scheme, measurement signal distortion caused by optical mirror surface pollution and particulate matter scattering interference in a semiconductor tail gas optical detection technology is avoided.

The invention relates to the technical field of semiconductor chemical mechanical polishing, in particular to a pressure-adjustable double-frequency ultrasonic-assisted semiconductor chemical mechanical polishing device which comprises a rotary table, and a tray, a lower vibration plate, an upper vibration plate, a magnetic sheet and a polishing pad are sequentially stacked and fixed to the upper surface of a table plate of the rotary table from bottom to top. A piezoelectric ceramic piece is fixed to the middle of the lower surface of the upper vibration plate, a retaining sleeve is eccentrically placed on the upper surface of the polishing pad, a threaded sleeve is in threaded connection with the upper end of the outer side face of the retaining sleeve, a damping spring is fixed to the outer top face of the threaded sleeve, a supporting piece is fixed to the upper end of the damping spring, and an inner ring of a second electric sliding ring is fixed to the upper surface of the supporting piece. A transmission shaft is fixedly assembled in an inner ring of the second electric slip ring, a clamping sleeve is fixed to the lower end of the transmission shaft, and an ultrasonic vibrator is fixedly assembled in the clamping sleeve. The method solves the problems that an existing semiconductor chemical mechanical polishing technology is low in polishing speed, poor in surface quality after polishing and low in polishing qualification rate, and is suitable for semiconductor chemical mechanical polishing.

The invention provides a full-layout defect rapid detection system based on pattern matching and classification, which relates to the technical field of semiconductor manufacturing and comprises a data acquisition and multi-source fusion module, a self-adaptive preprocessing module, a dynamic pattern matching module, a multi-source feature fusion module and a closed-loop optimization and output module, the dynamic mode matching module dynamically generates a defect template from real-time data through a clustering algorithm (such as DBSCAN) and a generative adversarial network (GAN), the speed and accuracy of defect detection are remarkably improved in combination with reinforcement learning filtering and region focusing technologies of the self-adaptive preprocessing module, a detection strategy can be adaptively adjusted according to the real-time data, and the defect detection accuracy is improved. According to the method, a high-risk area is preferentially matched, and GPU parallel computing acceleration processing is performed, so that the detection time is shortened to 50% or below of that of a traditional method, deformation or fuzzy defects can be effectively identified, the false alarm rate is reduced by about 30%, and high-quality input is provided for subsequent matching and classification.

The invention discloses a solar cell and a manufacturing method thereof, and a photovoltaic module, and relates to the field of photovoltaic technology. The solar cell includes: a semiconductor substrate having a first surface including a first region and a second region adjacent to a first cut side; the second region comprises a step structure, an included angle is formed between the side wall of the step structure and the thickness direction of the semiconductor substrate, the first region is provided with a first pyramid structure, and the bottom wall of the step structure is provided with a first texture structure or a second pyramid structure; the first doping layer is arranged on the first region, and the height of the bottom wall of the step structure is lower than that of the first doping layer; the first passivation layer is arranged on one side, deviating from the semiconductor substrate, of the first doping layer and is arranged on the second region; the second passivation layer is arranged on the edge, close to the second area, of the first area, part of the second area and the first cutting side face. The passivation effect near the cutting side face is improved, carrier recombination is reduced, and the photoelectric conversion efficiency is improved.

The invention relates to the technical field of MOS semiconductors, and discloses a silicon carbide thick-bottom oxide layer groove MOS structure and a preparation method thereof, the silicon carbide thick-bottom oxide layer groove MOS structure comprises a plurality of parallel MOS cells, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the lightly doped N layer is arranged in the middle of the N drift layer, the arc-shaped contour design with the inclined top is introduced to the two sides, the injection area is accurately controlled through the photoetching technology, the phenomenon that the edge electric field concentration of the N drift layer is effectively dispersed is effectively dispersed, in this way, electric field distribution is more uniform, breakdown voltage is improved, and local electric field concentration is reduced; moreover, the contact between the laterally symmetrical P-layer and the N substrate layer enhances the charge balance capability, and reduces the leakage current.

Development of resists are useful, for example, to form a patterning mask in the context of high-resolution patterning. Development can be accomplished using an organic vapor such as a carboxylic acid. In some implementations, the organic vapor is trifluoroacetic acid. In some implementations, the organic vapor is hexafluoro-acetylacetone. A metal-containing resist film such as an EUV-sensitive organo-metal oxide may be deposited on a semiconductor substrate using a dry or wet deposition technique. The metal-containing resist film on the semiconductor substrate may be developed using the organic vapor, or residue of metal-containing resist material formed on surfaces of a process chamber may be removed using the organic vapor.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

The invention belongs to the technical field of semiconductor testing, and discloses a novel automatic detection system and method for the electrostatic protection performance of a power device. A distributed parasitic parameter network model is constructed by acquiring packaging structure parameters of a to-be-tested power device and physical layout data of a test fixture, key parasitic parameter distribution is identified in combination with a time domain reflection measurement technology, a waveform distortion coefficient is calculated, and a spatio-temporal evolution model of electrostatic pulse propagation is constructed. Based on the model, a compensatory predistortion waveform is generated to counteract the parasitic effect of a transmission path, a device port response signal is collected in real time, an energy dissipation characteristic spectrum is extracted through wavelet packet decomposition, and quantitative evaluation of the electrostatic protection performance is achieved. According to the invention, the test precision and repeatability are improved, and the method is suitable for electrostatic protection tests of various novel power devices, especially high-frequency wide-band gap devices.

Dry development or dry removal of metal-containing extreme ultraviolet radiation (EUV) photoresist is performed in atmospheric conditions or performed in process tools without vacuum equipment. Dry removal of the metal-containing EUV photoresist may be performed under atmospheric pressure or over-atmospheric pressure. Dry removal of the metal-containing EUV photoresist may be performed with exposure to an air environment or with non-oxidizing gases. A process chamber or module may be modified or integrated to perform dry removal of the metal-containing EUV photoresist with baking, wafer cleaning, wafer treatment, or other photoresist processing function. In some embodiments, the process chamber for dry removal of the metal-containing EUV photoresist includes a heating assembly for localized heating of a semiconductor substrate and a movable discharge nozzle for localized gas delivery above the semiconductor substrate.

The invention discloses a semiconductor device communication system and method based on an SECS / GEM protocol. The system comprises an SECS / GEM protocol processing module, a PLC communication module and a service logic processing module. The protocol processing module realizes message coding and decoding and state management through an HSMS / GEM layered architecture, and supports equipment capability dynamic negotiation; the PLC communication module adopts a factory mode to adapt to a multi-manufacturer controller to realize online mapping of a physical register and a logic address; and the business logic module dynamically loads the command processor based on a reflection mechanism, and realizes multi-condition event triggering through a rule engine. The method comprises the processes of system initialization, message priority scheduling, composite alarm processing and exception recovery, and the equipment integration efficiency and the communication reliability are remarkably improved. The method solves the problems of rigid parameter mapping, single event processing and poor equipment compatibility of a traditional scheme, and can be widely applied to equipment automation control of scenes such as semiconductor wafer manufacturing and packaging testing.

The invention discloses a defect file and image number association method based on multi-format analysis, and relates to the technical field of semiconductor detection and data analysis, and the method comprises the following steps: constructing a multi-format rule base, receiving batch Klarf files and corresponding defect image folders, and extracting image numbers in defect image file names; reading field names of a preset number of Defect data of the Klarf file, matching the field names with the multi-format rule base, and selecting an analysis strategy according to a matching result by adopting a self-adaptive analysis algorithm; the analyzed Defect data are preprocessed, the association confidence coefficient is calculated through a three-layer verification algorithm, and an association result table is generated; according to the invention, automation, standardization and high reliability of semiconductor defect detection data processing are realized.

The invention discloses an irradiation-reinforced SiC super-junction MOS (Metal Oxide Semiconductor) structure and a preparation process thereof, and belongs to the technical field of MOS semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; by arranging the lightly doped N layer in the middle of the N drift layer and arranging the laterally symmetrical trapezoidal P-layers on the two sides of the N drift layer, the device can interact with electrons in the N drift layer, accelerate carrier recombination, reduce the influence of redundant carriers on the performance of the device, effectively reduce the performance degradation caused by irradiation, and improve the performance of the device. According to the invention, the concave heavily-doped N layer is formed at the bottom end of the lightly-doped N layer, so that the carrier concentration of the region can be greatly improved, and the conductivity is remarkably enhanced.

The invention discloses a silicon carbide TrenchMOS device and a manufacturing method thereof, and belongs to the field of semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of each MOS cell; the arc-shaped lightly-doped N layer is additionally arranged in the middle of the arc-shaped heavily-doped N layer, electric field distribution under reverse bias is smoothed through the doping concentration lower than that of the heavily-doped N layer, the interface electric field sudden change risk is reduced, dynamic loss is reduced, meanwhile, the doping concentration of the central area is diluted through the arc-shaped inner side lightly-doped N layer, a depletion area is promoted to be expanded, and the performance of the device is improved. Electric field distribution between drain gates is optimized, and stray capacitance is reduced to improve high-frequency performance.

The invention relates to the field of semiconductor manufacturing, and discloses a wafer processing quality backtracking evaluation method driven by a cross-modal knowledge graph, comprising the following steps: acquiring and preprocessing time sequence process data and text log data; modeling the time series data by adopting a long short-term memory network to predict the defect probability, extracting entities and relationships from a text by adopting a BERT model, and respectively constructing a process knowledge graph, a defect knowledge graph and an equipment knowledge graph; aligning the cross-modal features by using a generative adversarial network, and fusing the cross-modal features into a unified cross-modal knowledge graph; based on the unified atlas, probability backtracking reasoning of defect causes is carried out, and an active process parameter correction strategy is generated; and outputting a comprehensive quality score through the self-weighted dynamic evaluation model. According to the method, intelligent closed loop from passive diagnosis to active optimization can be realized, the accuracy and efficiency of defect positioning are remarkably improved, and a dynamic and comprehensive quality evaluation means is provided.

Process condition management facilitates the combination of dry development and post-development treatment into a single process chamber; eliminating the necessity for a post-dry development bake step in a separate chamber during semiconductor manufacturing. Thermal dry development and plasma dry development may be performed in the same chamber. Thermal dry development, plasma dry development and passivation such as an O2 flash treatment; or thermal dry development, plasma dry development, passivation and hardening operations are enabled without wafer transfer.