79724 results about "Semiconductor" patented technology

A semiconductor device with a metal foil and a sealing resin material. Metal foil is formed integrally with the sealing resin layer.

The invention provides a semiconductor defect detection and process optimization method based on deep learning. The method comprises the following steps: acquiring semiconductor wafer surface multispectral image data, wafer reflectivity distribution data and thickness distribution data through multispectral imaging equipment; performing multi-modal fusion preprocessing to generate a defect enhanced image; extracting micro-nano scale topological features of the surface of the wafer through a lattice structure guided deep learning network; performing frequency domain-space domain joint modeling on the topological features to generate a defect feature energy distribution diagram; fusing real-time process parameter data to dynamically classify defect features and output defect types and confidence coefficients; generating a process equipment control instruction according to the defect classification result; a defect cause knowledge graph is constructed through a causal inference engine, and a process optimization scheme is output; and feeding back the optimized process parameters to the semiconductor manufacturing equipment to form closed-loop control. The semiconductor manufacturing efficiency and the product quality can be improved, and the production cost is reduced.

Disclosed are methods of microelectronic processing to reveal conductive vias that are at least partially embedded in a bulk semiconductor, and resulting structures. A method of forming a microelectronic structure includes revealing the plurality of conductive vias from a back surface of the bulk semiconductor and forming a protective cap on each of the conductive vias on the back surface of the bulk semiconductor. The protective caps can be patterned or disposed selectively onto the conductive vias. The protective caps can cover the conductive vias or also cover a portion of the bulk semiconductor surrounding the conductive vias. The back surface of the bulk semiconductor is etched to form protruding conductive vias, which can be surrounded by sleeves of the bulk semiconductor. A dielectric layer is deposited over the back surface and planarized to reveal the plurality of conductive vias from the back surface.

The invention relates to the technical field of intelligent control of test equipment, and discloses a semiconductor device test equipment control system and method based on industrial data processing, and the method comprises the steps: collecting multi-source heterogeneous data of semiconductor device test equipment, and carrying out the preprocessing; constructing a structural causal model, and performing root cause identification through anti-fact reasoning by using the structural causal model; constructing an abnormal test fingerprint and a knowledge base; generating an intervention scheme, evaluating the generated intervention scheme, and selecting an optimal intervention scheme; processing the detected anomaly, and generating and implementing a preventive control strategy based on historical anomaly data and a causal analysis result; according to the invention, by introducing innovative technologies such as causal inference, anti-factual inference, abnormal test fingerprint identification and Monte Carlo tree search, intelligent control of semiconductor test equipment is realized.

The invention relates to the technical field of MOS semiconductors, and discloses a variably doped planar gate silicon carbide VDMOS device and a preparation process thereof, the variably doped planar gate silicon carbide VDMOS device comprises a plurality of MOS cells which are parallel to each other, and each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, and a lightly doped N layer is arranged in the middle of the N drift layer of a single MOS cell; lateral symmetric P-layers are arranged in the single MOS cell and located on the left side and the right side of the N drift layer, and the section contours of the corresponding sides of the lateral symmetric P-layers on the two sides are in an arc shape. By arranging the lightly doped N layer in the middle of the N drift layer and introducing the arc-shaped laterally-symmetrical P-layers to the two sides, the electric field distribution of the device is optimized, the local electric field concentration is reduced, the breakdown voltage is remarkably improved, and the charge balance capability is enhanced and the leakage current is reduced through the contact between the laterally-symmetrical P-layers and the N substrate layer.

The invention discloses a power semiconductor device aging on-line diagnosis method, which relates to the field of power electronics, and comprises the following steps: integrating an intelligent sensor and an aging test circuit, and establishing a multi-physics field coupling simulation model; based on the multi-physics field coupling simulation model, evaluating the aging state of the current device to obtain the health index of the device; based on the multi-dimensional data matrix, constructing an anomaly detection model, and outputting an anomaly detection result; predicting the failure probability and the remaining service life of the semiconductor device according to an abnormal detection result; generating a maintenance suggestion based on the predicted failure probability and remaining useful life of the semiconductor device; according to the method, the maintenance suggestion is generated according to the prediction result, the user is guided to take preventive maintenance measures in time, the accuracy of aging state evaluation is improved, the timeliness of fault early warning is enhanced, and economic losses and technical risks caused by sudden faults are reduced.

The invention relates to the technical field of semiconductor manufacturing, and discloses a semiconductor wafer etching method with a detection function. The method comprises the following steps: acquiring initial image data of a wafer surface through an optical detection device, and extracting geometric features and defect distribution information; processing through a multi-scale feature fusion algorithm, identifying an abnormal region and classifying defect types; dynamically adjusting process parameters of etching equipment according to defect conditions, and planning a self-adaptive etching path; during etching, a real-time monitoring module is used for collecting data, and etching parameters are corrected through a feedback control mechanism; and after etching, the etching precision is secondarily detected and verified by means of a multispectral imaging technology. According to the method, defects can be accurately positioned, the etching process is optimized, the etching precision and quality are effectively improved, the rejection rate is reduced, and the efficiency and reliability of semiconductor wafer manufacturing are improved.

The invention relates to the technical field of semiconductors, and particularly discloses a multiband LED chip and a preparation method thereof, and a white light LED light source, the LED chip comprises a light-emitting layer, and the light-emitting layer comprises a first cyan light multi-quantum well layer, a second long-wave blue light multi-quantum well layer, a third short-wave blue light multi-quantum well layer and a fourth purple light multi-quantum well layer which are sequentially stacked in the epitaxial direction; the first cyan light multi-quantum well layer, the second long-wave blue light multi-quantum well layer, the third short-wave blue light multi-quantum well layer and the fourth purple light multi-quantum well layer are each of a periodic structure formed by alternately stacking well layers and barrier layers, and the light-emitting wavelengths of the first cyan light multi-quantum well layer, the second long-wave blue light multi-quantum well layer, the third short-wave blue light multi-quantum well layer and the fourth purple light multi-quantum well layer are sequentially decreased. And the forbidden band widths of the barrier layers are sequentially decreased. According to the LED chip, the overall excitation efficiency can be effectively improved, and the output full-spectrum white light LED light source is higher in color rendering index, better in stability, less in damage to human eyes and high in light emitting efficiency.

To solve the problem in which: electric charges generated by a tunnel effect increase in proportion to the area of a region where the electric charges are detected; and when the area of the region where the electric charges are detected is reduced, light detection efficiency may be reduced.SOLUTION: The magnitude of the potential of a fourth semiconductor region is lower than the magnitude of the potential of a portion between the fourth semiconductor region and a third semiconductor region, and the difference between the magnitude of the potential of a first semiconductor region and the magnitude of the potential of a second semiconductor region is larger than the difference between the magnitude of the potential of the fourth semiconductor region and the magnitude of the potential of the portion between the fourth semiconductor region and the third semiconductor region. The magnitude of the potential of the third semiconductor region is lower than the magnitude of the potential of the fourth semiconductor region, and the difference between the magnitude of the potential of the first semiconductor region and the magnitude of the potential of the third semiconductor region is larger than the difference between the magnitude of the potential of the second semiconductor region and the magnitude of the potential of the fourth semiconductor region.SELECTED DRAWING: Figure 1

The invention discloses an automatic identification method and system for a wafer internal defect image of a 3D stacked chip, and belongs to the technical field of semiconductor manufacturing and detection. According to the method, optical, X-ray and ultrasonic image data are synchronously acquired based on a multi-modal imaging technology, imaging parameters are dynamically adjusted to adapt to different wafer levels and material characteristics, multi-modal features are extracted in combination with layered filtering and denoising, multi-resolution registration and a self-supervised deep learning method, and micron-sized defects are positioned by using an attention mechanism. And further constructing a defect-process parameter correlation model through reinforcement learning, generating a closed-loop process optimization instruction, and transmitting the closed-loop process optimization instruction to an execution system. The system comprises a multi-modal imaging module, a noise suppression module, a deep learning analysis module and a process optimization module, and supports edge computing deployment. According to the invention, the internal defect detection efficiency and precision of the multi-layer stacked chip are significantly improved, real-time closed-loop control of detection-analysis is realized, the wafer manufacturing quality risk is reduced, and the method is suitable for intelligent defect detection of an advanced packaging production line.

The invention relates to the technical field of vacuum extraction control, and discloses a multi-stage vacuum extraction control system which comprises a central processing unit, a multi-stage vacuum pump set control module, a vacuum degree dynamic monitoring module and the like. The multi-stage vacuum pump set control module coordinates all stages of pumps to work according to a preset vacuum degree target value, and the vacuum degree dynamic monitoring module collects pressure data in real time and judges abnormity. The pressure gradient adjusting module adjusts the extraction rate of the adjacent pump to maintain the vacuum gradient stable when the pressure is abnormal, and the abnormity response module controls starting and stopping or rate correction of the pump according to the abnormity level. In addition, the system further has the functions of vacuum pump efficiency evaluation, pressure feedback compensation, leakage detection, redundancy switching, historical data backtracking, collaborative optimization and the like. The system can accurately control the vacuum degree, efficiently deal with abnormities and realize equipment state monitoring and optimization, and is widely applied to the fields with high requirements on the vacuum degree, such as semiconductor manufacturing and vacuum coating.

Methods for making thin-films on semiconductor substrates, which may be patterned using EUV, include: depositing the organometallic polymer-like material onto the surface of the semiconductor substrate, exposing the surface to EUV to form a pattern, and developing the pattern for later transfer to underlying layers. The depositing operations may be performed by chemical vapor deposition (CVD), atomic layer deposition (ALD), and ALD with a CVD component, such as a discontinuous, ALD-like process in which metal precursors and counter-reactants are separated in either time or space.

Process condition management facilitates the combination of dry development and etching into a single process chamber; eliminating the necessity for a post-dry development bake step during semiconductor manufacturing. Methods and apparatuses for rapidly instituting a large drop in process chamber pressure allow thermal dry development and an O2 flash treatment or thermal dry development and plasma hardmask open operations to take place without wafer transfer.

The invention relates to the technical field of semiconductor lasers, in particular to a laser based on a bimetallic Bragg grating and a top surface HR reflecting film, which comprises a gain chip, a first high-reflection HR film is plated on the left end surface of the gain chip, and a first anti-reflection AR film is plated on the right end surface of the gain chip. A metal Bragg grating waveguide is arranged on the right side of the gain chip, the right end face of the gain chip and the left end face of the metal Bragg grating waveguide are aligned and attached to form an outer cavity structure, and the left end face of the metal Bragg grating waveguide is plated with a second anti-reflection AR film. The right end face of the metal Bragg grating waveguide is plated with a third anti-reflection AR film. Performance test is carried out on the laser provided by the invention, and test results show that the line width is 0.6 kHz, the SMSR is 63dB, and the threshold current is 22mA, thereby verifying the effectiveness of the laser provided by the invention.

The invention provides a back contact cell, a manufacturing method and a photovoltaic module, and belongs to the technical field of solar cells. The back contact battery comprises a semiconductor substrate, wherein a first surface of the semiconductor substrate comprises a first region and a second region which are alternately arranged along a first direction; the first semiconductor layer is at least partially arranged on the first region of the semiconductor substrate; the second semiconductor layer is at least partially arranged in the second area of the semiconductor substrate; the first electrode is arranged on the first semiconductor layer in the first region; the second electrode is arranged on the second semiconductor layer in the second region; the first semiconductor layer extends between the second semiconductor layer in the second region and the semiconductor substrate to form an overlapping part, and the second electrode covers at least part of the overlapping part; and / or, the second semiconductor layer extends to the first semiconductor layer in the first region to form an overlapping part, and the first electrode covers at least part of the overlapping part.

The invention relates to a liquid medicine concentration automatic control correction method and system in the technical field of semiconductor manufacturing, and the method comprises the steps: if the concentration deviation exceeds a preset threshold value, comparing real-time monitoring data with a chemical equilibrium model, obtaining the offset of a reaction rate, and judging the specific parameters of the liquid supplementing amount and the adjustment time; a proportional-integral control algorithm is combined with a trigger condition and a liquid supplementing parameter, the liquid medicine concentration is dynamically adjusted, a compensation factor is introduced for temperature fluctuation, and an adjusted concentration control instruction is obtained; liquid level distribution data in the cleaning tank are synchronously collected through a liquid level detection device, and whether the uniformity of the liquid medicine in the tank reaches a preset standard or not is judged in combination with the adjusted concentration control instruction; and continuously acquiring a stable distribution result, comparing the stable distribution result with an initial data set, judging the optimization degree of the control precision and the response speed, and obtaining a concentration fluctuation range and a uniformity index after dynamic adjustment.

The invention relates to the technical field of semiconductor manufacturing, in particular to a semiconductor defect detection method and system based on deep learning. The method comprises the following steps: step 1, multiband cooperative imaging and dynamic scanning control; 2, performing multi-scale feature fusion and defect identification; 3, dynamic threshold judgment and multi-scale feature fusion network optimization: dynamically adjusting a judgment threshold according to probability distribution characteristics of a current batch defect thermodynamic diagram, applying an offset to the threshold in combination with a wafer process type, and determining the offset according to a balance relationship between a false drop rate and an omission rate in historical data; critical samples and misjudgment samples with classification confidence close to a threshold value in historical detection are periodically screened, incremental learning is performed on the last layer of the multi-scale feature fusion network, and upstream network weight is frozen to prevent feature drift. Through fine image processing, multi-band information fusion, dynamic threshold adjustment, incremental learning and other mechanisms, the defect detection efficiency and accuracy in the semiconductor manufacturing process can be effectively improved, and the detection performance is continuously optimized.

The invention provides a regeneration wafer defect detection method and system based on point cloud, and belongs to the technical field of semiconductor manufacturing detection, and the method comprises the steps: carrying out the registration and fusion processing of the point cloud data of a target wafer, and obtaining the target point cloud data; performing plane fitting on the target point cloud data to determine a reference plane; performing feature extraction on the target point cloud data relative to the reference plane to obtain feature data; positioning a defect area based on the feature data, and calculating geometric parameters of the defect area; correcting the geometric parameters by using a preset error compensation model to obtain target geometric parameters; inputting the position of the defect area, the target geometric parameter and the feature data of the corresponding defect area into a defect classification model to obtain a defect type of the defect area; and generating a defect detection result of the target wafer based on the defect types, the positions, the target geometric parameters and the feature data of all the defect areas of the target wafer. According to the invention, the efficiency and reliability of regenerated wafer defect detection are improved.

The present invention relates to the field of semiconductor carrier technology, and in particular to a wafer box with a protective limiting device, which includes a bottom plate, a wafer storage box, a box cover, and a limiting assembly. The limiting assembly includes a limiting seat, a top assembly, a rotating plate, a limiting frame, and a rotating wheel. The limiting seat includes a connecting cross bar, a connecting arm, and a top blocking plate. The top assembly includes a connecting portion, a top protrusion, a connecting rod, a tensile sheet, and a reinforcing rib. Compared with the prior art, the present invention is provided with the wafer storage box for inserting wafers, and the limiting assembly is provided to top the wafers, thereby effectively preventing the wafers from being damaged. At the same time, by providing the top assembly, the top action has a protective limit, thereby preventing the rigid top from damaging the wafers. By providing the wafer storage box for loading 6-inch wafers, the cooperation of the fixing portion and the fixing assembly enables 6-inch wafers to be transported on an 8-inch wafer production line.

Dry development or dry removal of metal-containing extreme ultraviolet radiation (EUV) photoresist is performed in atmospheric conditions or performed in process tools without vacuum equipment. Dry removal of the metal-containing EUV photoresist may be performed under atmospheric pressure or over-atmospheric pressure. Dry removal of the metal-containing EUV photoresist may be performed with exposure to an air environment or with non-oxidizing gases. A process chamber or module may be modified or integrated to perform dry removal of the metal-containing EUV photoresist with baking, wafer cleaning, wafer treatment, or other photoresist processing function. In some embodiments, the process chamber for dry removal of the metal-containing EUV photoresist includes a heating assembly for localized heating of a semiconductor substrate and a movable discharge nozzle for localized gas delivery above the semiconductor substrate.

The invention discloses a semiconductor packaging test optimization method and system, and relates to the field of packaging testing, and the method comprises the steps: collecting and preprocessing a multi-dimensional abnormal signal, generating a standard data set, carrying out the feature extraction of data in the standard data set, obtaining a standard feature vector, and inputting the standard feature vector into a constructed abnormality detection model, the method comprises the steps of obtaining an abnormal signal report, distributing a test item for a chip through the abnormal signal report and a predefined mapping rule, generating a structure map and an electrical map, inputting the structure map and the electrical map into a multi-mode Transform model, outputting a fusion map, calculating a test weight according to the fusion map, and generating a test weight map and a region priority list. According to the invention, the testing efficiency, the micro defect detection precision and the boundary failure prediction of advanced packaging are improved.

The invention discloses a solar cell and a manufacturing method thereof, and a photovoltaic module, and relates to the field of photovoltaic technology. The solar cell includes: a semiconductor substrate having a first surface including a first region and a second region; the second area comprises an edge area and a middle area, each of the edge area and the middle area comprises a step structure recessed towards the second surface, and the step depth of the step structure of the edge area of the second area is larger than that of the step structure of the middle area of the second area; and the first doping layer is arranged on the first region, and the height of the bottom wall of the step structure in the middle region of the second region is lower than that of the first doping layer. The first passivation layer is arranged on the side, away from the semiconductor substrate, of the first doping layer and arranged on the second area. According to the embodiment of the invention, the thickness along the splitting direction is reduced, so that the splitting difficulty is reduced, meanwhile, the recombination of current carriers is reduced, and the passivation effect is improved.

The invention discloses a multi-AGV cooperative path planning and scheduling method for chip intelligent storage, and belongs to the field of high-precision electronic component intelligent storage. The method comprises the following steps: running according to a highway guide strategy, and pre-allocating tasks of each robot by using an MTSP problem according to different task types before path planning; an improved A * algorithm is provided, a global thermodynamic diagram congestion prediction and turning waiting heuristic method is introduced to establish a space-time joint search model, and a transportation path is optimized by greatly reducing the number of nodes needing to be searched and the turning and waiting times of the AGV, so that the efficiency is improved; in addition, a series of priority rules are also provided, and appearing conflicts are eliminated. Experiments verify the effectiveness of the method, high-reliability and low-vibration dust-free workshop AGV collaborative scheduling can be realized, and an efficient and safe warehousing automation solution is provided for semiconductor manufacturing.

The invention provides a third-generation semiconductor device multi-physical field coupling effect dynamic monitoring method and system, and relates to the technical field of semiconductors, and the method comprises the steps: collecting the data of a temperature field, an electric field, a magnetic field and a stress field through a complementary sensor array, constructing a feature tensor, inputting the feature tensor into a pre-trained graph neural network, and extracting a coupling effect dynamic evolution rule; on-line analysis and prediction are carried out by using an adaptive time window and a recurrent neural network, a multi-field coupling correlation degree evaluation model is established, an early warning level is determined according to the deviation between the coupling correlation degree and an early warning threshold value, and device risk evaluation and maintenance suggestions are generated, so that early warning of the failure risk of the semiconductor device is realized.

The invention provides a wafer edge defect detection method and system based on image recognition and a storage medium, and belongs to the technical field of semiconductor manufacturing, and the method comprises the steps: processing annular image data, and obtaining target image data; inputting the target image data into the edge defect prediction model to obtain a defect probability distribution diagram; based on the defect probability distribution diagram, identifying a pixel region with a probability value greater than or equal to a preset threshold value as a candidate defect region; performing feature extraction on the candidate defect region to obtain a target feature vector; inputting the target feature vector into a defect classification model, and determining the defect type and classification confidence of the candidate defect region; based on the defect type and / or the classification confidence, screening out a target defect area from the candidate defect areas; obtaining three-dimensional point cloud data of the target defect area, and calculating three-dimensional geometric parameters of the target defect area based on the three-dimensional point cloud data; and determining a detection result of the target wafer based on the defect type and the three-dimensional geometric parameters.

Various embodiments herein relate to methods, apparatus, and systems for baking metal-containing on a semiconductor substrate in the presence of a reactive gas species. For example, the method may include receiving the substrate in a process chamber, the substrate having a photoresist layer thereon, where the photoresist layer includes a metal-containing photoresist material; flowing a reactive gas species from a gas source, through a gas delivery line, into the process chamber, and exposing the substrate to the reactive gas species in the process chamber; and baking the photoresist layer while the substrate is exposed to the reactive gas species.

A three dimensional (3D) integrated circuit (IC) chip can include a multi-layer structure comprising a group of vertically stacked semiconductor layers. The multi-layer structure can include a group of processor cores distributed across the semiconductor layers, and a group of Through Silicon Vias (TSVs) arranged within the layers to facilitate electrical connections between the layers. The 3D IC chip can be optimized for thermal management based on a predictive model, enabling effective temperature control when utilized with a thermal management system that monitors and adjusts a cooling strategy of the 3D IC chip.

The invention provides a solar cell and a preparation method thereof, and a photovoltaic module, the rear surface of a semiconductor substrate is provided with a first region and a second region which are adjacent to each other, and the first region is provided with a first sub-region and first overlapping regions located at the two sides of the first sub-region; the first overlapping area is provided with a tunneling layer, a first doped conductive layer, a passivation layer, a second doped conductive layer and a first transparent conductive layer, the length of the first overlapping area in the first direction is D1, and the first direction is parallel to the surface where the semiconductor substrate is located; the rear surface of the semiconductor substrate is also provided with a third region and a fourth region which are adjacently arranged, and the third region is provided with a third sub-region and third overlapping regions located at the two sides of the third sub-region; the third overlapping region is provided with a tunneling layer, a first doped conductive layer, a passivation layer, a second doped conductive layer and a first transparent conductive layer, the length of the third overlapping region in the first direction is D2, and D1 is different from D2.

The invention discloses a multi-mode end point detection system and method for a semiconductor dry process, and relates to the field of gas concentration detection. A gas absorption cell; the reference light path adjusting unit comprises an adjustable attenuator used for adjusting signals; the first photoelectric detector is used for detecting a transmission signal; the second photoelectric detector is used for detecting a reference signal; the lateral scattered light detector is used for detecting a scattered signal of the particulate matters in the gas absorption tank; and the signal processing unit is in signal connection with the first photoelectric detector, the second photoelectric detector and the lateral scattering light detector and is used for performing compensation calculation on the transmission signal based on the reference signal and the scattering signal so as to obtain a corrected gas absorption signal. By adopting the scheme, measurement signal distortion caused by optical mirror surface pollution and particulate matter scattering interference in a semiconductor tail gas optical detection technology is avoided.