558 results about "Dry etching" patented technology

The invention relates to the technical field of semiconductor manufacturing, provides a wafer dry etching control method and system, aims to monitor an etching process in real time and dynamically control the etching process with high precision, and comprises the following steps: step 1, monitoring etching equipment, and collecting an etching parameter combination of etching and image information of a wafer etching area; 2, constructing a real-time data processing model, developing a multi-objective optimization function, and inputting a target value into the multi-objective optimization function to obtain an initial etching parameter combination; 3, in the etching process, a predicted value of etching result data is obtained through the real-time data processing model, the predicted value is compared with a target value, and an etching parameter combination of etching is dynamically adjusted; and 4, constructing an end point prediction model, monitoring whether the image features of the etched image information reach a preset threshold value or not in real time by the end point prediction model, and if yes, sending an etching end point signal. In addition, the invention provides a semiconductor wafer high-precision dry etching control system.

The invention discloses a chip-embedded TGV glass substrate and a manufacturing method thereof. The method comprises the following steps: providing a glass core plate; forming a temporary metal mask layer on the first surface of the glass core plate; performing pattern transfer and etching on the temporary metal mask layer; performing dry etching on the glass core plate in the second pattern area to form a first TGV hole; etching the glass core plate in the first pattern area and the second pattern area through a dry method to form a second TGV hole and deepen the depth of the first TGV hole; removing the temporary metal mask layer, performing metallization to form a first conductive through hole and a second conductive through hole, and manufacturing a first rewiring layer; grinding the second surface of the glass core plate until the first conductive through hole is exposed; etching the glass core plate through a dry method to form a cavity until the second conductive through hole is exposed; providing a chip, and embedding the chip into the cavity; therefore, no-damage cavity processing is realized, and the problems of surface damage, dimensional deviation, lateral erosion, microcracks or surface roughening and the like of the substrate are effectively avoided.

The invention relates to a manufacturing method of a thin-film resistor and a thin-film resistor structure. The method comprises the following steps: forming a first metal layer on a first main surface of a wafer; forming a masking layer in contact with the first metal layer; a resistance material layer is formed on the first main face and patterned, the patterned resistance material layer comprises a thin-film resistor, and the thin-film resistor is in ohmic contact with the first metal connecting line in the first metal layer through the masking layer. According to the method, the first metal layer serving as the metal connecting line of the thin-film resistor is firstly formed, and then the masking layer and the thin-film resistor are formed, so that the etching of the first metal layer and the etching of the masking layer can adopt dry etching, the damage of the dry etching to the thin-film resistor does not need to be considered, and the process difficulty can be reduced.

A method for manufacturing a display device that can easily achieve higher resolution is provided. A display device having both high display quality and high resolution is provided. A first EL film is deposited over a first pixel electrode, a first sacrificial film is formed to cover the first EL film and a first electrode, and the first sacrificial film and the first EL film are etched, so that a first EL layer is formed over the first pixel electrode. Then, the first sacrificial film is removed to expose the first electrode. Furthermore, a common electrode is formed over the first EL layer and the first electrode. The first EL film is etched by dry etching, and the first sacrificial film is removed by wet etching.

Provided is a method that allows for the etching of a silicon nitride film with respect to a silicon oxide film with high selectivity and high precision while preventing a degradation in the shape of the silicon oxide film portion during etching. The etching method of dry etching a film structure which is formed in advance on a wafer disposed in a processing chamber and in which an end portion of a film stack including a silicon nitride film and silicon oxide films vertically sandwiching the silicon nitride film forms a sidewall of a trench or hole, by supplying a gas for processing into the processing chamber, without using plasma includes: forming, as a first process, a reaction layer on the silicon nitride film by reaction of hydrogen fluoride gas at 30° C. or higher and 55° C. or lower; removing, thereafter, as a second process, the reaction layer having been formed in the first process, through volatilization by performing heating at 70° C. or higher and 110° C. or lower without causing the hydrogen fluoride gas to flow; and etching the silicon nitride film from the end portion in a lateral direction by performing the first and second processes a plurality of times.

The invention provides an etching method of a double-color second-class superlattice infrared detector, and belongs to the technical field of chip manufacturing. The method comprises the following steps: providing a double-color second-class superlattice infrared detector, and forming a photoresist mask on the surface of the double-color second-class superlattice infrared detector; under the condition that the ratio of the longitudinal etching rate to the transverse etching rate is not less than 5: 1, performing dry etching on the surface of the double-color second-class superlattice infrared detector to obtain an initial mesa structure; the initial mesa structure is subjected to wet etching, a middle mesa structure is obtained, the wet etching time is smaller than or equal to 2 min, and the wet etching temperature is smaller than or equal to 10 DEG C; and post-processing the middle table-board structure to obtain the table-board structure. Through organic combination of a high-anisotropy forming effect of dry etching and a low-damage repairing effect of wet etching, the low surface damage characteristic is considered while high aspect ratio etching is realized, the dark current of the device is fundamentally reduced, and the intrinsic detection performance of the device is improved.

The invention discloses a grid system for a plasma etching system and the plasma etching system, and belongs to the field of integrated circuit manufacturing, the grid system comprises a grid mesh close to a discharge outlet side of a discharge chamber,..., an Nth middle grid mesh and a grid mesh close to a dry etching part side which are arranged in sequence, and each grid mesh comprises a substrate, a plurality of grid mesh holes are uniformly distributed in the substrate, a first film layer with low surface energy and low sputtering yield is arranged on the outer surface of the substrate, and a second film layer with low surface energy and low sputtering yield is arranged on the inner wall of each grid mesh hole; n is an integer greater than or equal to 0. The invention can delay the loss of the grid mesh and delay the adsorption pollution on the surface of the grid mesh.

The invention provides a vertical deep ultraviolet LED epitaxial structure and a preparation method thereof. The vertical deep ultraviolet LED epitaxial structure comprises a substrate, an intrinsic layer, a sacrificial layer, a first electron injection layer, an etching barrier layer, a second electron injection layer, a quantum well active layer, an electron barrier layer and a hole injection layer which are sequentially stacked from bottom to top. Wherein the etching barrier layer is made of an n-type doped AlGaN material or an n-type doped AlN material; the mass percentage content of an Al component of the etching barrier layer is 70%-100%; according to the invention, the etching barrier layer with a high Al component is inserted into the electron injection structure, and the high Al-N bond energy and strong chemical stability of the etching barrier layer are utilized, so that the subsequent epitaxial layer can be effectively prevented from being excessively corroded in the dry etching process of the sacrificial layer, and the interface damage is reduced; meanwhile, the etching barrier layer with the high Al component and the electron injection layer form a remarkable barrier difference, the high barrier can guide electrons to be transversely and uniformly diffused in the electron injection layer, and the current density uniformity of the quantum well active layer is improved.

A method is disclosed of fabricating a MEMS device that includes one or more wafers configured as pump or valve. The pump or valve includes an inlet port to receive fluid and an outlet port to release the fluid within the pump or valve. The method comprises growing silicon dioxide on a silicon layer of the one or more wafers to form a silicon dioxide layer on the silicon layer, depositing silicon nitride on the silicon dioxide layer of the one or more wafers to form a silicon nitride layer on the silicon dioxide layer, spinning a front side to create a pattern thereon defining an area for the pump or valve, dry etching the one or more wafers at the area for the pump or valve to remove the silicon dioxide and silicon nitride layers to define an opening for the pump or valve.

The present application relates to the technical field of microelectrode preparation, and particularly relates to a transparent microelectrode array chip preparation method, comprising the following steps: S1. pretreating a glass substrate to improve the substrate surface cleanliness and adsorbability of the electrode film; S2. evaporating an ITO film on the surface of the pretreated glass substrate by using a magnetron sputtering process, as a transparent electrode; S3. spin-coating a photoresist on the surface of the ITO film and performing a patterning treatment, and then etching the ITO film to form a preset electrode structure by using a dry etching process, and then removing the photoresist and cleaning and drying; S4. coating an insulating layer on the surface of the substrate by using a PECVD process, patterning the insulating layer and etching by using a dry etching process to realize windowing, and then removing the photoresist and cleaning and drying; and realizing photoelectric synchronous detection. Avoiding metal residue interference: photoresist masks are used throughout the etching process to replace traditional metal hard masks.

The utility model relates to a kind of double sealing door mechanism of dry etching platform for radio frequency component in the field of radio frequency component manufacturing, including the processing box with processing cavity and the sealing door plate for closing processing cavity by being connected on processing box with hinge, still include: the sealing component for increasing the sealability between processing cavity is configured on the sealing door plate, temporary plugging is also carried out on the sealing component failure in the sealing door plate and is equipped with plugging component, leakage detection unit is arranged between the sealing component and plugging component;The application is designed by using main sealing, emergency sealing, leakage monitoring triple guarantee, effectively solve the problem that traditional single sealing door is easily caused by sealing element failure to lead to processing cavity air leakage, improve the sealing reliability of etching platform, avoid the influence of etching precision of radio frequency component due to air leakage, and the early warning function of leakage detection unit is convenient for staff to maintain in time, reduce equipment downtime loss.

The utility model discloses a dry etching equipment cavity protection device and dry etching equipment. According to the cavity protection device, a cavity attaching part comprises a first through hole, a first surface and a second surface, wherein the first surface and the second surface are oppositely arranged, and the first through hole penetrates through the first surface and the second surface; the cavity opening attaching part is provided with a second through hole and located on the first surface of the cavity attaching part, the diameter of the inner wall of the cavity opening attaching part is the same as that of the inner wall of the cavity attaching part, and the wall thickness of the cavity opening attaching part is smaller than that of the cavity attaching part; the bottom attaching part is arranged on the second surface of the cavity attaching part and located in the first through hole, the side wall of the bottom attaching part is connected with the inner wall of the cavity attaching part, and the surface, away from the cavity opening attaching part, of the bottom attaching part is flush with the surface, close to the bottom attaching part, of the cavity attaching part; the cavity attaching part is provided with a first hole and a second hole. According to the utility model, the protection on the inner wall of the cavity is improved.

The invention relates to a preparation process of a deep ultraviolet micro LED (light-emitting diode) array with self-aligned electrodes. According to the process, a metal barrier layer is deposited, a mesa shape is formed through wet etching, a mesa is formed through etching, a passivation layer is filled to protect the side wall, the CMP technology is combined, the surface is polished to be flat, ICP etching is carried out, the metal barrier layer is exposed, the metal barrier layer is washed away, the mesa can be exposed, and then a long electrode does not need to be aligned with the process in a high-precision mode. Complex procedures are not needed, the alignment difficulty is overcome and the chip yield is improved by combining the planarization of the filling thick passivation layer and the ICP dry etching technology, and industrialization of micro-LED array preparation is facilitated.

The invention relates to a resist underlayer film forming composition, a pattern forming method, and a resist underlayer film forming method. The purpose of the present invention is to provide: a composition for forming a resist underlayer film, which functions as an anti-reflective film and has excellent alkaline hydrogen peroxide water resistance, good landfill / planarization characteristics, and dry etching characteristics; a pattern forming method using the composition; and a method for forming a resist underlayer film. A composition for forming a resist underlayer film, which is characterized by containing (A) a polymer compound having a structural unit (a1) represented by formula (A-1) and at least one structural unit (a2) selected from structural units represented by formulae (A-2) to (A-4), (B) a crosslinking agent represented by formula (B-1), and (C) an organic solvent.

The reflective mask blank (100) according to the present invention is a reflective mask blank (100) for use as a material for a reflective mask (110) used in EUV lithography using extreme ultraviolet (EUV) light as exposure light. This reflective mask blank (100) is provided with: a substrate (1); a multilayer reflective film (2) that is formed on one main surface of the substrate (1) and reflects exposure light; a protective film (3) that is formed on the multilayer reflective film (2) and protects the multilayer reflective film (2); an absorption film (6) that is formed above the protective film (3) and that absorbs exposure light; and intermediate films (4, 5) provided between the protective film (3) and the absorbent film (6). The intermediate films (4, 5) include: a first intermediate film (4) containing niobium (Nb); and a second intermediate film (5) that is positioned closer to the absorbing film (6) than the first intermediate film (4) and is made of a material that can be dry-etched by an oxygen-containing gas. The absorber film (6) is formed of a material that can be dry-etched by a fluorine-containing gas.

This invention provides a high-selectivity dry etching method for surface convergence before p-GaN regrowth, comprising: etching the surface of the p-GaN layer or GaN layer of a GaN / AlGaN heterojunction in a Cl-based gas atmosphere to remove the native oxide layer and contaminants; introducing a mixture of BCl3 and fluorine-containing gas into a reaction chamber under inductively coupled plasma conditions, and maintaining the self-bias voltage within a first preset range for etching to selectively remove the p-GaN layer or GaN layer and achieve near-stop etching in the AlGaN layer, wherein the fluorine-containing gas is used to form an aluminum fluoride layer on the surface of the AlGaN layer to inhibit etching; and reducing the self-bias voltage from the first preset range to a second preset range and / or reducing the proportion of fluorine-containing gas in the mixed gas under plasma conditions to perform convergence treatment on the surface of the near-stop etched structure. This improves the repeatability of the process window and the adaptability of the regeneration length.

The invention discloses a method for composite etching of an electroplating gold plating layer, which comprises the following steps of: manufacturing a photoetching pattern on the front surface of gallium arsenide epitaxy, then evaporating a metal contact layer, depositing a SiNx protective mask layer, performing Mesa mesa etching on the gallium arsenide epitaxy, exposing a high-aluminum layer on the side surface of an epitaxial material, and forming an aluminum oxide limiting layer by adopting a wet oxidation process; a second SiNx protective mask layer continues to be deposited, and the metal contact layer is exposed through dry etching; forming a seed gold layer by adopting magnetron sputtering TiW / Au metal, and forming a photoresist mask with a target electrode pattern on the seed gold layer; electroplating thick gold on the photoresist mask pattern; the photoresist mask layer is removed after completion; the method of combining dry etching and wet etching is adopted to remove the gold plating layer in the non-electroplating area, so that the lateral corrosion of the metal layer is obviously reduced, the high-precision and high-fidelity electrode pattern transfer is realized, the lateral corrosion of the metal layer is reduced, and the passivation protection effect of the device is improved.

The invention relates to a preparation method of an epitaxial structure with micron holes and the epitaxial structure, and belongs to the technical field of epitaxial wafer manufacturing. Comprising the following steps: sequentially growing an AlN buffer layer, a Si-doped 3D AlN layer containing a nano-scale air gap, a high-temperature AlN layer, an n-type AlGaN layer, a multi-quantum well active layer, an electron barrier layer, a p-type AlGaN layer and a p-type GaN contact layer on the surface of a substrate; etching a region corresponding to the n electrode in the epitaxial structure until the air gap is exposed; growing a SiO2 protective layer; enlarging a nano-scale air gap to a micron-scale air gap through electrochemical etching; and preparing a p electrode metal layer on the p-type GaN contact layer, and preparing an n electrode metal layer on the micron-level air gap of the Si-doped 3D AlN layer to obtain an epitaxial structure with micron holes. According to the invention, the nanoscale fusiform air gap is expanded to the micron scale by using the dry etching process and the electrochemical etching process, so that the light extraction efficiency is improved.

This invention relates to the field of CMOS integrated circuit manufacturing processes and discloses a method for fabricating a PIP capacitor. First, the WSi of the lower electrode of the PIP capacitor is reduced by implantation. x Thin film stress is reduced, and then parasitic SiO2 on the surface of the lower electrode of the PIP capacitor is reduced by dry etching. WSi on the lower electrode is reduced by implantation. x Thin-film stress can improve the reliability of PIP capacitors; the principle for selecting the injection energy is to maximize the depth (R0) of the injection Gaussian distribution. p +3ΔR p ) to reach the entire WSi x 80% of the film thickness; WSi after implantation x The stress in the thin film was reduced by an order of magnitude by selecting phosphorus to eliminate WSi. x Thin film stress is a concern because phosphorus is frequently used for N-type polycrystalline doping. Simultaneously, phosphorus implantation also increases the polycrystalline doping concentration and reduces polycrystalline depletion.

A dry etching method for indium-containing III-V compound semiconductor materials, relating to the field of semiconductor laser processing technology, solves the problem of volatile InCl during etching of indium-containing compound semiconductor laser materials in existing technologies. x Deposition leads to decreased etching rates, cavity contamination, and high-temperature assisted etching causes mask loss, morphology degradation, and process instability. This invention addresses these issues by setting a cycle program that alternates between etching and rinsing pulses. During the etching stage, H2 is introduced to suppress the formation of non-volatile InCl3 products and simultaneously convert InCl3 products into InCl2, effectively inhibiting byproduct formation and improving etching efficiency. During the physical rinsing stage, Ar is used to effectively remove non-volatile InCl3 adhering to the surface of the etched material. x The product exposes the semiconductor substrate, promoting chemical pulses to carry out chemical reactions to etch the substrate, effectively preventing cavity contamination and a decrease in etching uniformity, and significantly improving the controllability and repeatability of the etching morphology.

The invention relates to a manufacturing method of a slope table-board in a semiconductor structure and a semiconductor device. The manufacturing method comprises the following steps: forming a first target film layer; according to the top surface design shape and the top surface design size of the slope mesa, photoetching and first dry etching are carried out on the first target film layer, and the remaining first target film layer after the first dry etching is a first target structure; the top surface shape and the top surface size of the first target structure are the same as the top surface design shape and the top surface design size; a second target film layer with the target thickness is formed on the first target structure, the target thickness is determined according to the slope design angle of the slope table top, and the second target film layer and the first target film layer are made of the same material; and second dry etching is carried out on the second target film layer to form a slope table surface, and a slope part of the slope table surface comprises the second target film layer left after the second dry etching. According to the invention, the angle of the formed slope can be accurately controlled.

The invention discloses a semiconductor device and a manufacturing method thereof. The manufacturing method comprises the following steps: providing a substrate; forming a hard mask layer on the substrate, wherein the hard mask layer is provided with an etching window for exposing part of the substrate; the hard mask layer serves as a mask, the substrate exposed out of the etching window is etched, a shallow groove is formed in the substrate, and the vertex angle of the shallow groove is a sharp angle; back-etching the hard mask layer from the side wall, close to one side of the shallow trench, of the hard mask layer; a first oxide layer is deposited through HDP-CVD, the bottom and the side wall of the shallow trench and the hard mask layer are covered with the first oxide layer, and the thickness of the first oxide layer in the area corresponding to the sharp corner is smaller than that of the other area of the first oxide layer; and performing dry etching to remove the first oxide layer and part of the substrate, so that the sharp corner is converted into a round corner. The smooth radian, the rounded shape and the like of the sharp corner are easier to control, the rounding effect of the sharp corner is excellent, and RNWE can be effectively inhibited; meanwhile, electric leakage of a cellular area is greatly reduced, and the working voltage stability and long-term reliability of the semiconductor device are improved.

This invention discloses an adsorption lifting device for a dry etching machine. The lower chamber is equipped with a silicon wafer support device and a silicon wafer positioning device. The silicon wafer support device includes a support rod, and the silicon wafer positioning device includes a positioning rod. The support rod is driven by a first power device to reciprocate between a support station and a first standby station. The positioning rod is driven by a second power device to reciprocate between a positioning station and a second standby station. A placement platform has support holes and positioning holes. A cooling groove for cooling the silicon wafer is provided on the placement platform within the silicon wafer placement area. An air inlet for connecting cooling gas into the cooling groove is provided on the worktable. An adsorption device for adsorbing the silicon wafer on the placement platform is also provided on the worktable. This device can accurately place the silicon wafer in the silicon wafer placement area using the positioning rod and effectively fix the silicon wafer, preventing cooling gas leakage and ensuring accurate etching of the silicon wafer, thus guaranteeing production efficiency and quality.

Methods, systems, and devices for divider and contact formation for memory cells are described. In some examples, a protective mask (e.g., a photoresist layer) may be formed over existing circuit structures above a substrate. Contact structures may be exposed when the protective mask is removed. In some examples, the protective mask may be removed using a dry etching operation. In some examples, one or more additional etching operations may be performed to expose (and subsequently fabricate) additional circuit structures.

This invention provides an etching method using silicon-containing hydrofluorocarbon. [Solution] The plasma dry etching method is based on the general formula: C x H y F z Si n (I) An etching gas mixture containing a compound having (1≦x≦6, 1≦y≦9, 1≦z≦15, n=1 or 2) is used, wherein the compound contains one or more methyl groups, and at least one methyl group is bonded to a Si atom. This method includes HAR dry etching processes, selective dry etching processes, and cyclic selective dry etching processes.

The invention relates to a resist pattern forming method. The present invention addresses the problem of providing, in optical lithography using high-energy rays, a method for forming a resist pattern, the method comprising a step of developing a resist film after exposure by dry etching to form a positive or negative resist pattern, said resist composition having a non-chemically amplified resist composition having excellent use sensitivity and limit resolution. The solution of the invention is a method for forming a resist pattern, which comprises the following steps: (i) forming a resist film on a substrate or a substrate laminated with an underlayer film by using a resist composition containing a hypervalent iodine compound represented by the following formula (1), (2) or (3), a carboxyl group-containing compound and a solvent; the resist pattern is formed by (ii) exposing the resist film to a high-energy ray, (iii) subjecting the exposed resist film to a heat treatment, and (iv) developing the heat-treated resist film by dry etching.

The embodiment of the present disclosure provides a preparation method of a semiconductor structure, a semiconductor structure and a memory, and relates to the technical field of semiconductors. The method comprises the following steps: providing a substrate; forming an initial structure above the substrate, wherein the initial structure comprises an insulating layer, a silicon layer, a groove, a plurality of recesses and a first electrode; the first electrode covers the inner walls of the groove and the plurality of recesses; forming a protective layer on the surface of the first electrode; removing the protective layer on the inner wall of the groove and the first electrode on the inner wall of the groove; removing the protective layer on the inner wall of the recess and part of the insulating layer close to the groove, so as to expose the first electrode on the surface of the recess; and sequentially forming a dielectric layer covering the first electrode and a second electrode covering the dielectric layer on the exposed surface of the first electrode, thereby avoiding the problems of short circuit of the lower electrode and damage of the lower electrode caused by direct dry etching, ensuring the integrity of the lower electrode while completing the isolation of the lower electrode, and improving the performance of the capacitor.

The invention provides a nanoimprint master template, a master negative template, a preparation method of the master negative template and a nanoimprint alignment system. The preparation method of the master template comprises the following steps: spin-coating photoresist on a silicon wafer; the method comprises the following steps: placing a mask on a silicon wafer coated with photoresist, exposing and developing by utilizing a photoetching technology, showing a first main body pattern and a first alignment pattern area on the mask on the photoresist, then baking and hardening, and transferring the pattern on the photoresist to the silicon wafer by dry etching; removing the residual photoresist to form a female template; then preparing a female negative template based on the female template, and adjusting the position of the female negative template under an optical microscope, so that the Moire fringe grating and the annular grating are aligned between the female template and the female negative template; according to the invention, the blank in the technical field of nanoimprint alignment in China is realized, high-precision alignment imprint is realized by adopting the existing common photoetching equipment and combining with an optical structure to assist alignment, and the original photoetching overlay precision is multiple times higher than the original precision.

This invention provides a thin-film transistor (TFT), its fabrication method, and a display panel. The method for fabricating the TFT includes: sequentially forming a gate, a gate insulating layer, a semiconductor layer, a doped semiconductor layer, and a metal layer on one side of a substrate; forming a photoresist layer on the surface of the metal layer, the photoresist layer including a first photoresist layer; sequentially performing a first wet etching, photoresist ashing, dry etching, and a second wet etching through the first photoresist layer to obtain a source, a drain, an ohmic contact layer, and an active layer. At least one of the first and second wet etching processes uses a composite etching solution, which includes molten metal and fluoride ions. The composite etching solution can etch the metal layer, the doped semiconductor layer, and part of the semiconductor layer. This fabrication process can save process steps, reduce parasitic capacitance and light leakage current, thereby effectively improving reliability defects such as water ripples and crosstalk in display panels, and also facilitating the achievement of extremely narrow bezels.

The invention discloses a chip continuous extraction device for a dry etching machine, and belongs to the technical field of semiconductor manufacturing equipment. Comprising a magnetic levitation conveying mechanism and a cleaning module, the magnetic levitation conveying mechanism comprises a track base plate, a motor stator module and a magnetic levitation and air floatation supporting plate, the motor stator module is arranged in the track base plate, the magnetic levitation and air floatation supporting plate is located above the motor stator module, and a limiting ring is arranged on the edge of the magnetic levitation and air floatation supporting plate; a multi-cavity air path structure is arranged in the magnetic suspension air floatation supporting plate, a permanent magnet array is arranged at the bottom of the magnetic suspension air floatation supporting plate, air floatation micropores are formed in the upper surface of the magnetic suspension air floatation supporting plate, and the cleaning module comprises an air supply module and an air return module. According to the invention, continuous and uninterrupted assembly line type extraction and on-line processing of chips from an etching machine to downstream equipment are realized, and the production efficiency, the positioning precision and the cleanliness are remarkably improved.