1263 results about "Dry etching" patented technology

The invention discloses an actuator structure and a liquid spraying device comprising the same, the actuator structure comprises a vibrating membrane, a piezoelectric material, a lower electrode and an upper electrode, the top surface and the bottom surface of the piezoelectric material are respectively connected to the upper electrode and the lower electrode, the vibrating membrane is connected to the bottom surface of the lower electrode, and the upper electrode is connected to the bottom surface of the piezoelectric material. The piezoelectric material is a single crystal piezoelectric film material. The liquid spraying device comprises the actuator structure. According to the actuator structure and the liquid spraying device comprising the actuator structure, the piezoelectric material is processed and manufactured by using the single crystal piezoelectric film material, so that the single crystal piezoelectric film material can be processed by using a wet etching technology, the problems in a dry etching process are effectively avoided, the preparation precision of the actuator structure is ensured, and the manufacturing cost of the actuator structure is reduced. The stability of the actuator structure is improved, and the manufacturing cost of the actuator structure is reduced.

A semiconductor process provides a semiconductor substrate including a plurality of pads and a passivation layer. The passivation layer has a plurality of openings to expose the pads. Forming a ball bottom metal material layer on the connecting pad and the passivation layer; a bump is formed on the under-ball metal material layer by electroplating and overlaps the pad and a portion of the passivation layer in an orthographic projection direction. A patterned photoresist layer is formed on the bumps. The patterned photoresist layer completely covers the bump and extends towards the outer periphery of the bump to cover the ball bottom metal material layer. A first part of the ball bottom metal material layer is formed at the part covered by the patterned photoresist layer, and a second part of the ball bottom metal material layer is formed at the part not covered by the patterned photoresist layer. And removing a second part, which is not covered by the patterned photoresist layer and the bumps, of the under-ball metal material layer. And removing the patterned photoresist layer to expose the first part which is originally covered by the patterned photoresist layer. And removing the first part on the passivation layer by adopting dry etching to form a ball bottom metal layer. And the side wall of the ball bottom metal layer is flush with the side wall of the bump.

The invention discloses a polycrystalline silicon etching method, which comprises the following steps of: firstly, carrying out a polycrystalline silicon etching process for the first time, and carrying out a certain amount of transverse etching; an isotropic dry etching process is adopted, so that the polycrystalline silicon has transverse etching. And then a polycrystalline silicon etching process with a high selection ratio is carried out, and an anisotropic etching process is adopted to ensure that the polycrystalline silicon on the surface is etched cleanly. According to the etching process, a step-by-step etching process method is adopted, the isotropic etching process is firstly carried out to control the etching amount of transverse etching, then the anisotropic etching method and the high-selectivity etching method are adopted to carry out etching of different etching amounts on areas with inconsistent feature sizes, and accurate etching of polycrystalline silicon is guaranteed.

The invention relates to the technical field of semiconductor manufacturing, provides a wafer dry etching control method and system, aims to monitor an etching process in real time and dynamically control the etching process with high precision, and comprises the following steps: step 1, monitoring etching equipment, and collecting an etching parameter combination of etching and image information of a wafer etching area; 2, constructing a real-time data processing model, developing a multi-objective optimization function, and inputting a target value into the multi-objective optimization function to obtain an initial etching parameter combination; 3, in the etching process, a predicted value of etching result data is obtained through the real-time data processing model, the predicted value is compared with a target value, and an etching parameter combination of etching is dynamically adjusted; and 4, constructing an end point prediction model, monitoring whether the image features of the etched image information reach a preset threshold value or not in real time by the end point prediction model, and if yes, sending an etching end point signal. In addition, the invention provides a semiconductor wafer high-precision dry etching control system.

The invention provides a method for forming a strained silicon layer and a semiconductor structure, which comprises the steps of covering a semiconductor layer and a gate stack structure to form an etching stop layer, and the semiconductor layer comprises a first device region and a second device region which are separated from each other; forming an auxiliary side wall surrounding the side wall of the gate stack structure on the etching stop layer; forming a patterned hard mask layer; taking the patterned hard mask layer as an etching mask, and performing selective etching on the second device region through a wet etching process to form a sigma trench; and growing a strained silicon layer in the sigma groove. According to the invention, on the premise of not sacrificing the consistency of the critical dimensions of the sigma trench, the etching load effect caused by dry etching in the forming process of the sigma trench is avoided.

A dry etching method of the present disclosure includes bringing a β-diketone and a gas containing a halogen atom in its molecule into contact with an etching target film containing a metal, an oxide of the metal, or a nitride of the metal formed on a surface of a workpiece to etch the etching target film, the metal containing at least one selected from the group consisting of In, Ga, Cu, Co, Fe, Sn, Zn, Al, Ta, and As.

The invention relates to the technical field of semiconductor manufacturing, and discloses a plasma dry etching process monitoring method and device based on a metasurface, and the method comprises the steps: obtaining a first photoetching layout corresponding to all structures of a target device; determining a key structure area of the target device in the first photoetching layout, periodically repeating the key structure area to form a metasurface of the key structure, and obtaining a corresponding second photoetching layout according to the metasurface; wherein the key structure comprises all structures; splicing the second photoetching layout and the first photoetching layout in parallel to obtain an integral photoetching layout; carrying out a plasma dry etching process on the whole photoetching layout; obtaining a terahertz reflection spectrum generated by irradiating a corresponding area of a second photoetching layout in the whole photoetching layout through an electromagnetic beam; and according to the terahertz reflection spectrum, determining a process state of a plasma dry etching process in a key structure area in the first photoetching layout in the whole photoetching layout.

The invention relates to the technical field of wireless communication, and provides a preparation method of a surface acoustic wave filter and the surface acoustic wave filter.The preparation method comprises the steps that S1, a substrate of the surface acoustic wave filter is obtained; s2, growing a plurality of metal electrodes and a protective layer on the front surface of the substrate, wherein the protective layer completely covers the plurality of metal electrodes; s3, presetting a soaking column area on the substrate, and spin-coating a layer of photoresist on the back surface of the substrate; s4, removing the photoresist in the soaking column region through exposure and development; s5, etching the soaking column region through dry etching to form a groove, and removing the residual photoresist on the substrate; s6, depositing an electroplating seed layer on the back surface of the substrate, and continuing to complete the copper electroplating process, so that the groove is filled with copper; and S7, grinding the back surface of the substrate until the back surface of the substrate is exposed, and reserving the soaking column formed in the groove to obtain the surface acoustic wave filter. The surface acoustic wave filter provided by the invention can effectively improve the thermal damage resistance of the device under the working condition of high input power.

The invention provides a dual damascene process method, and relates to the technical field of semiconductors. The dual damascene process method comprises the following steps: sequentially forming a dielectric layer, a patterned first hard mask layer, a first planarization layer and a patterned second hard mask layer on a substrate; performing dry etching by using the second hard mask layer to form a through hole stopped on the surface of the substrate; removing the second hard mask layer and the first planarization layer; performing dry etching by using the first hard mask layer to form a groove; removing the first hard mask layer; and forming a metal layer to fill the through hole and the groove so as to obtain the dual damascene structure. According to the process method, the connectivity of the formed through hole can be ensured, and a low-resistance channel of a metal interconnection structure is subsequently formed in the bottom area of the through hole; meanwhile, the first hard mask layer is removed after the through hole is formed, accurate transmission of the key size of the through hole can be ensured, the accuracy of the key size of the subsequently formed metal interconnection structure is improved, and therefore the yield of a chip product and the performance of a device are improved.

The invention relates to the technical field of vacuum measurement, in particular to a multi-sealing-cavity MEMS capacitor thin film vacuum gauge, and is characterized in that a silicon substrate is arranged above substrate glass and is bonded with the substrate glass; a pressure sensing film is obtained in the middle of the silicon substrate in a photoetching and dry etching mode; a fixed metal electrode is obtained in the middle of the substrate glass in a photoetching and sputter coating mode; a capacitance gap is formed between the fixed metal electrode and the pressure sensing film; photoetching and corroding the silicon substrate, forming a working sealing cavity above the pressure sensing film, and respectively forming a first cavity and a second cavity above two sides of the pressure sensing film; getter blocks are arranged in the first chamber and the second chamber; and the sealing glass is arranged above the silicon substrate. On the premise that the size of the vacuum gauge is not obviously increased, the multiple chambers are arranged to form the sealing cavity, the air suction capacity is improved, high vacuum obtaining and long-term maintaining performance of the sealing cavity of the vacuum gauge are ensured, and the long-term stability of the vacuum gauge is greatly improved.

The invention discloses a Micro-LED chip array integrated with a homogeneous micro-lens array and a preparation method thereof, and the method comprises the steps: carrying out the wafer-level precise bonding of a Micro-LED light-emitting pixel array and a CMOS drive circuit substrate, removing a substrate, integrating a homogeneous pixel-level GaN micro-lens array on a GaN-based pixel array through the photoetching, hot melting backflow and dry etching technologies, and carrying out the precise bonding of the micro-LED light-emitting pixel array and the CMOS drive circuit substrate. And finally, realizing the full-pixel common cathode conduction of the Micro-LED chip by adopting a metal interconnection process. According to the method, the Micro-LED pixel array and the micro-lens array are homogeneously integrated, are made of the same material and have no refractive index difference, so that no Fresnel loss exists on an interface, and the light extraction efficiency of a chip is improved. In addition, the method is simple in manufacturing process, low in cost, good in chip structure reliability, high in stability and suitable for being applied to industrial chip manufacturing.

The invention provides a metal gate and a preparation method thereof, and the preparation method comprises the steps: depositing a first metal material, carrying out the dry etching of the first metal material in a second part of a groove, removing a protrusion, enlarging the size of an opening of the groove, and filling a second metal material to form the metal gate, thereby solving a gap defect in the metal gate, and improving the reliability of the metal gate. According to the invention, the stability of the metal gate can be improved, and the difference of pattern loading (pattern loading effect) can be reduced.

The invention provides a manufacturing method of a sigma trench and a semiconductor device thereof, and the manufacturing method of the sigma trench comprises the steps: providing a substrate, forming a gate structure on the substrate, and forming source and drain regions in the substrate at two sides of the gate structure; anisotropic dry etching is carried out, and a first groove is formed in the source drain region; performing an isotropic chemical reaction, raising the temperature after the reaction is finished to sublimate a reaction product, forming a second groove in the first groove, enabling the top of the side wall of the second groove to be located at the bottom of the gate structure, and forming an undercut at the bottom of the gate structure; and performing wet etching, and forming a sigma groove in the second groove. According to the Sigma trench formed by the three steps of anisotropic dry etching, isotropic chemical reaction and wet etching, the top of the side wall of the Sigma trench is located at the bottom of the gate structure, and the undercut is formed at the bottom of the gate structure, so that the linear distance between the source region and the drain region is shortened, the resistance is reduced, and the performance of the device is improved.

The invention discloses a Micro-LED (Light Emitting Diode) device self-alignment groove filling and passivating method, which comprises the following steps that a Micro-LED device is provided, and the Micro-LED device comprises array units and grooves between the array units; preparing a dielectric layer on the Micro-LED device, wherein the dielectric layer fills the groove and covers all the array units; curing the dielectric layer; and thinning the whole surface of the dielectric layer by using a mask-free dry etching back etching method until the upper surfaces of all the array units are exposed, and forming a patterned passivation layer at the groove. The whole surface of the dielectric layer is thinned by using a mask-free dry etching back etching method, mask preparation and photoetching are not needed, the height of the dielectric layer can be accurately regulated and controlled through an etching process, and the process is simple; meanwhile, due to the fact that the register step and the developing solution corrosion step are avoided, the technological method can eliminate the problems of interface gaps and table top residues caused by register errors, the graphical passivation layer which is tightly connected can be formed without being restrained by the shape and the size, the etching resistance of the passivation structure is improved, and the device manufacturing yield is improved.

The invention discloses a GaN HEMT (High Electron Mobility Transistor) device with high gate reliability and a preparation method thereof. The preparation method comprises the following steps: providing a basic structure; sequentially forming a p-type GaN layer, a gate material layer, a dielectric mask layer and a metal mask layer; patterning etching is carried out; carrying out wet etching on the metal mask structure, and meanwhile, generating a corrosion effect on the side surface of the grid precursor to form a grid; performing dry etching to form a p-type GaN structure; performing plasma treatment on the side surface; and respectively manufacturing and forming a source electrode and a drain electrode. Dry etching is replaced by wet etching to form a structure that the p-type GaN structure extends to the source and drain sides, grid self-alignment etching is achieved, the uniformity and controllability of an extension area are improved, the technological process is simplified, the repeatability of device structure preparation is guaranteed, meanwhile, plasma is used for treating and passivating the side wall, and the device structure is more stable in performance. Current leakage caused by a surface state and surface roughness is suppressed, off-state leakage of the device is greatly reduced, and reliability is improved.

Aspects of the present disclosure relate to a process flow for fabricating a waveguide structure having a silicon nitride core with atomic-scale smooth sidewalls achieved by wet etch (rather than traditional dry etch treatment). The mask is pre-biased to account for lateral etching during the wet etching step.

The invention provides semiconductor process equipment and an etching method. The equipment comprises a plasma excitation device and a process chamber, and the plasma excitation device comprises a first sub-cavity, a second sub-cavity, a first radio frequency assembly and a second radio frequency assembly, the first sub-cavity and the second sub-cavity are communicated with each other, and the first radio frequency assembly and the second radio frequency assembly are connected with the first sub-cavity and the second sub-cavity respectively. The first sub-cavity is communicated with a first gas source, and the first gas source can convey first process gas to the first sub-cavity; the first radio frequency assembly is used for exciting a first gas source into first plasma; the second sub-cavity is communicated with a second gas source, and the second gas source can convey second process gas to the second sub-cavity; the second radio frequency assembly is used for exciting the gas and / or the first plasma in the second sub-cavity, so that the gas and / or the first plasma react in the second sub-cavity, and a reaction product containing free radicals is generated. And the free radicals can chemically react with the material on the surface of the wafer, so that chemical dry etching on the wafer by using the free radicals is realized, and the damage to the surface of the wafer is reduced.

Provided is a method for etching a silicon nitride film with high accuracy and high selectivity with respect to a silicon oxide film, while preventing deterioration of the shape of a silicon oxide film portion during etching. A dry etching method according to the present invention is used for etching a film structure that is formed in advance on a wafer disposed in a processing chamber, and that is configured such that an end portion of a film layer obtained by laminating a silicon nitride film so as to be vertically sandwiched by silicon oxide films constitutes a side wall of a groove or a hole, in a state in which a gas for processing is supplied into the processing chamber and no plasma is used, wherein: the method comprises (a) a step for reacting a hydrogen fluoride gas at a prescribed temperature to form a reaction layer on the silicon nitride film, (b) a step for channeling a gas of a polar solvent to process the reaction layer formed in step (a), and (c) a step for performing heating at a temperature higher than that in step (a) in a state in which no hydrogen fluoride gas is channeled and volatilizing the reaction layer formed in step (a) and processed in step (b) to remove the reaction layer; and steps (a) to (c) are repeated a plurality of times.

To provide a pattern forming method capable of forming a fine pattern with a high aspect ratio without causing pattern collapse.SOLUTION: A pattern forming method comprises preparing a resist material containing a polymer having a silicon-containing acid-labile group, forming a resist film by using the resist material, exposing and baking the resist film, and then developing the resist film by dry etching to form a pattern.SELECTED DRAWING: None

The invention discloses an antireflection film, a preparation method thereof and an optical device, and relates to the technical field of optics, the method comprises the steps that a composite material film layer is deposited on a substrate, the composite material film layer comprises a first material and a second material, and the etching rate of the first material is different from that of the second material during wet etching or dry etching; performing wet etching or dry etching on the composite material film layer to obtain a porous film layer; and sequentially carrying out cleaning treatment and drying treatment on the porous membrane layer. According to the anti-reflection film, the preparation method thereof and the optical device, the anti-reflection film of a porous structure is prepared by combining a coating technology commonly used in the industry and laboratories with a wet or dry etching method, equipment hardware does not need to be transformed, and the anti-reflection film is efficient and low in cost.

The invention discloses a chip-embedded TGV glass substrate and a manufacturing method thereof. The method comprises the following steps: providing a glass core plate; forming a temporary metal mask layer on the first surface of the glass core plate; performing pattern transfer and etching on the temporary metal mask layer; performing dry etching on the glass core plate in the second pattern area to form a first TGV hole; etching the glass core plate in the first pattern area and the second pattern area through a dry method to form a second TGV hole and deepen the depth of the first TGV hole; removing the temporary metal mask layer, performing metallization to form a first conductive through hole and a second conductive through hole, and manufacturing a first rewiring layer; grinding the second surface of the glass core plate until the first conductive through hole is exposed; etching the glass core plate through a dry method to form a cavity until the second conductive through hole is exposed; providing a chip, and embedding the chip into the cavity; therefore, no-damage cavity processing is realized, and the problems of surface damage, dimensional deviation, lateral erosion, microcracks or surface roughening and the like of the substrate are effectively avoided.

The invention discloses an etching method of a passivation layer, and the method comprises the steps: forming the passivation layer on a metal layer, the metal layer being formed in an interlayer dielectric layer, the interlayer dielectric layer being formed on a substrate, and the substrate being used for forming a semiconductor device; covering the passivation layer with a light resistor, and removing the light resistor in the target region through exposure and development in sequence to expose the passivation layer in the target region; wet etching is carried out, so that the passivation layer of the target area is thinned; and performing dry etching until the metal layer of the target area is exposed. After the passivation layer on the metal layer is covered with the light resistor, the target area is exposed through exposure and development in sequence, the passivation layer of the target area is removed through wet etching and dry etching in sequence, the metal layer of the target area is exposed, and therefore the appearance of the edge of the junction area of the exposed metal layer and the passivation layer is steeper, and the light resistance of the metal layer is improved. And the residue of the passivation layer is reduced, so that the phenomena of skip plating and falling of the subsequent electroplating metal layer are avoided.

According to one embodiment, a method of manufacturing a capacitor includes providing a substrate to be processed; providing a first conductive material portion on a main surface of a semiconductor substrate located in an opening; processing the conductive layer in a pattern shape by dry etching; providing a first contact electrode, a second contact electrode, and a second conductive material portion; performing dry etching to the first conductive material portion to disconnect electrical connection between a connection portion and the semiconductor substrate; and performing wet etching to the second conductive material portion to disconnect electrical connection between the first contact electrode and the second contact electrode.

The invention discloses a wavelength-tunable dual-mode semiconductor laser chip and a preparation method thereof, and belongs to the technical field of semiconductors. The chip comprises a laser area, an electrical isolation area, an amplification feedback area and two-end film coating areas, a multi-layer growth structure of the chip comprises multiple functional layers, a mode expansion waveguide layer is of a special structure, an ohmic contact layer comprises specific electrode layout, and the two-end film coating areas adopt 1550nm AR films. The preparation method comprises the steps of forming each functional region, and forming the laser region by using holographic exposure and dry etching processes to form the grating layer. On the basis of an InP semiconductor process platform, the integrated level is high, and a middle phase region is omitted, so that dual-mode output is more stable; eBL is adopted to etch the phase shift Bragg grating and the double-end-face AR coating film, so that generation of pure microwave signals in a degenerate mode can be inhibited; dual-mode synchronous or asynchronous tuning can be realized by tuning the injection current ratio, and the dual-mode tuning circuit has the characteristics of low power consumption and high efficiency and is suitable for scenes with high energy efficiency requirements.

The present invention relates to a processing method for a gradient film layer and a processing method for a gradient-depth micro-nano structure. The processing method for the gradient film layer includes the following steps: fixing a planar film layer on the surface of a substrate; forming a sacrificial film layer with a gradually changing thickness on the surface of the planar film layer through gradient coating and / or exposure and development; based on the etching selectivity ratio, removing the sacrificial film layer and the planar film layer above the gradient surface in sequence through dry etching to obtain a substrate with a gradient film layer; the processing method for the gradient-depth micro-nano structure includes the following steps: forming a photoresist film on the surface of the gradient film layer and patterning the photoresist film in the gradient structure region; through etching and resist removal, removing the photoresist film and the gradient film layer in the gradient structure region in sequence, and after the etching is completed, through post-treatment, a gradient-depth micro-nano structure is obtained. The present invention has the effects of improving the processing flexibility, increasing the thickness control range of the gradient film layer, and obtaining a gradient-depth micro-nano structure with a continuous depth change.

A dry etching device and a control method thereof, the dry etching device comprising: an electrostatic chuck configured to bear a wafer; the ejector pins penetrate through the electrostatic chuck, are parallel to the plane of the chuck surface of the electrostatic chuck, and are not collinear; and the pressure sensor is configured to obtain the load bearing of the ejector pin. The position of the wafer on the ejector pin can be detected through the bearing of the ejector pin obtained by the pressure sensor, so that whether the position of the wafer borne on the ejector pin deviates or not is judged, a basis is provided for judging whether movement of the ejector pin is stopped or not, the problem of wafer sliding can be effectively reduced, the situation can be effectively prevented from being further expanded, and the service life of the wafer is prolonged. And the occurrence of sheet collision and sheet breaking accidents is reduced, the manufacturing yield can be effectively improved, and the waste sheet rate is reduced.

An MEMS wafer corrosion thickness monitoring and corrosion process evaluation method comprises the steps that a plurality of monitoring points are designed in a preset area of a silicon wafer pattern surface, the monitoring points are of structures with different shapes and different depths, structures with different heights are formed on photoresist through a multi-depth photoetching process, and the monitoring points are used for monitoring the corrosion thickness of the silicon wafer. The structure is integrally transferred to the surface of a silicon wafer through one-time dry etching, multiple depth monitoring points are formed, an anti-corrosion protection layer is deposited on the pattern face of the wafer, wet etching is carried out on the back face of the wafer, the light-transmitting state of the monitoring points is recognized through chemical corrosive liquid and an optical detection system, and the light-transmitting area proportion is quantified; according to the light transmission sequence and time, the corrosion depth and uniformity of each area of the wafer are calculated, the process result and the wafer quality are evaluated, the wet method corrosion depth can be accurately controlled, the corrosion uniformity in the wafer is greatly improved, and the manufacturing process of the monitoring structure is simplified.

The invention provides a composition, a resist underlayer film, a semiconductor device and a preparation method thereof. The composition comprises a silicon-containing resin, a solvent and an acid, the silicon-containing resin has a high branching degree, a new branching degree DB of the silicon-containing resin is defined according to the branching degree contributed by a Q structural unit and a T structural unit in the silicon-containing resin and in combination with a 29Si nuclear magnetic resonance spectrogram, and the branching degree DB of the silicon-containing resin is controlled to be within a proper range. The silicon-containing resin is added into the composition, so that a resist underlayer film formed by the composition has relatively high anti-reflection performance and relatively high dry etching rate at the same time.

The invention discloses a preparation method of anti-glare glass. The preparation method comprises the following steps: cleaning the surface of a glass substrate; coating a film layer on the surface of the glass substrate; coating photoresist on the film layer; carrying out exposure, development and film layer etching treatment; the longitudinal depth of the glass is directionally etched through dry etching, and longitudinal and transverse etching are simultaneously carried out through a wet etching mode, so that a certain depth-to-width ratio is obtained, and the anti-glare area is increased; or, the surface of the glass is subjected to preliminary morphology construction through a wet method, and then accurate depth control and feature shaping are achieved in a specific area through dry etching. The anti-glare performance can be effectively improved and is close to the disordered diffusion effect of frosting; the surface texture distribution is more uniform, and the defects that in a traditional frosting process, flash points are not uniform, and the surface microstructure is difficult to accurately control are overcome; according to the invention, a microstructure is directly formed on the glass substrate by adopting an etching process, so that the reliability requirements in various harsh use environments can be met.

The invention relates to a manufacturing method of a thin-film resistor and a thin-film resistor structure. The method comprises the following steps: forming a first metal layer on a first main surface of a wafer; forming a masking layer in contact with the first metal layer; a resistance material layer is formed on the first main face and patterned, the patterned resistance material layer comprises a thin-film resistor, and the thin-film resistor is in ohmic contact with the first metal connecting line in the first metal layer through the masking layer. According to the method, the first metal layer serving as the metal connecting line of the thin-film resistor is firstly formed, and then the masking layer and the thin-film resistor are formed, so that the etching of the first metal layer and the etching of the masking layer can adopt dry etching, the damage of the dry etching to the thin-film resistor does not need to be considered, and the process difficulty can be reduced.