829 results about "Dry etching" patented technology

The invention relates to the technical field of semiconductor manufacturing, provides a wafer dry etching control method and system, aims to monitor an etching process in real time and dynamically control the etching process with high precision, and comprises the following steps: step 1, monitoring etching equipment, and collecting an etching parameter combination of etching and image information of a wafer etching area; 2, constructing a real-time data processing model, developing a multi-objective optimization function, and inputting a target value into the multi-objective optimization function to obtain an initial etching parameter combination; 3, in the etching process, a predicted value of etching result data is obtained through the real-time data processing model, the predicted value is compared with a target value, and an etching parameter combination of etching is dynamically adjusted; and 4, constructing an end point prediction model, monitoring whether the image features of the etched image information reach a preset threshold value or not in real time by the end point prediction model, and if yes, sending an etching end point signal. In addition, the invention provides a semiconductor wafer high-precision dry etching control system.

The invention discloses a Micro-LED chip array integrated with a homogeneous micro-lens array and a preparation method thereof, and the method comprises the steps: carrying out the wafer-level precise bonding of a Micro-LED light-emitting pixel array and a CMOS drive circuit substrate, removing a substrate, integrating a homogeneous pixel-level GaN micro-lens array on a GaN-based pixel array through the photoetching, hot melting backflow and dry etching technologies, and carrying out the precise bonding of the micro-LED light-emitting pixel array and the CMOS drive circuit substrate. And finally, realizing the full-pixel common cathode conduction of the Micro-LED chip by adopting a metal interconnection process. According to the method, the Micro-LED pixel array and the micro-lens array are homogeneously integrated, are made of the same material and have no refractive index difference, so that no Fresnel loss exists on an interface, and the light extraction efficiency of a chip is improved. In addition, the method is simple in manufacturing process, low in cost, good in chip structure reliability, high in stability and suitable for being applied to industrial chip manufacturing.

The invention provides a metal gate and a preparation method thereof, and the preparation method comprises the steps: depositing a first metal material, carrying out the dry etching of the first metal material in a second part of a groove, removing a protrusion, enlarging the size of an opening of the groove, and filling a second metal material to form the metal gate, thereby solving a gap defect in the metal gate, and improving the reliability of the metal gate. According to the invention, the stability of the metal gate can be improved, and the difference of pattern loading (pattern loading effect) can be reduced.

To provide a pattern forming method capable of forming a fine pattern with a high aspect ratio without causing pattern collapse.SOLUTION: A pattern forming method comprises preparing a resist material containing a polymer having a silicon-containing acid-labile group, forming a resist film by using the resist material, exposing and baking the resist film, and then developing the resist film by dry etching to form a pattern.SELECTED DRAWING: None

The invention discloses a chip-embedded TGV glass substrate and a manufacturing method thereof. The method comprises the following steps: providing a glass core plate; forming a temporary metal mask layer on the first surface of the glass core plate; performing pattern transfer and etching on the temporary metal mask layer; performing dry etching on the glass core plate in the second pattern area to form a first TGV hole; etching the glass core plate in the first pattern area and the second pattern area through a dry method to form a second TGV hole and deepen the depth of the first TGV hole; removing the temporary metal mask layer, performing metallization to form a first conductive through hole and a second conductive through hole, and manufacturing a first rewiring layer; grinding the second surface of the glass core plate until the first conductive through hole is exposed; etching the glass core plate through a dry method to form a cavity until the second conductive through hole is exposed; providing a chip, and embedding the chip into the cavity; therefore, no-damage cavity processing is realized, and the problems of surface damage, dimensional deviation, lateral erosion, microcracks or surface roughening and the like of the substrate are effectively avoided.

According to one embodiment, a method of manufacturing a capacitor includes providing a substrate to be processed; providing a first conductive material portion on a main surface of a semiconductor substrate located in an opening; processing the conductive layer in a pattern shape by dry etching; providing a first contact electrode, a second contact electrode, and a second conductive material portion; performing dry etching to the first conductive material portion to disconnect electrical connection between a connection portion and the semiconductor substrate; and performing wet etching to the second conductive material portion to disconnect electrical connection between the first contact electrode and the second contact electrode.

An MEMS wafer corrosion thickness monitoring and corrosion process evaluation method comprises the steps that a plurality of monitoring points are designed in a preset area of a silicon wafer pattern surface, the monitoring points are of structures with different shapes and different depths, structures with different heights are formed on photoresist through a multi-depth photoetching process, and the monitoring points are used for monitoring the corrosion thickness of the silicon wafer. The structure is integrally transferred to the surface of a silicon wafer through one-time dry etching, multiple depth monitoring points are formed, an anti-corrosion protection layer is deposited on the pattern face of the wafer, wet etching is carried out on the back face of the wafer, the light-transmitting state of the monitoring points is recognized through chemical corrosive liquid and an optical detection system, and the light-transmitting area proportion is quantified; according to the light transmission sequence and time, the corrosion depth and uniformity of each area of the wafer are calculated, the process result and the wafer quality are evaluated, the wet method corrosion depth can be accurately controlled, the corrosion uniformity in the wafer is greatly improved, and the manufacturing process of the monitoring structure is simplified.

The invention provides a composition, a resist underlayer film, a semiconductor device and a preparation method thereof. The composition comprises a silicon-containing resin, a solvent and an acid, the silicon-containing resin has a high branching degree, a new branching degree DB of the silicon-containing resin is defined according to the branching degree contributed by a Q structural unit and a T structural unit in the silicon-containing resin and in combination with a 29Si nuclear magnetic resonance spectrogram, and the branching degree DB of the silicon-containing resin is controlled to be within a proper range. The silicon-containing resin is added into the composition, so that a resist underlayer film formed by the composition has relatively high anti-reflection performance and relatively high dry etching rate at the same time.

The invention relates to a manufacturing method of a thin-film resistor and a thin-film resistor structure. The method comprises the following steps: forming a first metal layer on a first main surface of a wafer; forming a masking layer in contact with the first metal layer; a resistance material layer is formed on the first main face and patterned, the patterned resistance material layer comprises a thin-film resistor, and the thin-film resistor is in ohmic contact with the first metal connecting line in the first metal layer through the masking layer. According to the method, the first metal layer serving as the metal connecting line of the thin-film resistor is firstly formed, and then the masking layer and the thin-film resistor are formed, so that the etching of the first metal layer and the etching of the masking layer can adopt dry etching, the damage of the dry etching to the thin-film resistor does not need to be considered, and the process difficulty can be reduced.

A method for manufacturing a display device that can easily achieve higher resolution is provided. A display device having both high display quality and high resolution is provided. A first EL film is deposited over a first pixel electrode, a first sacrificial film is formed to cover the first EL film and a first electrode, and the first sacrificial film and the first EL film are etched, so that a first EL layer is formed over the first pixel electrode. Then, the first sacrificial film is removed to expose the first electrode. Furthermore, a common electrode is formed over the first EL layer and the first electrode. The first EL film is etched by dry etching, and the first sacrificial film is removed by wet etching.

Provided is a method that allows for the etching of a silicon nitride film with respect to a silicon oxide film with high selectivity and high precision while preventing a degradation in the shape of the silicon oxide film portion during etching. The etching method of dry etching a film structure which is formed in advance on a wafer disposed in a processing chamber and in which an end portion of a film stack including a silicon nitride film and silicon oxide films vertically sandwiching the silicon nitride film forms a sidewall of a trench or hole, by supplying a gas for processing into the processing chamber, without using plasma includes: forming, as a first process, a reaction layer on the silicon nitride film by reaction of hydrogen fluoride gas at 30° C. or higher and 55° C. or lower; removing, thereafter, as a second process, the reaction layer having been formed in the first process, through volatilization by performing heating at 70° C. or higher and 110° C. or lower without causing the hydrogen fluoride gas to flow; and etching the silicon nitride film from the end portion in a lateral direction by performing the first and second processes a plurality of times.

The invention provides an etching method of a double-color second-class superlattice infrared detector, and belongs to the technical field of chip manufacturing. The method comprises the following steps: providing a double-color second-class superlattice infrared detector, and forming a photoresist mask on the surface of the double-color second-class superlattice infrared detector; under the condition that the ratio of the longitudinal etching rate to the transverse etching rate is not less than 5: 1, performing dry etching on the surface of the double-color second-class superlattice infrared detector to obtain an initial mesa structure; the initial mesa structure is subjected to wet etching, a middle mesa structure is obtained, the wet etching time is smaller than or equal to 2 min, and the wet etching temperature is smaller than or equal to 10 DEG C; and post-processing the middle table-board structure to obtain the table-board structure. Through organic combination of a high-anisotropy forming effect of dry etching and a low-damage repairing effect of wet etching, the low surface damage characteristic is considered while high aspect ratio etching is realized, the dark current of the device is fundamentally reduced, and the intrinsic detection performance of the device is improved.

A resist pattern is formed by (i) applying a resist composition comprising a hypervalent iodine compound, a carboxy-containing polymer, and a solvent onto a substrate or an underlying film to form a resist film, (ii) exposing the resist film to high-energy radiation, (iii) baking the exposed resist film, and (iv) dry etching the baked resist film for development.

The invention discloses a grid system for a plasma etching system and the plasma etching system, and belongs to the field of integrated circuit manufacturing, the grid system comprises a grid mesh close to a discharge outlet side of a discharge chamber,..., an Nth middle grid mesh and a grid mesh close to a dry etching part side which are arranged in sequence, and each grid mesh comprises a substrate, a plurality of grid mesh holes are uniformly distributed in the substrate, a first film layer with low surface energy and low sputtering yield is arranged on the outer surface of the substrate, and a second film layer with low surface energy and low sputtering yield is arranged on the inner wall of each grid mesh hole; n is an integer greater than or equal to 0. The invention can delay the loss of the grid mesh and delay the adsorption pollution on the surface of the grid mesh.

The invention provides a vertical deep ultraviolet LED epitaxial structure and a preparation method thereof. The vertical deep ultraviolet LED epitaxial structure comprises a substrate, an intrinsic layer, a sacrificial layer, a first electron injection layer, an etching barrier layer, a second electron injection layer, a quantum well active layer, an electron barrier layer and a hole injection layer which are sequentially stacked from bottom to top. Wherein the etching barrier layer is made of an n-type doped AlGaN material or an n-type doped AlN material; the mass percentage content of an Al component of the etching barrier layer is 70%-100%; according to the invention, the etching barrier layer with a high Al component is inserted into the electron injection structure, and the high Al-N bond energy and strong chemical stability of the etching barrier layer are utilized, so that the subsequent epitaxial layer can be effectively prevented from being excessively corroded in the dry etching process of the sacrificial layer, and the interface damage is reduced; meanwhile, the etching barrier layer with the high Al component and the electron injection layer form a remarkable barrier difference, the high barrier can guide electrons to be transversely and uniformly diffused in the electron injection layer, and the current density uniformity of the quantum well active layer is improved.

A method is disclosed of fabricating a MEMS device that includes one or more wafers configured as pump or valve. The pump or valve includes an inlet port to receive fluid and an outlet port to release the fluid within the pump or valve. The method comprises growing silicon dioxide on a silicon layer of the one or more wafers to form a silicon dioxide layer on the silicon layer, depositing silicon nitride on the silicon dioxide layer of the one or more wafers to form a silicon nitride layer on the silicon dioxide layer, spinning a front side to create a pattern thereon defining an area for the pump or valve, dry etching the one or more wafers at the area for the pump or valve to remove the silicon dioxide and silicon nitride layers to define an opening for the pump or valve.

The application belongs to the technical field of graphene composite membrane preparation, and specifically discloses a preparation method and application of a Nafion / graphene / PES-liquid Nafion semi-hydrated composite membrane, wherein the preparation method comprises the following steps: attaching copper foil with graphene to a solid Nafion membrane, with the side of the copper foil with better graphene growth quality being in contact with the solid Nafion membrane; performing heat pressing treatment on the device; etching off the graphene on the other side of the copper foil that is not in contact with the Nafion membrane by using a dry etching method; removing the copper foil by using a wet etching method; drying the Nafion / graphene composite membrane at room temperature; immersing a PES porous membrane in liquid Nafion to obtain a PES-liquid Nafion sample; placing the sample in a water vapor environment to perform a semi-hydrated reaction and obtain a PES-liquid Nafion semi-hydrated membrane; and after drying at room temperature, attaching the Nafion / graphene composite membrane to the PES-liquid Nafion semi-hydrated membrane to obtain a Nafion / graphene / PES-liquid Nafion semi-hydrated composite membrane. The semi-hydrated composite membrane prepared by the application can be stably electrolyzed in liquid water for a long time, can enrich heavy water, and can better protect the graphene.

The invention provides a dry etching method for a molybdenum silicide layer, and relates to the field of semiconductor mask plates. The method is used for performing dry etching pattern transfer on the molybdenum silicide phase shift layer in the phase shift mask. The method comprises the following steps of: 1, putting a patterned molybdenum silicide layer into an ICP (Inductively Coupled Plasma) dry etching machine; 2, mixed SF6 gas and Ar gas are introduced into the etching cavity; and 3, the plasma concentration is regulated and controlled by controlling the ICP source, the plasma bombardment kinetic energy is regulated and controlled through the RF source, and etching of the molybdenum silicide layer is completed. According to the dry etching method, SF6 and Ar are adopted as etching gas, a good etching selection ratio and good morphology can be obtained by controlling the gas proportion, the ICP power and the RF power, and the dry etching method has the advantages of being good in safety, low in production cost and the like.

The present application relates to the technical field of microelectrode preparation, and particularly relates to a transparent microelectrode array chip preparation method, comprising the following steps: S1. pretreating a glass substrate to improve the substrate surface cleanliness and adsorbability of the electrode film; S2. evaporating an ITO film on the surface of the pretreated glass substrate by using a magnetron sputtering process, as a transparent electrode; S3. spin-coating a photoresist on the surface of the ITO film and performing a patterning treatment, and then etching the ITO film to form a preset electrode structure by using a dry etching process, and then removing the photoresist and cleaning and drying; S4. coating an insulating layer on the surface of the substrate by using a PECVD process, patterning the insulating layer and etching by using a dry etching process to realize windowing, and then removing the photoresist and cleaning and drying; and realizing photoelectric synchronous detection. Avoiding metal residue interference: photoresist masks are used throughout the etching process to replace traditional metal hard masks.

The present invention provides a metal etching method, characterized by comprising the following steps: S1, depositing a metal layer on a dielectric layer on a wafer substrate; S2, performing a first photolithography on the metal layer using an original metal photomask; S3, performing a first dry etching on the metal layer, followed by removal of the photoresist; S4, providing a protective metal photomask, and performing a second photolithography on the metal layer; S5, performing a second dry etching to remove metal residue on the sidewalls, followed by removal of the photoresist. This method provides a metal etching process employing two dry etching steps, eliminating metal residue on the sidewalls and meeting metal-related parameter requirements for small-sized devices.

The utility model relates to a kind of double sealing door mechanism of dry etching platform for radio frequency component in the field of radio frequency component manufacturing, including the processing box with processing cavity and the sealing door plate for closing processing cavity by being connected on processing box with hinge, still include: the sealing component for increasing the sealability between processing cavity is configured on the sealing door plate, temporary plugging is also carried out on the sealing component failure in the sealing door plate and is equipped with plugging component, leakage detection unit is arranged between the sealing component and plugging component;The application is designed by using main sealing, emergency sealing, leakage monitoring triple guarantee, effectively solve the problem that traditional single sealing door is easily caused by sealing element failure to lead to processing cavity air leakage, improve the sealing reliability of etching platform, avoid the influence of etching precision of radio frequency component due to air leakage, and the early warning function of leakage detection unit is convenient for staff to maintain in time, reduce equipment downtime loss.

The utility model discloses a dry etching equipment cavity protection device and dry etching equipment. According to the cavity protection device, a cavity attaching part comprises a first through hole, a first surface and a second surface, wherein the first surface and the second surface are oppositely arranged, and the first through hole penetrates through the first surface and the second surface; the cavity opening attaching part is provided with a second through hole and located on the first surface of the cavity attaching part, the diameter of the inner wall of the cavity opening attaching part is the same as that of the inner wall of the cavity attaching part, and the wall thickness of the cavity opening attaching part is smaller than that of the cavity attaching part; the bottom attaching part is arranged on the second surface of the cavity attaching part and located in the first through hole, the side wall of the bottom attaching part is connected with the inner wall of the cavity attaching part, and the surface, away from the cavity opening attaching part, of the bottom attaching part is flush with the surface, close to the bottom attaching part, of the cavity attaching part; the cavity attaching part is provided with a first hole and a second hole. According to the utility model, the protection on the inner wall of the cavity is improved.

The invention relates to a preparation process of a deep ultraviolet micro LED (light-emitting diode) array with self-aligned electrodes. According to the process, a metal barrier layer is deposited, a mesa shape is formed through wet etching, a mesa is formed through etching, a passivation layer is filled to protect the side wall, the CMP technology is combined, the surface is polished to be flat, ICP etching is carried out, the metal barrier layer is exposed, the metal barrier layer is washed away, the mesa can be exposed, and then a long electrode does not need to be aligned with the process in a high-precision mode. Complex procedures are not needed, the alignment difficulty is overcome and the chip yield is improved by combining the planarization of the filling thick passivation layer and the ICP dry etching technology, and industrialization of micro-LED array preparation is facilitated.

The invention relates to a resist underlayer film forming composition, a pattern forming method, and a resist underlayer film forming method. The purpose of the present invention is to provide: a composition for forming a resist underlayer film, which functions as an anti-reflective film and has excellent alkaline hydrogen peroxide water resistance, good landfill / planarization characteristics, and dry etching characteristics; a pattern forming method using the composition; and a method for forming a resist underlayer film. A composition for forming a resist underlayer film, which is characterized by containing (A) a polymer compound having a structural unit (a1) represented by formula (A-1) and at least one structural unit (a2) selected from structural units represented by formulae (A-2) to (A-4), (B) a crosslinking agent represented by formula (B-1), and (C) an organic solvent.

The application provides a MOSCAP device trench preparation method, comprising the following steps: S1, providing a wafer to be processed, performing photoetching and ion implantation on the wafer to form a first ion implantation area; S2, annealing the wafer to diffuse the first ion implantation area to form a second ion implantation area; S3, growing an oxide layer on the wafer; and S4, removing the oxide layer by wet etching to form a target trench structure. The preparation method can improve the relatively sharp angle formed in the dry etching process, thereby reducing the stress at the angle and improving the reliability of the device. The application further provides a MOSCAP device.

The reflective mask blank (100) according to the present invention is a reflective mask blank (100) for use as a material for a reflective mask (110) used in EUV lithography using extreme ultraviolet (EUV) light as exposure light. This reflective mask blank (100) is provided with: a substrate (1); a multilayer reflective film (2) that is formed on one main surface of the substrate (1) and reflects exposure light; a protective film (3) that is formed on the multilayer reflective film (2) and protects the multilayer reflective film (2); an absorption film (6) that is formed above the protective film (3) and that absorbs exposure light; and intermediate films (4, 5) provided between the protective film (3) and the absorbent film (6). The intermediate films (4, 5) include: a first intermediate film (4) containing niobium (Nb); and a second intermediate film (5) that is positioned closer to the absorbing film (6) than the first intermediate film (4) and is made of a material that can be dry-etched by an oxygen-containing gas. The absorber film (6) is formed of a material that can be dry-etched by a fluorine-containing gas.

This invention provides a high-selectivity dry etching method for surface convergence before p-GaN regrowth, comprising: etching the surface of the p-GaN layer or GaN layer of a GaN / AlGaN heterojunction in a Cl-based gas atmosphere to remove the native oxide layer and contaminants; introducing a mixture of BCl3 and fluorine-containing gas into a reaction chamber under inductively coupled plasma conditions, and maintaining the self-bias voltage within a first preset range for etching to selectively remove the p-GaN layer or GaN layer and achieve near-stop etching in the AlGaN layer, wherein the fluorine-containing gas is used to form an aluminum fluoride layer on the surface of the AlGaN layer to inhibit etching; and reducing the self-bias voltage from the first preset range to a second preset range and / or reducing the proportion of fluorine-containing gas in the mixed gas under plasma conditions to perform convergence treatment on the surface of the near-stop etched structure. This improves the repeatability of the process window and the adaptability of the regeneration length.

The invention discloses a method for composite etching of an electroplating gold plating layer, which comprises the following steps of: manufacturing a photoetching pattern on the front surface of gallium arsenide epitaxy, then evaporating a metal contact layer, depositing a SiNx protective mask layer, performing Mesa mesa etching on the gallium arsenide epitaxy, exposing a high-aluminum layer on the side surface of an epitaxial material, and forming an aluminum oxide limiting layer by adopting a wet oxidation process; a second SiNx protective mask layer continues to be deposited, and the metal contact layer is exposed through dry etching; forming a seed gold layer by adopting magnetron sputtering TiW / Au metal, and forming a photoresist mask with a target electrode pattern on the seed gold layer; electroplating thick gold on the photoresist mask pattern; the photoresist mask layer is removed after completion; the method of combining dry etching and wet etching is adopted to remove the gold plating layer in the non-electroplating area, so that the lateral corrosion of the metal layer is obviously reduced, the high-precision and high-fidelity electrode pattern transfer is realized, the lateral corrosion of the metal layer is reduced, and the passivation protection effect of the device is improved.