5469 results about "Dry etching" patented technology

Provided is a dry etching method for an oxide semiconductor film containing at least In, Ga, and Zn, which includes etching an oxide semiconductor film in a gas atmosphere containing a halogen-based gas.

Provided is a dry etching method for an oxide semiconductor film made of In—Ga—Zn—O, in which an etching gas containing a hydrocarbon is used in a dry etching process for the oxide semiconductor film made of In—Ga—Zn—O formed on a substrate.

A tray 15 for a dry etching apparatus 1 has substrate accommodation holes 19A to 19D penetrating thickness direction and a substrate support portion 21 supporting an outer peripheral edge portion of a lower surface 2a of a substrate 2. A dielectric plate 23 has a tray support surface 28 supporting a lower surface of the tray 15, substrate placement portions 29A through 29D inserted from a lower surface side of the tray 15 into the substrate accommodation holes 19A through 19D and having a substrate placement surface 31 at its upper end surface for placing the substrate 2. A dc voltage applying mechanism 43 applies a dc voltage to an electrostatic attraction electrode 40. A heat conduction gas supply mechanism 45 supplies a heat conduction gas between the substrate 2 and substrate placement surface 31. The substrate 2 can be retained on the substrate placement surface 31 with high degree of adhesion. This results in that the cooling efficiency of the substrate 2 is improved and processing is uniformed at the entire region of the substrate surface including the vicinity of the outer peripheral edge.

A III-Nitride field-effect transistor, specifically a HEMT, comprises a channel layer, a barrier layer on the channel layer, an etch stop layer on the cap layer, a dielectric layer on the etch stop layer, a gate recess that extends to the barrier layer, and a gate contact in the gate recess. The etch stop layer may reduce damage associated with forming the recessed gate by not exposing the barrier layer to dry etching. The etch stop layer in the recess is removed and the remaining etch stop layer serves as a passivation layer.

A method for etching a target layer on a substrate by a dry etching process includes at least one etching cycle, wherein an etching cycle includes: depositing a halogen-containing film using reactive species on the target layer on the substrate; and etching the halogen-containing film using a plasma of a non-halogen etching gas, which plasma alone does not substantially etch the target layer, to generate etchant species at a boundary region of the halogen-containing film and the target layer, thereby etching a portion of the target layer in the boundary region.

A method of forming spacers for spacer-defined multiple pattering (SDMP), includes: depositing a pattern transfer film by PEALD on the entire patterned surface of a template using halogenated silane as a precursor and nitrogen as a reactant at a temperature of 200° C. or less, which pattern transfer film is a silicon nitride film; dry-etching the template using a fluorocarbon as an etchant, and thereby selectively removing a portion of the pattern transfer film formed on a top of a core material and a horizontal portion of the pattern transfer film while leaving the core material and a vertical portion of the pattern transfer film as a vertical spacer, wherein a top of the vertical spacer is substantially flat; and dry-etching the core material, whereby the template has a surface patterned by the vertical spacer on a underlying layer.

A method for etching a target layer on a substrate by a dry etching process includes at least one etching cycle, wherein an etching cycle includes: depositing a carbon halide film using reactive species on the target layer on the substrate; and etching the carbon halide film using a plasma of a non-halogen hydrogen-containing etching gas, which plasma alone does not substantially etch the target layer, thereby generating a hydrogen halide as etchant species at a boundary region of the carbon halide film and the target layer, thereby etching a portion of the target layer in the boundary region.

A method of forming vertical spacers for spacer-defined multiple patterning, includes: depositing a first conformal pattern-transfer film having a first film stress, and continuously depositing a second conformal pattern-transfer film having a second film stress on a template; dry-etching the template except for a core material and a vertical portion of the first and second pattern-transfer films to form vertical spacers; and dry-etching the core material, forming a vacant space between the vertical spacers, wherein by adjusting the difference in film stress between the first and second pattern-transfer films, the leaning angle of the spacers is adjusted.

To provide a very-low-cost and short-TAT connection structure superior in connection reliability in accordance with a method for three-dimensionally connecting a plurality of semiconductor chips at a shortest wiring length by using a through-hole electrode in order to realize a compact, high-density, and high-function semiconductor system. The back of a semiconductor chip is decreased in thickness up to a predetermined thickness through back-grinding, a hole reaching a surface-layer electrode is formed at a back position corresponding to a device-side external electrode portion through dry etching, a metallic deposit is applied to the sidewall of the hole and the circumference of the back of the hole, a metallic bump (protruded electrode) of another semiconductor chip laminated on the upper side is deformation-injected into the through-hole by compression bonding, and the metallic bump is geometrically caulked and electrically connected to the inside of a through-hole formed in an LSI chip. It is possible to realize a unique connection structure having a high reliability in accordance with the caulking action using the plastic flow of a metallic bump in a very-low-cost short-TAT process and provide a three-dimensional inter-chip connection structure having a high practicability.

An etching apparatus is provided, in which a plurality of electrodes are disposed for placing a substrate, high-frequency power sources as many as electrodes are provided, and the electrodes and the high-frequency power sources are connected to each other independently. Among a plurality of electrodes, a high-frequency power applied to an electrode disposed below the central portion of the substrate and a high-frequency power applied to electrodes disposed below comer portions of the substrate are controlled respectively, whereby in-plane uniformity of etching can be enhanced.

The following resist composition which is excellent particularly in transparency to light beams and dry etching properties and gives a resist pattern excellent in sensitivity, resolution, evenness, heat resistance, etc., as a chemical amplification type resist, is presented. A resist composition which comprises a fluoropolymer (A) having repeating units represented by a structure formed by the cyclopolymerization of one molecule of a fluorinated diene and one molecule of a monoene, in which the monoene unit in each repeating unit has a blocked acid group capable of regenerating the acid group by the action of an acid, an acid-generating compound (B) which generates an acid upon irradiation with light, and an organic solvent (C).

The invention discloses an etching method, a low-temperature polysilicon thin film transistor and an AMOLED panel. The etching method comprises the steps of pumping sulfur hexafluoride SF<6> and oxygen O<2> to a process chamber to perform etching on a metal molybdenum Mo layer to obtain molybdenum fluoride MoF<x>; pumping chlorine Cl<2> and oxygen O<2> to perform etching on the metal molybdenum Molayer to obtain molybdenum chloride MoCl<x>; and pumping a fluoro-etching gas and oxygen O<2> to be reacted with MoCl<x> to obtain easily volatile molybdenum oxyfluoride MoF<x>O<y>. By virtue of thescheme provided by the invention, residue of dry etching resultants can be reduced, and the problem of a display abnormal phenomenon of the AMOLED panel is solved.

There are included steps of forming a silicon nitride layer on a silicon layer or a silicon oxide layer, loading the silicon layer or the silicon oxide layer and the silicon nitride layer in a dry etching atmosphere, and selectively etching the silicon nitride layer with respect to the silicon layer or the silicon oxide layer by flowing a fluorine gas consisting of any one of CH2F2, CH3F, or CHF3 and an inert gas to the dry etching atmosphere. Hence, in the etching process of the silicon nitride layer, the etching selectivity of the silicon nitride layer to Si or SiO2 can be enhanced and also etching anisotropy can be enhanced.

A plasma composition and its use in a method for the dry etching of a stack of at least one material chemically too reactive towards the use of a Cl-based plasma are provided. Small amounts of nitrogen (5% up to 10%) can be added to a BCl₃ comprising plasma and used in an anisotropical dry etching method whereby a passivation film is deposited onto the vertical sidewalls of stack etched for protecting the vertical sidewalls from lateral attack such that straight profiles can be obtained.

A method for manufacturing a fin-type field effect transistor simply and securely by using a SOI (Silicon On Insulator) wafer, capable of suppressing an undercut formation, is disclosed. The method includes forming a fin-shaped protrusion by selectively dry-etching a single crystalline silicon layer until an underlying buried oxide layer is exposed; forming a sacrificial oxide film by oxidizing a surface of the protrusion including a damage inflicted thereon; and forming a fin having a clean surface by removing the sacrificial oxide film by etching, wherein an etching rate r₁ of the sacrificial oxide film is higher than an etching rate r₂ of the buried oxide layer during the etching.