1687 results about "Dry etching" patented technology

A method for manufacturing a vibration element that includes a base portion, a first vibration arm and a second vibration arm that extend from the base portion along a first direction and are arranged along a second direction intersecting the first direction, and bottomed grooves on both main surfaces of the first vibration arm and both main surfaces of the second vibration arm includes: a preparing step of preparing a crystal substrate; a protective film forming step of forming a protective film on the crystal substrate except for groove regions that are regions in which the grooves are formed; and a dry etching step of dry etching the crystal substrate through the protective film to form the grooves. The grooves provided in at least one of the first vibration arm and the second vibration arm include a first groove and a second groove arranged along the second direction.

The invention discloses an actuator structure and a liquid spraying device comprising the same, the actuator structure comprises a vibrating membrane, a piezoelectric material, a lower electrode and an upper electrode, the top surface and the bottom surface of the piezoelectric material are respectively connected to the upper electrode and the lower electrode, the vibrating membrane is connected to the bottom surface of the lower electrode, and the upper electrode is connected to the bottom surface of the piezoelectric material. The piezoelectric material is a single crystal piezoelectric film material. The liquid spraying device comprises the actuator structure. According to the actuator structure and the liquid spraying device comprising the actuator structure, the piezoelectric material is processed and manufactured by using the single crystal piezoelectric film material, so that the single crystal piezoelectric film material can be processed by using a wet etching technology, the problems in a dry etching process are effectively avoided, the preparation precision of the actuator structure is ensured, and the manufacturing cost of the actuator structure is reduced. The stability of the actuator structure is improved, and the manufacturing cost of the actuator structure is reduced.

The invention discloses a preparation method of a lithium niobate film waveguide frequency doubling device based on ferroelectric domain regulation and control. The method comprises the following steps of: spin-coating photoresist on the surface of a lithium niobate film, transferring a pattern by utilizing a photoetching technology, coating a film, stripping to form an electrode, applying high-voltage electric pulse to the electrode, and controlling the size of an electric field in the lithium niobate film and a reversal domain growth process through the material and the thickness of an insulating layer in the electrode, thereby controlling the reversal depth of a ferroelectric domain. And finally, spin-coating the photoresist again, transferring the pattern by photoetching, and performing dry etching to obtain the frequency doubling waveguide device. The frequency multiplication waveguide device preparation method provided by the invention has the characteristics of simple processing method, high device preparation efficiency and low loss, and meets the actual requirements in the fields of nonlinear optics, integrated optics and the like.

A silicon-containing resist underlayer film forming composition for forming a resist underlayer film which is able to be removed not only by a conventional dry etching method but also by a wet etching method that uses a chemical agent, and which has excellent lithography characteristics, while enabling the achievement of a high etching rate during wet etching. A silicon-containing resist underlayer film forming composition which contains (A) a polysiloxane, (B) nitric acid, (C) a bisphenol compound and (D) a solvent.

A semiconductor process provides a semiconductor substrate including a plurality of pads and a passivation layer. The passivation layer has a plurality of openings to expose the pads. Forming a ball bottom metal material layer on the connecting pad and the passivation layer; a bump is formed on the under-ball metal material layer by electroplating and overlaps the pad and a portion of the passivation layer in an orthographic projection direction. A patterned photoresist layer is formed on the bumps. The patterned photoresist layer completely covers the bump and extends towards the outer periphery of the bump to cover the ball bottom metal material layer. A first part of the ball bottom metal material layer is formed at the part covered by the patterned photoresist layer, and a second part of the ball bottom metal material layer is formed at the part not covered by the patterned photoresist layer. And removing a second part, which is not covered by the patterned photoresist layer and the bumps, of the under-ball metal material layer. And removing the patterned photoresist layer to expose the first part which is originally covered by the patterned photoresist layer. And removing the first part on the passivation layer by adopting dry etching to form a ball bottom metal layer. And the side wall of the ball bottom metal layer is flush with the side wall of the bump.

The invention discloses a manufacturing method of an insulating printed circuit board based on high voltage resistance. The manufacturing method comprises the following steps: S1, mixing ceramic powder and polyimide, and heating and curing to form a base material; s2, pollutants on the surface of the base material are removed through a plasma cleaning technology, and the binding force of the base material and a subsequent layer is improved; s3, transferring a circuit pattern to the surface of the base material on the base material through a laser direct writing technology; s4, performing deposition on the circuit pattern through a vacuum deposition technology to form a copper film layer; s5, performing mask manufacturing by using photoresist, and removing the copper film layer which is not covered by the mask through wet or dry etching to form a circuit; s6, a laser drilling technology is used for drilling micropores, and the inner walls of the micropores are metalized through a chemical copper plating technology; and S7, after circuit manufacturing is completed, ultraviolet light curing epoxy resin is used as an insulating coating. The circuit board material and the implementation method are innovated, so that the problems in the prior art are solved, and the voltage resistance, the insulating property and the reliability of the circuit board are improved.

The invention discloses a polycrystalline silicon etching method, which comprises the following steps of: firstly, carrying out a polycrystalline silicon etching process for the first time, and carrying out a certain amount of transverse etching; an isotropic dry etching process is adopted, so that the polycrystalline silicon has transverse etching. And then a polycrystalline silicon etching process with a high selection ratio is carried out, and an anisotropic etching process is adopted to ensure that the polycrystalline silicon on the surface is etched cleanly. According to the etching process, a step-by-step etching process method is adopted, the isotropic etching process is firstly carried out to control the etching amount of transverse etching, then the anisotropic etching method and the high-selectivity etching method are adopted to carry out etching of different etching amounts on areas with inconsistent feature sizes, and accurate etching of polycrystalline silicon is guaranteed.

The invention relates to the technical field of semiconductor manufacturing, provides a wafer dry etching control method and system, aims to monitor an etching process in real time and dynamically control the etching process with high precision, and comprises the following steps: step 1, monitoring etching equipment, and collecting an etching parameter combination of etching and image information of a wafer etching area; 2, constructing a real-time data processing model, developing a multi-objective optimization function, and inputting a target value into the multi-objective optimization function to obtain an initial etching parameter combination; 3, in the etching process, a predicted value of etching result data is obtained through the real-time data processing model, the predicted value is compared with a target value, and an etching parameter combination of etching is dynamically adjusted; and 4, constructing an end point prediction model, monitoring whether the image features of the etched image information reach a preset threshold value or not in real time by the end point prediction model, and if yes, sending an etching end point signal. In addition, the invention provides a semiconductor wafer high-precision dry etching control system.

The invention provides a method for forming a strained silicon layer and a semiconductor structure, which comprises the steps of covering a semiconductor layer and a gate stack structure to form an etching stop layer, and the semiconductor layer comprises a first device region and a second device region which are separated from each other; forming an auxiliary side wall surrounding the side wall of the gate stack structure on the etching stop layer; forming a patterned hard mask layer; taking the patterned hard mask layer as an etching mask, and performing selective etching on the second device region through a wet etching process to form a sigma trench; and growing a strained silicon layer in the sigma groove. According to the invention, on the premise of not sacrificing the consistency of the critical dimensions of the sigma trench, the etching load effect caused by dry etching in the forming process of the sigma trench is avoided.

The invention belongs to the technical field of semiconductors, and provides a cleavage method, which adopts non-mechanical means such as etching, corrosion and the like to avoid the action of mechanical stress on a slice wafer, thereby greatly reducing the possibility of cracks on the end face of the slice wafer. Specifically, the cleavage method is implemented according to the following steps: growing silicon oxide on the back surface of a thin wafer to form a mask layer; coating photoresist on the surface of one side, deviating from the sheet wafer, of the mask layer to form a second glue layer; photoetching the second adhesive layer to construct a second cleavage region which is overlapped with the first cleavage region on the front surface of the thin wafer; removing silicon oxide on the mask layer relative to the position of the second cleavage region; coating at least two layers of photoresist on the front surface of the thin wafer to form a first adhesive layer; photoetching the first adhesive layer, and displaying a first cleavage area through a developing step; performing dry etching on the front surface of the sheet wafer; and performing wet etching on the back surface of the sheet wafer.

A dry etching method of the present disclosure includes bringing a β-diketone and a gas containing a halogen atom in its molecule into contact with an etching target film containing a metal, an oxide of the metal, or a nitride of the metal formed on a surface of a workpiece to etch the etching target film, the metal containing at least one selected from the group consisting of In, Ga, Cu, Co, Fe, Sn, Zn, Al, Ta, and As.

The invention relates to the technical field of semiconductor manufacturing, and discloses a plasma dry etching process monitoring method and device based on a metasurface, and the method comprises the steps: obtaining a first photoetching layout corresponding to all structures of a target device; determining a key structure area of the target device in the first photoetching layout, periodically repeating the key structure area to form a metasurface of the key structure, and obtaining a corresponding second photoetching layout according to the metasurface; wherein the key structure comprises all structures; splicing the second photoetching layout and the first photoetching layout in parallel to obtain an integral photoetching layout; carrying out a plasma dry etching process on the whole photoetching layout; obtaining a terahertz reflection spectrum generated by irradiating a corresponding area of a second photoetching layout in the whole photoetching layout through an electromagnetic beam; and according to the terahertz reflection spectrum, determining a process state of a plasma dry etching process in a key structure area in the first photoetching layout in the whole photoetching layout.

The invention relates to the technical field of wireless communication, and provides a preparation method of a surface acoustic wave filter and the surface acoustic wave filter.The preparation method comprises the steps that S1, a substrate of the surface acoustic wave filter is obtained; s2, growing a plurality of metal electrodes and a protective layer on the front surface of the substrate, wherein the protective layer completely covers the plurality of metal electrodes; s3, presetting a soaking column area on the substrate, and spin-coating a layer of photoresist on the back surface of the substrate; s4, removing the photoresist in the soaking column region through exposure and development; s5, etching the soaking column region through dry etching to form a groove, and removing the residual photoresist on the substrate; s6, depositing an electroplating seed layer on the back surface of the substrate, and continuing to complete the copper electroplating process, so that the groove is filled with copper; and S7, grinding the back surface of the substrate until the back surface of the substrate is exposed, and reserving the soaking column formed in the groove to obtain the surface acoustic wave filter. The surface acoustic wave filter provided by the invention can effectively improve the thermal damage resistance of the device under the working condition of high input power.

The invention provides a novel semiconductor test probe manufacturing process, which comprises the following steps of: coating a first photoresist layer on a silicon substrate, photoetching and developing; growing a metal layer on the silicon substrate by using an electroplating method; cleaning after removing the first photoresist layer; growing a silicon oxide layer on the silicon substrate and the metal layer; coating a second photoresist layer, photoetching and developing to form a probe beam etching position; performing dry etching on the silicon oxide layer below the etching position of the probe beam; performing partial dry etching on the metal layer below the etching position of the probe beam to form the probe beam; cleaning after removing the second photoresist layer; cleaning after removing the silicon oxide layer; coating a third photoresist layer, photoetching and developing to form a probe angle etching position; partially etching the metal layer below the probe angle etching position to form a probe head; and cleaning after removing the third photoresist layer. According to the novel semiconductor test probe manufacturing process provided by the invention, the process flow is simplified, and the tip angle of the probe can be well controlled.

The invention provides a dual damascene process method, and relates to the technical field of semiconductors. The dual damascene process method comprises the following steps: sequentially forming a dielectric layer, a patterned first hard mask layer, a first planarization layer and a patterned second hard mask layer on a substrate; performing dry etching by using the second hard mask layer to form a through hole stopped on the surface of the substrate; removing the second hard mask layer and the first planarization layer; performing dry etching by using the first hard mask layer to form a groove; removing the first hard mask layer; and forming a metal layer to fill the through hole and the groove so as to obtain the dual damascene structure. According to the process method, the connectivity of the formed through hole can be ensured, and a low-resistance channel of a metal interconnection structure is subsequently formed in the bottom area of the through hole; meanwhile, the first hard mask layer is removed after the through hole is formed, accurate transmission of the key size of the through hole can be ensured, the accuracy of the key size of the subsequently formed metal interconnection structure is improved, and therefore the yield of a chip product and the performance of a device are improved.

The invention relates to the technical field of vacuum measurement, in particular to a multi-sealing-cavity MEMS capacitor thin film vacuum gauge, and is characterized in that a silicon substrate is arranged above substrate glass and is bonded with the substrate glass; a pressure sensing film is obtained in the middle of the silicon substrate in a photoetching and dry etching mode; a fixed metal electrode is obtained in the middle of the substrate glass in a photoetching and sputter coating mode; a capacitance gap is formed between the fixed metal electrode and the pressure sensing film; photoetching and corroding the silicon substrate, forming a working sealing cavity above the pressure sensing film, and respectively forming a first cavity and a second cavity above two sides of the pressure sensing film; getter blocks are arranged in the first chamber and the second chamber; and the sealing glass is arranged above the silicon substrate. On the premise that the size of the vacuum gauge is not obviously increased, the multiple chambers are arranged to form the sealing cavity, the air suction capacity is improved, high vacuum obtaining and long-term maintaining performance of the sealing cavity of the vacuum gauge are ensured, and the long-term stability of the vacuum gauge is greatly improved.

The invention discloses a Micro-LED chip array integrated with a homogeneous micro-lens array and a preparation method thereof, and the method comprises the steps: carrying out the wafer-level precise bonding of a Micro-LED light-emitting pixel array and a CMOS drive circuit substrate, removing a substrate, integrating a homogeneous pixel-level GaN micro-lens array on a GaN-based pixel array through the photoetching, hot melting backflow and dry etching technologies, and carrying out the precise bonding of the micro-LED light-emitting pixel array and the CMOS drive circuit substrate. And finally, realizing the full-pixel common cathode conduction of the Micro-LED chip by adopting a metal interconnection process. According to the method, the Micro-LED pixel array and the micro-lens array are homogeneously integrated, are made of the same material and have no refractive index difference, so that no Fresnel loss exists on an interface, and the light extraction efficiency of a chip is improved. In addition, the method is simple in manufacturing process, low in cost, good in chip structure reliability, high in stability and suitable for being applied to industrial chip manufacturing.

The invention belongs to the technical field of inertial sensors, and particularly discloses an MEMS accelerometer with low parasitic capacitance and a preparation method. According to the invention, the hollow area is formed at the position directly facing the back of the pickup electrode, so that the directly facing area between the pickup electrode and the upper cover silicon substrate is reduced, and the parasitic capacitance is reduced. In addition, a grounding polar plate is arranged between the pickup electrodes, so that the relative movement between the excitation electrode and the silicon substrate of the upper cover plate is shielded, and the influence of stray capacitance between the excitation electrode and the silicon substrate is further reduced. The hollow area is formed on the back of the pickup electrode of the MEMS accelerometer through the thin film supporting structure in combination with plasma dry etching, and the preparation method is simple in process, suitable for various capacitive MEMS accelerometers or gravimeters and good in compatibility and practicability.

The invention provides a metal gate and a preparation method thereof, and the preparation method comprises the steps: depositing a first metal material, carrying out the dry etching of the first metal material in a second part of a groove, removing a protrusion, enlarging the size of an opening of the groove, and filling a second metal material to form the metal gate, thereby solving a gap defect in the metal gate, and improving the reliability of the metal gate. According to the invention, the stability of the metal gate can be improved, and the difference of pattern loading (pattern loading effect) can be reduced.

The invention relates to the technical field of photoelectricity, in particular to a light-emitting diode chip and a preparation method thereof and an LED. In the preparation method provided by the invention, an N-type semiconductor layer in a non-preset area is subjected to second photoetching treatment and second dry etching, etching gases adopted by the second dry etching are CF4 gas and Ar gas, and the etching gases adopted by the second dry etching are CF4 gas and Ar gas; therefore, the Si doping concentration of the N-type semiconductor layer in the non-preset area is lower than the Si doping concentration of the N-type semiconductor layer in the non-first area, third photoetching processing and third dry etching are carried out on the N-type semiconductor layer in the preset area, and the etching gas adopted by the third dry etching is SiCl4 gas and Ar gas, so that the Si doping concentration of the N-type semiconductor layer in the non-preset area is lower than the Si doping concentration of the N-type semiconductor layer in the non-first area. According to the invention, the specific etching gas is adopted twice to carry out the etching treatment in the specific region, so that the voltage of the chip is reduced, and the brightness of the chip is improved at the same time.

The invention provides a manufacturing method of a sigma trench and a semiconductor device thereof, and the manufacturing method of the sigma trench comprises the steps: providing a substrate, forming a gate structure on the substrate, and forming source and drain regions in the substrate at two sides of the gate structure; anisotropic dry etching is carried out, and a first groove is formed in the source drain region; performing an isotropic chemical reaction, raising the temperature after the reaction is finished to sublimate a reaction product, forming a second groove in the first groove, enabling the top of the side wall of the second groove to be located at the bottom of the gate structure, and forming an undercut at the bottom of the gate structure; and performing wet etching, and forming a sigma groove in the second groove. According to the Sigma trench formed by the three steps of anisotropic dry etching, isotropic chemical reaction and wet etching, the top of the side wall of the Sigma trench is located at the bottom of the gate structure, and the undercut is formed at the bottom of the gate structure, so that the linear distance between the source region and the drain region is shortened, the resistance is reduced, and the performance of the device is improved.

To provide a resist underlayer film formation method capable of forming a resist underlayer film exhibiting excellent dry etching resistance.SOLUTION: A resist underlayer film formation method for forming a resist under layer film on a substrate includes a step (i) of coating a composition for resist underlayer film formation containing a polymer (A) and an organic solvent onto the substrate and obtaining a coating film, and subjecting the coating film to heat treatment at a temperature of 100°C or higher and 800°C or lower from 10 seconds to 7,200 seconds and curing the coating film, to form an underlayer film precursor film, and a step (ii) of curing the underlayer film precursor film by plasma irradiation, to form a resist underlayer film, wherein as the polymer (A), an aromatic ring-containing resin containing no hydroxyl group and organic group represented by the following general formula (1) in a repeating unit constituting the polymer is used.SELECTED DRAWING: Figure 1

The invention discloses a Micro-LED (Light Emitting Diode) device self-alignment groove filling and passivating method, which comprises the following steps that a Micro-LED device is provided, and the Micro-LED device comprises array units and grooves between the array units; preparing a dielectric layer on the Micro-LED device, wherein the dielectric layer fills the groove and covers all the array units; curing the dielectric layer; and thinning the whole surface of the dielectric layer by using a mask-free dry etching back etching method until the upper surfaces of all the array units are exposed, and forming a patterned passivation layer at the groove. The whole surface of the dielectric layer is thinned by using a mask-free dry etching back etching method, mask preparation and photoetching are not needed, the height of the dielectric layer can be accurately regulated and controlled through an etching process, and the process is simple; meanwhile, due to the fact that the register step and the developing solution corrosion step are avoided, the technological method can eliminate the problems of interface gaps and table top residues caused by register errors, the graphical passivation layer which is tightly connected can be formed without being restrained by the shape and the size, the etching resistance of the passivation structure is improved, and the device manufacturing yield is improved.

To provide an EUV mask blank which prevents damage to a multilayer reflective film due to dry etching using a halogen gas as an etching gas, and dry etching using an oxygen-based gas as an etching gas.SOLUTION: In a reflective mask blank for EUV lithography, a multilayer reflective film reflecting EUV light, a protective film for the multilayer reflective film, and an absorption layer absorbing EUV light are formed in this order. The protective film is made of rhodium (Rh) or a rhodium material including Rh and at least one element selected from the group consisting of nitrogen (N), oxygen (O), carbon (C), boron (B), ruthenium (Ru), niobium (Nb), molybdenum (Mo), tantalum (Ta), iridium (Ir), palladium (Pd), zirconium (Zr), and titanium (Ti).SELECTED DRAWING: None

The invention discloses a GaN HEMT (High Electron Mobility Transistor) device with high gate reliability and a preparation method thereof. The preparation method comprises the following steps: providing a basic structure; sequentially forming a p-type GaN layer, a gate material layer, a dielectric mask layer and a metal mask layer; patterning etching is carried out; carrying out wet etching on the metal mask structure, and meanwhile, generating a corrosion effect on the side surface of the grid precursor to form a grid; performing dry etching to form a p-type GaN structure; performing plasma treatment on the side surface; and respectively manufacturing and forming a source electrode and a drain electrode. Dry etching is replaced by wet etching to form a structure that the p-type GaN structure extends to the source and drain sides, grid self-alignment etching is achieved, the uniformity and controllability of an extension area are improved, the technological process is simplified, the repeatability of device structure preparation is guaranteed, meanwhile, plasma is used for treating and passivating the side wall, and the device structure is more stable in performance. Current leakage caused by a surface state and surface roughness is suppressed, off-state leakage of the device is greatly reduced, and reliability is improved.

Aspects of the present disclosure relate to a process flow for fabricating a waveguide structure having a silicon nitride core with atomic-scale smooth sidewalls achieved by wet etch (rather than traditional dry etch treatment). The mask is pre-biased to account for lateral etching during the wet etching step.

The invention provides semiconductor process equipment and an etching method. The equipment comprises a plasma excitation device and a process chamber, and the plasma excitation device comprises a first sub-cavity, a second sub-cavity, a first radio frequency assembly and a second radio frequency assembly, the first sub-cavity and the second sub-cavity are communicated with each other, and the first radio frequency assembly and the second radio frequency assembly are connected with the first sub-cavity and the second sub-cavity respectively. The first sub-cavity is communicated with a first gas source, and the first gas source can convey first process gas to the first sub-cavity; the first radio frequency assembly is used for exciting a first gas source into first plasma; the second sub-cavity is communicated with a second gas source, and the second gas source can convey second process gas to the second sub-cavity; the second radio frequency assembly is used for exciting the gas and / or the first plasma in the second sub-cavity, so that the gas and / or the first plasma react in the second sub-cavity, and a reaction product containing free radicals is generated. And the free radicals can chemically react with the material on the surface of the wafer, so that chemical dry etching on the wafer by using the free radicals is realized, and the damage to the surface of the wafer is reduced.

Provided is a method for etching a silicon nitride film with high accuracy and high selectivity with respect to a silicon oxide film, while preventing deterioration of the shape of a silicon oxide film portion during etching. A dry etching method according to the present invention is used for etching a film structure that is formed in advance on a wafer disposed in a processing chamber, and that is configured such that an end portion of a film layer obtained by laminating a silicon nitride film so as to be vertically sandwiched by silicon oxide films constitutes a side wall of a groove or a hole, in a state in which a gas for processing is supplied into the processing chamber and no plasma is used, wherein: the method comprises (a) a step for reacting a hydrogen fluoride gas at a prescribed temperature to form a reaction layer on the silicon nitride film, (b) a step for channeling a gas of a polar solvent to process the reaction layer formed in step (a), and (c) a step for performing heating at a temperature higher than that in step (a) in a state in which no hydrogen fluoride gas is channeled and volatilizing the reaction layer formed in step (a) and processed in step (b) to remove the reaction layer; and steps (a) to (c) are repeated a plurality of times.

To provide a pattern forming method capable of forming a fine pattern with a high aspect ratio without causing pattern collapse.SOLUTION: A pattern forming method comprises preparing a resist material containing a polymer having a silicon-containing acid-labile group, forming a resist film by using the resist material, exposing and baking the resist film, and then developing the resist film by dry etching to form a pattern.SELECTED DRAWING: None

The invention discloses an antireflection film, a preparation method thereof and an optical device, and relates to the technical field of optics, the method comprises the steps that a composite material film layer is deposited on a substrate, the composite material film layer comprises a first material and a second material, and the etching rate of the first material is different from that of the second material during wet etching or dry etching; performing wet etching or dry etching on the composite material film layer to obtain a porous film layer; and sequentially carrying out cleaning treatment and drying treatment on the porous membrane layer. According to the anti-reflection film, the preparation method thereof and the optical device, the anti-reflection film of a porous structure is prepared by combining a coating technology commonly used in the industry and laboratories with a wet or dry etching method, equipment hardware does not need to be transformed, and the anti-reflection film is efficient and low in cost.