29 results about "Multiple patterning" patented technology

The invention discloses a shape perception optical proximity effect correction method and device, a storage medium and electronic equipment, and the method comprises the steps: obtaining an original design layout; performing CMP simulation on the original design layout to generate wafer morphology data; constructing a coupling optical model based on the EUV three-dimensional mask model and the wafer morphology data; performing layout decomposition on the design layout according to a multi-patterning process rule to obtain at least two mask plate patterns; a coupling optical model is adopted to carry out collaborative morphology perception optical proximity effect correction on the at least two mask plate graphs, and at least two corrected mask plate graphs are obtained; wherein when the current mask pattern is corrected, the adopted optical proximity environment comprises a historical mask correction result generated based on the coupling optical model. According to the invention, the imaging precision of advanced process nodes can be improved.

Disclosed are methods and apparatuses for performing spacer on spacer multiple patterning schemes using an exhumable first spacer material and a complementary second spacer material. Certain embodiments involve using a tin oxide spacer material for one of the spacer materials in spacer on spacer self aligned multiple patterning.

Various embodiments herein relate to techniques for depositing photoresist material on a substrate. For example, the tin techniques may involve providing the substrate in a reaction chamber; providing a first and second reactant to the reaction chamber, where the first reactant is an organo-metallic precursor having a formula of M1aR1bL1c, where: M1 is a metal having a high patterning radiation-absorption cross-section, R1 is an organic group that survives the reaction between the first reactant and the second reactant and is cleavable from M1 under exposure to patterning radiation, L1 is a ligand, ion, or other moiety that reacts with the second reactant, a≥1, b≥1, and c≥1, and where at least one of the following conditions is satisfied: the photoresist material comprises two or more high-patterning radiation absorbing elements, and / or the photoresist material comprises a composition gradient along a thickness of the photoresist material.

The application discloses a topography-aware optical proximity correction method and device, a storage medium and an electronic device. The topography-aware optical proximity correction method comprises the following steps: obtaining an original design layout; performing CMP simulation on the original design layout to generate wafer topography data; constructing a coupled optical model based on an EUV three-dimensional mask model and the wafer topography data; decomposing the layout of the design layout according to multi-graphic patterning process rules to obtain at least two mask layout; and performing collaborative topography-aware optical proximity correction on the at least two mask layout by using the coupled optical model to obtain at least two corrected mask layout; wherein when the current mask layout is corrected, the optical proximity environment used includes historical mask correction results generated based on the coupled optical model. The application can improve the imaging accuracy of advanced process nodes.

Methods of forming structures suitable for a multiple patterning process are disclosed. Exemplary methods include forming a material overlying the substrate by providing a silicon precursor to the reaction chamber for a silicon precursor pulse period providing one or more of a nitrogen reactant and an oxygen reactant to the reaction chamber for a reactant pulse period, providing an inert gas to the reaction chamber for an inert gas pulse period, and providing a plasma power to form a plasma within the reaction chamber for a plasma pulse period. The inert gas can be provided during the plasma period and / or the plasma power can be pulsed to mitigate any damage to an underlying layer, while providing desired properties of the material layer.

Three-dimensional (3D) NAND memory devices and methods are provided. In one aspect, a fabrication method includes forming a conductor / insulator stack over a substrate, configuring memory cells through the conductor / insulator stack, forming a conductive layer, removing a portion of the conductive layer to form an opening in the conductive layer, depositing a dielectric material in a space of the opening, and forming an airgap in the space.

The invention provides a self-aligned multi-pattern forming method and a semiconductor device, and the method comprises the steps: providing a semiconductor device which comprises a stacked structure, a patterned first mandrel layer and a patterned first mask layer which are sequentially arranged from bottom to top, by-products are deposited on the side wall surface of the patterned first core shaft layer and the side wall surface and the top surface of the patterned first mask layer; in the byproduct removal step, in the atmosphere of inert gases, the byproducts are stripped through physical bombardment, and the inert gases comprise helium and argon; and an acid pickling step: performing acid pickling on the by-product in an acid solution until the side wall surface of the patterned first mandrel layer and the side wall surface and the top surface of the patterned first mask layer are exposed. According to the invention, the side wall of the patterned first core shaft layer can be prevented from being etched by a chemical reaction, so that the integrity of the side wall of the patterned first core shaft layer is kept, and the accuracy of subsequent pattern transmission is ensured.

In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

The present disclosure provides a method for forming a monitoring pattern and a method for monitoring a pattern, the method for forming a monitoring pattern comprising: providing a material layer to be etched, sequentially forming a preset number of hard mask layers on the surface of the material layer to be etched, the last formed hard mask layer comprising a plurality of shafts, at least one shaft having a length in a direction parallel to other shafts different from the lengths of the other shafts; forming a sidewall around the patterned hard mask layer, then removing the patterned hard mask layer, etching the hard mask layer adjacent to the bottom of the sidewall with the sidewall as a mask, then removing the sidewall to form a new patterned hard mask layer; repeating the above process of forming a patterned hard mask layer several times to form a monitoring pattern on the hard mask layer adjacent to the material layer to be etched, then transferring the monitoring pattern to the material layer to be etched. The method can monitor each process of a multi-pattern technology and improve the yield.

The invention provides a self-aligned multi-patterning method, which comprises the following steps of: forming a side wall layer on the side wall of a mandrel layer, forming a protective layer on the surface of a material layer to be etched, and exposing a part of a second side surface of the side wall layer and the top of the mandrel layer; removing part of the core shaft layer to expose part of the first side surface of the side wall layer; carrying out smoothing treatment on the exposed side wall layer; removing the core shaft layer and the protective layer; and etching the to-be-etched material layer by taking the side wall layer as a mask to form an etching layer. According to the method, the morphology asymmetry of the side wall is reduced through the protective layer, the loss of the to-be-etched material layer is protected in the process of removing the mandrel, the asymmetry of the side wall structure is further reduced by etching and correcting the top of the side wall layer, the height difference between the to-be-etched material layer on the left and right sides of the side wall can be reduced in the process of removing the protective layer, and the yield of the to-be-etched material layer is improved. Therefore, the morphology and size uniformity of the etching layer is improved, and the device performance is improved. In addition, the CD correction material layer is formed on the etching layer, so that the morphology and the size of the etching layer are further optimized, and the performance of the device is further enhanced.

A method comprising the steps of: a. forming a first pattern of regularly spaced apart templates (4) on a layer (3) to be patterned by self-aligned multiple patterning, b. subsequently forming hard mask spacers (5) on the sidewalls of said templates (4), thereby forming a second pattern formed by assemblies (4, 5) comprising a template (4) and a hard mask spacer (5) on its sidewall, and c. subsequently etching said second pattern in the layer (3) to be patterned.

A method of forming a device includes forming a patterned resist layer over a substrate using an extreme ultraviolet (EUV) lithography process. The method includes forming a mandrel in a plasma processing chamber by selectively depositing a mandrel material over the patterned resist layer, the mandrel including the patterned resist layer and the mandrel material.

IC interconnect structures including subtractively patterned features. Feature ends may be defined through multiple patterning of multiple cap materials for reduced misregistration. Subtractively patterned features may be lines integrated with damascene vias or with subtractively patterned vias, or may be vias integrated with damascene lines or with subtractively patterned lines. Subtractively patterned vias may be deposited as part of a planar metal layer and defined currently with interconnect lines. Subtractively patterned features may be integrated with air gap isolation structures. Subtractively patterned features may be include a barrier material on the bottom, top, or sidewall. A bottom barrier of a subtractively patterned features may be deposited with an area selective technique to be absent from an underlying interconnect feature. A barrier of a subtractively patterned feature may comprise graphene or a chalcogenide of a metal in the feature or in a seed layer.

A computer-implemented method for modeling mandrel tolerance in a design of semiconductor device. The method includes receiving a multiple patterning (MPT) process design kit (PDK) for the semiconductor device. The PDK includes design parameters of a plurality of transistors that form at least part of the semiconductor device and a plurality of fins associated with each of the plurality of transistors. The method includes generating a fin index identifying each of the plurality of fins and grouping the fin indexes of the plurality of fins into two or more groups based on a type of fin. The method further includes identifying a mandrel mismatch in response to determining that a first fin index associated with a first transistor belongs to a group that is different from a second fin index associated with a second transistor. The method also includes determining a device parameter based on the mandrel mismatch identified.

The utility model provides a packaging structure, comprising a first crystal seed layer provided with a plurality of patterned first grooves; the first electroplating copper layer is arranged on the first crystal seed layer, the first electroplating copper layer comprises a first upper surface and a first lower surface opposite to the first upper surface, and the first lower surface is provided with a plurality of first protruding parts corresponding to the first grooves. The utility model aims to provide a packaging structure so as to at least improve the thickness uniformity of an electroplating copper layer.

A method of forming a device includes forming a patterned resist layer over a substrate using an extreme ultraviolet (EUV) lithography process. The method includes forming a mandrel in a plasma processing chamber by selectively depositing a mandrel material over the patterned resist layer, the mandrel comprising the patterned resist layer and the mandrel material.

The disclosure relates to the manufacture of semiconductor devices, especially to methods and processing assemblies for forming a patterned structure on a substrate. The methods comprise providing the substrate comprising a first structure into a reaction chamber, wherein a surface of the first structure comprises a first material and the substrate comprises a second material, and selectively depositing a conformal passivation layer on the first material relative to the second material to cover the first structure, and selectively depositing an etch-stop layer on the second material relative to the passivation layer. In some embodiments, a multiple patterning or a tone reversal of a pattern may be performed using the methods and deposition assemblies of the disclosure.

The invention provides a self-aligned multiple pattern forming method and a semiconductor device, and the method comprises the steps: providing a semiconductor device which comprises a stacked structure, a graphical first mandrel layer and a graphical first mask layer which are sequentially arranged from bottom to top; performing deposition on the laminated structure to form a first side wall layer; depositing at the bottom of the first side wall layer to form a first polymer layer covering the bottom and the side part of the first side wall layer; etching the top of the first side wall layer; and removing the first polymer layer to expose the bottom and the side part of the first side wall layer. According to the invention, the first polymer layer can protect the side part of the first side wall layer, so that only the top of the first side wall layer is etched in the step of etching the top of the first side wall in the subsequent execution, the integrity and symmetry of the side part of the first side wall layer are maintained, and the accuracy of subsequent pattern transmission is facilitated.

Structures with features formed by self-aligned double patterning and methods of self-aligned multiple patterning. The structure comprises a first field-effect transistor including a first gate and a first protrusion projecting laterally from the first gate, and a second field-effect transistor including a second gate and a second protrusion projecting laterally from the second gate. The second gate and the second protrusion are spaced in a lateral direction from the first gate and the first protrusion. The structure further comprises a gate contact connecting the first protrusion of the first gate to the second protrusion the second gate.

The embodiment of the invention relates to a multi-patterning method, electronic equipment and a computer readable storage medium. The method comprises the following steps: generating a first mask based on a design layout, wherein leads of a metal layer in the design layout are arranged according to a minimum design rule; a second mask is generated based on the design layout, the second mask comprises an expansion area generated by expanding each lead by a first preset distance, and the expansion area comprises a continuous area so that the leads in the corresponding areas in the design layout can be covered; and respectively exposing the first mask and the second mask to form light intensity distribution used for generating a photoetching groove corresponding to the lead in the photoresist. According to the scheme disclosed by the invention, a larger process window, higher overlay precision and good line end performance can be realized.

Multiple patterning approaches using radiation sensitive organometallic materials is described. In particular, multiple patterning approaches can be used to provide distinct multiple patterns of organometallic material on a hardmask or other substrate through a sequential approach that leads to a final pattern. The multiple patterning approach may proceed via sequential lithography steps with multiple organometallic layers and may involve a hardbake freezing after development of each pattern. Use of an organometallic resist with dual tone properties to perform pattern cutting and multiple patterning of a single organometallic layer are described. Corresponding structures are also described.

A system and method for determining one or more characteristic parameters of a portion of a pattern on a substrate are described. Pattern information for a pattern on the substrate is received. The pattern on the substrate has a first portion and a second portion. The first portion (404A, 406B) of the pattern is blocked (400, 402) based on the pattern information, for example using a geometric block mask (408, 410), such that the second portion of the pattern remains unblocked. One or more parameters of the unblocked second portion of the pattern are determined. In some embodiments, the first portion and the second portion of the pattern correspond to different exposures in a semiconductor lithography process. The semiconductor lithography process may be a multiple patterning technique, such as a double patterning process, a triple patterning process, or a spaced double patterning process.

The invention discloses a multi-fold periscopic prism capable of realizing high-power optical zooming and a processing method of the multi-fold periscopic prism. According to the invention, a semiconductor manufacturing process is adopted, high-precision alignment of a plurality of patterned film layers can be realized by adopting exposure to recognize the same mark reference, the highest alignment precision can reach a hundred-nanometer level, and the alignment precision of the patterned film layer of a product processed by a conventional gluing equipment CCD recognition mode is about 20 microns; the method can effectively avoid the loss of luminous flux in the prism light transmission process caused by the deviation of a graphical film layer and the influence of stray light abnormity caused by the deviation on the imaging quality, can realize multi-fold prism processing, is applied to a mobile phone, can form an ultra-long light path in a narrow space in a folding manner, and has a wide application prospect. The ultra-high-magnification optical zoom and excellent image quality can be realized, and meanwhile, the relative lightness and thinness of a machine body are kept.

In accordance with embodiments, a memory array is formed with a multiple patterning process. In embodiments a first trench is formed within a multiple layer stack and a first conductive material is deposited into the first trench. After the depositing the first conductive material, a second trench is formed within the multiple layer stack, and a second conductive material is deposited into the second trench. The first conductive material and the second conductive material are etched.

The disclosure relates to the manufacture of semiconductor devices, especially to methods and processing assemblies for forming a patterned structure on a substrate. The methods comprise providing the substrate comprising a first structure into a reaction chamber, wherein a surface of the first structure comprises a first material and the substrate comprises a second material, and selectively depositing a conformal passivation layer on the first material relative to the second material to cover the first structure, and selectively depositing an etch-stop layer on the second material relative to the passivation layer. In some embodiments, a multiple patterning or a tone reversal of a pattern may be performed using the methods and deposition assemblies of the disclosure.

This invention relates to a method for multi-patterning a substrate. A method for providing etch selectivity in a substrate processing is disclosed. More specifically, a plasma treatment of multiple exposed structures comprising different materials is provided. The plasma treatment preferentially enhances the etch selectivity among at least two of the exposed structures. In one embodiment, multiple exposed structures are used as part of a multi-patterning substrate process. In one embodiment, the exposed structures may include an organic planarization layer and a spin-coated metal layer. The plasma treatment may include a plasma formed using nitrogen and hydrogen and the emission of vacuum ultraviolet (VUV) wavelength radiation from such plasma.

A method of microfabrication is provided. The method includes providing a wafer having a patterned layer formed thereon. The patterned layer includes a mandrel structure having a first sidewall and a second sidewall on opposing sides of the mandrel structure. A first spacer is formed on the first sidewall of the mandrel structure by asymmetric deposition, asymmetric etch or a combination thereof. A second spacer is formed on the second sidewall of the mandrel structure so that the first spacer, the mandrel structure and the second spacer form a three-material structure. A first etch mask is formed over the patterned layer. The first etch mask includes a first opening that exposes the three-material structure. One or two materials of the three-material structure are selectively removed via the first opening.

Various embodiments herein relate to techniques for depositing photoresist material on a substrate. For example, the techniques may involve providing the substrate in a reaction chamber; providing a first and second reactant to the reaction chamber, where the first reactant is an organo-metallic precursor having a formula of M1aR1bL1c, where: M1 is a metal having a high patterning radiation-absorption cross-section, R1 is an organic group that survives the reaction between the first reactant and the second reactant and is cleavable from M1 under exposure to patterning radiation, L1 is a ligand, ion, or other moiety that reacts with the second reactant, a≥1, b≥1, and c≥1, and where at least one of the following conditions is satisfied: the photoresist material comprises two or more high-patterning radiation absorbing elements, and / or the photoresist material comprises a composition gradient along a thickness of the photoresist material.

The application provides a multiple patterning and semiconductor device manufacturing method, which comprises the following steps: providing a semiconductor substrate, forming a hard mask layer and a first patterning glue layer on the surface of the semiconductor substrate in sequence; depositing the first patterning glue layer by using a deposition technology to form a first deposition layer; removing the top part of the first deposition layer covered by the top part of the first patterning glue layer by using a top removal technology; removing the first patterning glue layer by using a glue removal technology to form a non-usable multiple pattern to be molded; and processing the non-usable multiple pattern to be molded by using a pressurized casting technology to form a usable multiple patterning glue layer. Therefore, the cost of photolithography and etching processes can be saved, and a semiconductor device with smaller line width can be finally manufactured.