155 results about "Multiple patterning" patented technology

A method of forming spacers for spacer-defined multiple pattering (SDMP), includes: depositing a pattern transfer film by PEALD on the entire patterned surface of a template using halogenated silane as a precursor and nitrogen as a reactant at a temperature of 200° C. or less, which pattern transfer film is a silicon nitride film; dry-etching the template using a fluorocarbon as an etchant, and thereby selectively removing a portion of the pattern transfer film formed on a top of a core material and a horizontal portion of the pattern transfer film while leaving the core material and a vertical portion of the pattern transfer film as a vertical spacer, wherein a top of the vertical spacer is substantially flat; and dry-etching the core material, whereby the template has a surface patterned by the vertical spacer on a underlying layer.

A method of forming vertical spacers for spacer-defined multiple patterning, includes: depositing a first conformal pattern-transfer film having a first film stress, and continuously depositing a second conformal pattern-transfer film having a second film stress on a template; dry-etching the template except for a core material and a vertical portion of the first and second pattern-transfer films to form vertical spacers; and dry-etching the core material, forming a vacant space between the vertical spacers, wherein by adjusting the difference in film stress between the first and second pattern-transfer films, the leaning angle of the spacers is adjusted.

Methods and systems for evaluating the performance of multiple patterning processes are presented. Patterned structures are measured and one or more parameter values characterizing geometric errors induced by the multiple patterning process are determined. In some examples, a single patterned target and a multiple patterned target are measured, the collected data fit to a combined measurement model, and the value of a structural parameter indicative of a geometric error induced by the multiple patterning process is determined based on the fit. In some other examples, light having a diffraction order different from zero is collected and analyzed to determine the value of a structural parameter that is indicative of a geometric error induced by a multiple patterning process. In some embodiments, a single diffraction order different from zero is collected. In some examples, a metrology target is designed to enhance light diffracted at an order different from zero.

Method for nanopatterning of inorganic materials, such as ceramic (e.g. metal oxide) materials, and organic materials, such as polymer materials, on a variety of substrates to form nanopatterns and/or nanostructures with control of dimensions and location, all without the need for etching the materials and without the need for re-alignment between multiple patterning steps in forming nanostructures, such as heterostructures comprising multiple materials. The method involves patterning a resist-coated substrate using electron beam lithography, removing a portion of the resist to provide a patterned resist-coated substrate, and spin coating the patterned resist-coated substrate with a liquid precursor, such as a sol precursor, of the inorganic or organic material. The remaining resist is removed and the spin coated substrate is heated at an elevated temperature to crystallize the deposited precursor material.

The invention relates to a self-aligned multi-patterning mask layer and a formation method thereof. The formation method comprises the following steps that: a semiconductor substrate is provided and a to-be-etched material layer is formed at the surface of the semiconductor substrate; a sacrificial material layer is formed at the surface of the to-be-etched material layer; etching is carried out on the sacrificial material layer to form a sacrificial layer, wherein the dimension of the portion, approaching the to-be-etched material layer, of the sacrificial layer is smaller than that of the portion, far away from the to-be-etched material layer, of the sacrificial layer; and a side wall is formed at the surface of the side wall of the sacrificial layer, wherein the portions of the two sides of the side wall are inclined towards the middle portion of the side wall from a position at the surface of the to-be-etched material layer to a position far away from the surface of the to-be-etched material layer. Because the portions of the two sides of the side wall are inclined towards the middle portion of the side wall and the profile shapes of the portions of the two sides of the side wall are identical with each other, the shapes of side walls of the to-be-etched material layer formed by etching by using the side wall as the mask subsequently are identical, so that the electrical performance of the semiconductor device that is formed subsequently is not influenced.

Methods of multiple patterning of low-k dielectric films are described. For example, a method includes forming and patterning a first mask layer above a low-k dielectric layer, the low-k dielectric layer disposed above a substrate. A second mask layer is formed and patterned above the first mask layer. A pattern of the second mask layer is transferred at least partially into the low-k dielectric layer by modifying first exposed portions of the low-k dielectric layer with a first plasma process and removing the modified portions of the low-k dielectric layer. Subsequently, a pattern of the first mask layer is transferred at least partially into the low-k dielectric layer by modifying second exposed portions of the low-k dielectric layer with a second plasma process and removing the modified portions of the low-k dielectric layer.

Self-aligned spacer multiple patterning method are provided. The methods involve alkaline treatment of photoresist patterns and allow for the formation of high density resist patterns. The methods find particular applicability in semiconductor device manufacture.

One embodiment provides a method for determining mask layouts. During operation, the system can receive a design intent. Next, the system can determine a set of critical edges in the design layout, and select a first edge and a second edge. The system can then determine a first trench and a second trench using the first edge and the second edge, respectively. Note that an edge of the first trench may substantially overlap with the first edge, and an edge of the second trench may substantially overlap with the second edge. Next, the system may assign the first trench and the second trench to the first mask layout and the second mask layout, respectively. The system can then increase the first trench and the second trench, thereby improving pattern fidelity. The resulting mask layouts may be used in a double patterning process.

One illustrative method disclosed herein involves identifying an overall target pattern comprised of at least one hole-type feature, decomposing the overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern and the second sub-target pattern each comprise at least one common hole-type feature, generating a first set of mask data information corresponding to the first sub-target pattern, and generating a second set of mask data information corresponding to the second sub-target pattern.

A computer-implemented method for validating a design is disclosed. The method includes receiving, with the computer, the design, where the design is printable using a multiple-patterning process when the computer is invoked, and where the design includes a plurality of shapes and at least one conflict preventing decomposition of the design into a plurality of multiple-patterning masks. The method also includes forming a subset of the shapes, the subset including the shapes associated with the at least one conflict, categorizing each of the shapes of the subset into one of a plurality of topology types generating one or more stitch candidate solutions for each of the plurality of topology types, and decomposing the design into a plurality of masks.

Methods and systems for evaluating the performance of multiple patterning processes are presented. Patterned structures are measured and one or more parameter values characterizing geometric errors induced by the multiple patterning process are determined. In some examples, a primary, multiple patterned target is measured and a value of a parameter of interest is directly determined from the measured data by a Signal Response Metrology (SRM) measurement model. In some other examples, a primary, multiple patterned target and an assist target are measured and a value of a parameter of interest is directly determined from the measured data by a Signal Response Metrology (SRM) measurement model. In some other examples, a primary, multiple patterned target is measured at different process steps and a value of a parameter of interest is directly determined from the measured data by a Signal Response Metrology (SRM) measurement model.

A method for providing temporary measurement targets during a multiple patterning process which can be removed in the completion of the process. The metrology target is defined in either the first or the second exposure of a multiple exposure process and whether or not it is temporary or made permanent is selected according to whether or not the area of the target is covered or cleared out in the other exposure. The use of temporary targets reduces the amount of space on the substrate that must be devoted to targets.

Embodiments herein provide apparatus and methods for performing a deposition and a patterning process on a spacer layer with good profile control in multiple patterning processes. In one embodiment, a method for depositing and patterning a spacer layer during a multiple patterning process includes conformally forming a spacer layer on an outer surface of a patterned structure disposed on a substrate, wherein the patterned structure has a first group of openings defined therebetween, selectively treating a first portion of the spacer layer formed on the substrate without treating a second portion of the spacer layer, and selectively removing the treated first portion of the spacer layer.

Methods and systems for measuring process induced errors in a multiple patterning semiconductor fabrication process based on measurements of a specimen and process information from one or more previous process steps employed to fabricate the specimen are presented herein. A metrology tool is employed after a number of process steps have been executed. The metrology tool measures structural parameters of interest of metrology targets on the wafer based on measured signals and process information, and communicates correctable process parameter values to one or more process tools involved in the previous process steps. When executed by the appropriate process tool, the correctable process parameter values reduce process induced errors in the geometry of the structures fabricated by the process flow. In another aspect, multiple metrology tools are used to control a fabrication process in combination with process information from one or more process steps in the process flow.

An integrated circuit memory comprises a set of lines each line having parallel X direction line portions in a first region and Y direction line portions in a second region. The second region is offset from the first region. The lengths of the X direction line portions are substantially longer than the lengths of the Y direction line portions. The X direction and Y direction line portions have respective first and second pitches with the second pitch being at least 3 times larger than the first pitch. Contact pickup areas are at the Y direction line portions. In some examples, the lines comprise word lines or bit lines. The memory can be created using multiple patterning methods to create lines of material and then the parallel X direction line portions and parallel Y direction line portions.

Some aspects of the present disclosure provide for a method of automatically balancing mask misalignment for multiple patterning layers to minimize the consequences of mask misalignment. In some embodiments, the method defines a routing grid for one or more double patterning layers within an IC layout. The routing grid has a plurality of vertical grid lines extending along a first direction and a plurality of horizontal grid lines extending along a second, orthogonal direction. Alternating lines of the routing grid in a given direction (e.g., the horizontal and vertical direction) are assigned different colors. Shapes on the double patterning layers are then routed along the routing grid in a manner that alternates between different colored grid lines. By routing in such a manner, variations in capacitive coupling caused by mask misalignment are reduced.

An integrated circuit pattern comprises a set of lines of material having X and Y direction portions. The X and Y direction portions have first and second pitches, the second pitch being larger, such as at least 3 times larger, than the first pitch. The X direction portions are parallel and the Y direction portions are parallel. The end regions of the Y direction portions comprise main line portions and offset portions. The offset portions comprise offset elements spaced apart from and electrically connected to the main line portions. The offset portions define contact areas for subsequent pattern transferring procedures. A multiple patterning method, for use during integrated circuit processing procedures, provides contact areas for subsequent pattern transferring procedures.

Novel methods of double patterning a photosensitive resin composition are provided. The methods involve applying the photosensitive composition to a substrate and thermally crosslinking the composition. The crosslinked layer can be used to provide reflection control. Upon exposure to light, the crosslinked polymer (or oligomer or monomer) in the compositions will decrosslink, rendering the light-exposed portions soluble in typical photoresist developing solutions (e.g., alkaline developers). Advantageously, the crosslinked portions of the composition remain insoluble in the solvent used to form the photosensitive composition. As a result, the coating, lithographic, and or developing steps can be repeated multiple times in varying order, depending upon the particular process, without destroying earlier-formed patterns.

The invention is directed to a method for patterning a material layer. The method comprises steps of forming a mask layer on the material layer. A multiple patterning process is performed on the mask layer for transferring at least a first pattern from a first photomask through a first photoresist and a second pattern from a second photomask from a second photoresist layer into the mask layer without performing any etching process. The mask layer exposes a portion of the material layer and the mask layer is patterned at the time that the first photoresist layer and the second photoresist layer are developed respectively. An etching process is performed to pattern the material layer by using the mask layer as an etching mask.

A method and system for evaluating a lithographic pattern obtained using multiple-patterning lithographic processing are presented. In one aspect, the method includes aligning a target design with a lithographic pattern. The target design may comprise a first design and a second design. The method further comprises identifying in the lithographic pattern a stitching region based on a region of overlap between the first design and the second design. The method further comprises determining for the identified stitching region whether a predetermined criterion is fulfilled. In some embodiments, determining whether a predetermined criterion is fulfilled may comprise determining a line or trench minimum width. Alternately or additionally, determining whether a predetermined criterion is fulfilled may comprise determining a stitching metric for the identified stitching region, and evaluating whether or not the stitching metric fulfills the predetermined criterion.

A system and method for providing a cell layout for multiple patterning technology is provided. An area to be patterned is divided into alternating sites corresponding to the various masks. During a layout process, sites located along a boundary of a cell are limited to having patterns in the mask associated with the boundary site. When placed, the individual cells are arranged such that the adjoining cells alternate the sites allocated to the various masks. In this manner, the designer knows when designing each individual cell that the mask pattern for one cell will be too close to the mask pattern for an adjoining cell.