590 results about "Integrated circuit design" patented technology

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention discloses an ultrahigh-precision low-noise band-gap reference circuit, and relates to the technical field of integrated circuit design, the ultrahigh-precision low-noise band-gap reference circuit comprises a starting turn-off circuit, a reference core circuit, a high-order temperature compensation circuit and a digital trimming circuit, the starting turn-off circuit is connected with the reference core circuit, and the high-order temperature compensation circuit is connected with the digital trimming circuit through a Brokaw type band-gap reference topological structure. Accurate compensation of the voltage is achieved through deep negative feedback of the operational amplifier and a high-order temperature compensation circuit, and the temperature drift of the reference voltage is as low as 0.5-2 ppm / DEG C (-40 DEG C to 130 DEG C) and is increased by 5-10 times compared with a traditional band-gap reference (5-10 ppm / DEG C). The power consumption of the system can be saved by turning off the circuit when the circuit is not used, meanwhile, the digital trimming module is added to replace laser trimming in traditional engineering, the upper limit of the trimming range is improved, high-order temperature compensation and the digital trimming circuit are introduced, the precision of output voltage is improved, different devices are replaced, and the noise of the circuit is reduced. The problems that a traditional high-voltage band-gap reference temperature coefficient is high and noise is large are solved.

The invention discloses a code generation method and system based on multi-objective reinforcement learning, and belongs to the technical field of digital integrated circuit design, and the method comprises the following steps: S1, generating an SFT training data set; s2, generating an MORL data set; s3, performing supervision and fine tuning on the model by taking the SFT training data set as input, so that the model masters the basic RTL code generation capability; s4, taking the MORL data set as input to train the model after supervision and fine tuning in the S3, and realizing multi-objective optimization; and S5, according to a user demand, describing a multi-target constraint through vector rewards, screening non-dominated candidate codes by using Pareto optimization to obtain an optimal RTL code, and outputting the optimal RTL code, vector reward details and a PPA equilibrium curve. According to the method and the system, basic constraints are met, and meanwhile generation of RTL codes with PPA indexes capable of being customized according to requirements is achieved.

The invention belongs to the technical field of analog integrated circuit design and memory read-write, and provides a multi-valued RRAM read-write circuit with a write-and-read function. The multi-valued RRAM read-write circuit is a multi-port device capable of performing read-write simultaneously, in write operation, a low dropout regulator is utilized to provide voltage for the RRAM circuit and the standard resistance circuit, mirror current is generated, the resistance value of the RRAM is set to be the total resistance of the standard resistance circuit, an operational amplifier is connected into the circuit through a CMOS switch, and feedback is formed to stabilize the voltage at the two ends of the RRAM; and in the read operation, the CMOS switch is used for disconnecting the operational amplifier, and the voltage at the two ends of the RRAM device is directly read. Compared with an existing multi-valued read-write circuit, the multi-valued RRAM read-write circuit has the advantages that write-and-read multi-valued RRAM read-write is realized, and meanwhile, the read-write circuit is not separated, so that the write-in speed is increased, and the area of the read-write circuit is saved.

The invention relates to the technical field of integrated circuit design, computer system structures and embedded systems, in particular to a high-real-time interrupt management system and method based on an RISC-V. The system comprises an improved platform-level interrupt controller and an optimized processor internal interrupt processing unit. The system and the method are in tight coupling cooperative work through a special interruption field interface and a system bus, and the system further comprises a core local interrupter, an SRAM, an APB bus matrix and other components. The improved platform-level interrupt controller is responsible for sampling, gating, arbitration, flow control and direct memory access transmission of external interrupt, and a plurality of functional modules are arranged in the improved platform-level interrupt controller; an interrupt processing unit in the processor is responsible for hardware handshake, vector jump, nested control and tail biting mechanism implementation. Through hardware field management, multi-level priority arbitration, hardware nesting and tail biting mechanisms, delay and overhead caused by software intervention in a traditional architecture are eliminated, nanosecond response is achieved, the system throughput rate is increased, the software development threshold is lowered, and the method is suitable for strong real-time scenes.

The invention belongs to the technical field of analog integrated circuit design automation, and discloses an analog integrated circuit cross-process performance prediction method and system based on Transform transfer learning, and the method comprises the steps: 1, carrying out the preprocessing of analog integrated circuit sample data; 2, serializing the sample data according to a preset sequence, mapping each parameter into vector representation, adding a global abstract vector, and splicing according to a fixed sequence to form an input sequence; 3, encoding the input sequence to obtain an output sequence; 4, inputting the global features into the regression head network, and outputting a performance index prediction value; 5, training is carried out, network parameters obtained through pre-training of the source technology are migrated to the target technology, fine adjustment is carried out on part of network parameters of a target technology data set, and cross-technology performance prediction is achieved; and 6, performing forward reasoning on operational amplifier design parameters under a given target process according to the steps 2-4 to obtain a performance prediction result. The method improves the stability and efficiency of performance prediction.

The invention discloses an integrated circuit design Verilog code generation method and device based on a large language model, equipment and a medium, and relates to the technical field of computers, and the method comprises the steps that semantic analysis is conducted on an input language of an integrated circuit user side through the large language model, and a target constraint set is determined based on an obtained performance index set and through a regular expression; a candidate architecture scheme is generated by utilizing thinking chain technology reasoning, the candidate architecture scheme is predicted by utilizing an XGBoost regression model, and a target architecture scheme is determined based on an index prediction result and the candidate architecture scheme by utilizing a non-dominated sorting genetic algorithm; and determining an initial Verilog code based on the target architecture scheme and a preset code template library, and performing code style conversion on the initial Verilog code based on a code style feature corresponding to the integrated circuit user side to obtain a target Verilog code. And the efficiency and availability of integrated circuit design are improved.

The invention provides a code processing method and device of an integrated circuit, electronic equipment and a storage medium. The method comprises the steps that a source code is obtained, the source code comprises parameter information of a sub-module in the integrated circuit, and the source code is a register transfer level code; constructing a structured encapsulation unit tree based on the source code; packaging the structured packaging unit tree according to a high-level hardware description language to obtain a structured object; instantiating the structured object to obtain a hardware description language module; and in response to the received connection instruction, code generation is performed based on the connection instruction and the hardware description language module to obtain a connection code, the connection instruction comprises a connection relationship between the sub-modules in the integrated circuit, the connection code indicates a signal transmission path between the sub-modules in the integrated circuit, and the connection code is a hardware description language code. According to the invention, the connection efficiency of signal transmission paths between modules in an integrated circuit design can be improved.

The invention provides a process control method and device for integrated circuit design, equipment and a storage medium, and belongs to the technical field of integrated circuit design, and the method comprises the steps: determining execution weights of a plurality of verification tasks in a current design stage according to a preset association rule; and based on the execution weight, screening out a target verification task from the plurality of verification tasks, and marking the target verification task as an enabled state. The corresponding most concerned target verification task can be determined in different design stages, and the number of times of operation of invalid EDA tools is reduced.

The invention provides an electric wiring component, a consumable chip and an ink box, and relates to the technical field of integrated circuit manufacturing and integrated circuit design. The electrical wiring member includes a plurality of contact points for contacting a contact pin of the image forming apparatus; the plurality of contact points comprise a plurality of corner contact points and a plurality of non-corner contact points; at least two corner contacts are suspended contacts, and the suspended contacts are in contact with the contact pins but are not electrically connected with the printing head chip; according to the invention, at least two corner contacts are suspended contacts, so that the number of corner contacts electrically connected with the imaging equipment is reduced, and the problems that the corner contacts cannot be normally and electrically connected with corresponding contact pins due to pollution, so that the contact between the consumable chip side and the terminal of the imaging equipment main body side is insufficient, and the service life of the imaging equipment is prolonged are solved. And the consumable chip and the imaging equipment cannot be in normal contact and electrical connection.

Embodiments of the present disclosure provide enhanced systems and methods for predicting optimal design flow parameters for optimized output targets for physical design synthesis of a given IC design. A Variational Autoencoder (VAE) along with a regression network are trained using a dataset comprising synthesis design construction flows from historical IC designs to provide a training data representation of the dataset constrained to a latent space of the VAE. The system generates feature vectors based on the training data representation of the dataset and updates the feature vectors with initial design characteristics of the given IC design. The system iteratively performs an input gradient search of the updated feature vectors to optimize an objective function of the design targets to identify locally optimal design parameters. The system identifies globally optimal design flow parameters for optimized design targets based on locally optimal design parameters.

The invention relates to the field of integrated circuit design and photoetching manufacturing simulation, in particular to a layout violation repair guidance method, layout violation repair guidance equipment, a medium and a product. The layout violation repair guidance method comprises the following steps: inputting an initial layout and a physical design rule to be checked, dividing the initial layout into a plurality of layout blocks, and carrying out physical design rule checking on each layout block; if the design rule violation exists, analyzing graphic attributes around the violation to obtain the cause of the violation; and outputting violation repair guidance information according to the violation cause. And outputting violation repair guidance information of each layout block until all the layout blocks complete rule check. Wherein the graph attributes comprise fixed graphs, access paths of pins and ports, and a wiring network. The electronic equipment, the computer storage medium and the computer program product have the same beneficial effects as the layout violation repair guidance method.

The invention discloses a memory generation method, electronic equipment and a storage medium, and relates to the technical field of integrated circuit design, and the method comprises the following steps: obtaining basic parameters of a memory; converting the basic parameters into compiler commands; determining a splicing strategy for the physical memory according to the data width, the address depth and the size of the physical memory; a logical memory is generated based on the compiler command and the stitching policy. According to the method, the basic parameters are converted into the compiler commands, and dynamic mapping of the parameters and the compiler commands is realized, so that the basic information, the function information and the performance information of the memory are unified and automatically read, the logic memory is automatically generated, the method has universality, and the generation efficiency of the memory is improved.

An emulator system and a method for emulating functionalities of an integrated circuit design are disclosed. In one aspect, the system includes a plurality of verification components each comprising circuitry configured to perform transactions with at least another verification component. The system can include a plurality of proxies, each executing on a processor and corresponding to a respective one of the verification components. The system can include a switch that is communicatively coupled with the proxies, the switch dynamically configurable to, in a first time duration, operate with a first subset of the proxies to enable a first transaction between a functional module of the design and a first verification component. The switch can be dynamically configurable to, in a second time duration, operate with a second subset of the proxies to enable a second transaction between the functional module and a second verification component.

The application provides a simulation method of a memory. The simulation method is based on: an EDA platform of integrated circuit design is used to build a front simulation key path circuit of the memory, and a front simulation net list of the memory is extracted and expanded. In a memory design layout, each global signal line is segmented, and each segment is attached to a repeated unit above it, and a post-simulation net list is extracted. Each module of the post-simulation net list is used to replace the corresponding module in the expanded front simulation net list to obtain a simplified post-simulation key path net list. The memory is simulated based on the post-simulation key path net list. The technical scheme provided by the application greatly simplifies the simulation net list for verifying the memory design while retaining the internal logic of the repeated unit, and meanwhile, the coupling effect of the internal logic of the repeated unit on the global signal is retained. In the simulation process, the net list module corresponding to the repeated unit appears only once, and the simulation speed is effectively improved.

This application relates to the field of integrated circuit design technology, and in particular to a hardware-software integrated border texture sampling system. This system implements border texture sampling through a hardware-software integration approach, supports user-defined sampling colors, and pre-stores a target texture lookup table on the software side, providing the hardware side with the target index value for the customized color. The hardware side only needs to perform target offset mapping and target address calculation to directly read the target texture data from the cache based on the target address, eliminating the need for format conversion after obtaining the texture data, thus saving hardware computing resources. Furthermore, the target texture lookup table contains texture data in multiple data formats, so the hardware side does not need to always obtain large-bit-width texture data and then convert it, but can directly obtain the texture data with the required bit width, thereby reducing the memory access bandwidth on the hardware side and improving border texture sampling efficiency.

The invention relates to a dual-core heterogeneous CMOS drive circuit of a micro spectrometer in the technical field of spectrum detection and integrated circuit design, which comprises a dual-core heterogeneous main control chip, a drive chip, an AD acquisition chip, a built-in algorithm module and a data interface module, and is characterized in that the dual-core heterogeneous main control chip comprises an ARM core and an FPGA core; the ARM core converts an instruction sent by main control equipment into a standardized control signal, the FPGA core receives the control signal output by the ARM core and generates a driving time sequence signal, and the driving chip drives the CMOS sensor to output a video signal; the AD acquisition chip is driven to carry out data acquisition on video signals, original analog signals in the video signals are converted into digital signals to obtain original data of a spectrum, the ARM core packages the original data and transmits the original data to the built-in algorithm module, and a detection result report is generated. And the ARM core transmits the original data and the detection result report back to the main control equipment through the data interface module.

The application relates to the technical field of integrated circuit design, in particular to an inverter chain circuit shielding SET pulse signals and a module packaged based on the inverter chain circuit shielding SET pulse signals. The inverter chain is constructed based on a three-stage inverter structure, which not only has the basic function of an inverter, but also has the outstanding ability of shielding SET pulse signals through reasonable circuit design, can shield voltage jump in any direction, and ensures that the output node o3 can still output with correct logic state.

The invention discloses a pulse wave signal detection-oriented transimpedance amplifier circuit with input voltage clamping and current offset functions, and relates to the technical field of integrated circuit design, the pulse wave signal detection-oriented transimpedance amplifier circuit comprises a pseudo-differential structure, a current offset module and a photosensitive diode, the pseudo-differential structure is composed of two independent operational amplifiers with double-end input and single-end output, the trans-impedance amplifier of a pseudo-differential structure composed of two independent operational amplifiers with double-end input and single-end output is used, the same voltage is connected to the same-direction input end of the trans-impedance amplifier, voltage clamping is carried out on double-end input, the differential mode precision and low-frequency stability of an input virtual site are improved, differential mode imbalance and flicker noise caused by operational amplifier mismatch are eliminated, and the stability of the trans-impedance amplifier is improved. The dynamic range of the pulse wave detection system is improved, and the pulse wave detection system has the advantages of high-precision and wide-range ambient light suppression effect, high circuit reliability, low circuit complexity, easy implementation, high loop stability, small area and low power consumption.

This invention belongs to the field of integrated circuit design technology, specifically relating to a method for optimizing integrated circuit design data. This method first constructs a "tool-layer-semantic" data acquisition architecture, integrating multi-channel parallel acquisition units to collect heterogeneous data from multiple sources. Compliance pre-verification is performed through hardware logic circuits and a verification rule base, extracting key data identifiers. A three-level incremental compression strategy based on key data priority, combined with an intelligent index integrating multi-dimensional indexes, is used for compression and storage. The stored data undergoes multi-dimensional optimization, including semantic deduplication, priority optimization, format conversion, and source quality backtracking, forming a unified format optimized semantic. Through an interactive interface, it is adapted and interacted with electronic design automation tools. After consistency verification and performance testing feedback loops, the final design data and full-process traceability information are obtained and stored. This invention achieves unified management, efficient compression, intelligent optimization, and full-process traceability of design data.

In some embodiments, a computer-implemented method for designing an integrated circuit using transistor placement optimization is provided. A computing system receives a specification for the integrated circuit. The specification includes a netlist describing a plurality of transistors and connections between terminals of the plurality of transistors. The computing system determines an initial location and an orientation on a canvas for each transistor in the plurality of transistors. The computing system uses an objective function based at least in part on the initial locations and the orientations of the plurality of transistors to generate a rough placement having globally optimized locations and orientations for the plurality of transistors. The computing system uses a local refinement technique to optimize the rough placement to generate a fine placement, and uses a routing technique to generate a routing for the fine placement to generate a completed design.

This application relates to a three-node flip-flop fault-tolerant latch suitable for harsh radiation environments in the field of integrated circuit design technology. The latch includes: an excitation module for transmitting input signals to sensitive nodes N2, N4, N6, and Q through multiple clock-controlled transmission gates; an interlock feedback loop consisting of four three-input clock-gated inverting CE units and four three-input inverting CE units; a module responsible for generating voltages for sensitive nodes N1, N3, N5, and N7, and for achieving interference self-recovery of sensitive nodes N1 to N7 and Q based on signals from sensitive nodes A and B; and an AB node generation and recovery module using two four-input inverting CE units and inversion operation to generate voltages for sensitive nodes A and B from signals from N1 to N7 and Q. This latch has good TNU (Terror-Noise Nullification) immunity, enabling three-node flip-flop recovery even when any three sensitive nodes experience a TNU.

The invention belongs to the technical field of integrated circuit design automation, and discloses an FPGA process mapping method and system based on bias learning, and the method comprises the steps: S1, carrying out the KLUT input lookup table mapping of an input logic network, and obtaining initial mapping; s2, on the basis of the initial mapping, constructing a dependency graph, and obtaining a dependency relationship between a cut set of each node and a leaf node of the cut set; s3, initializing an increment table based on a dependency relationship between the cut set of each node and a leaf node thereof, and calculating an area increment of each candidate cut set of each node relative to the current optimal cut set; s4, based on the area increment of each candidate cut set of each node relative to the current optimal cut set, executing multiple rounds of offset learning iterative optimization; and S5, learning experience from the local optimal solution of the current round, recovering a global optimal solution, and outputting a result.

The invention discloses a PUF (Physical Unclonable Function) circuit based on a memristor cellular automaton and a use method thereof, and belongs to the technical field of integrated circuit design and information security, the circuit comprises a first cellular initialization module, a second cellular initialization module, 2N cellular node modules, 2N-bit excitation signal input terminals, 2N-bit response signal output terminals, and power supply terminals VCC, VDD, VEE and GND, the 2N cellular node modules are connected end to end to form an annular array, N is an integer which is a positive integer multiple of 4, and each cellular node module comprises a Rule30 logic module and a cellular module, so that the problems of high hardware overhead, poor expandability and insufficient attack resistance of a traditional PUF (Physical Unclonable Function) are effectively solved; the circuit structure is simplified; the hardware resource consumption is reduced; and the flexible expansion of response bits is supported.

The application provides an MSI address translation simulation system and method, and relates to the technical field of integrated circuit design and verification. The system comprises an MSI transaction generation module, which is used for generating MSI transactions based on an interrupt target semantic model; a synchronous interface module, which is used for synchronizing configuration information, running states and transaction semantics between the MSI address translation simulation system and a device under test; an MSI transaction identification module, which is used for identifying MSI transactions in a mixed transaction flow; a translation result collection and path fingerprint extraction module, which is used for collecting translation results of the MSI transactions after address translation by the device under test and constructing translation path fingerprints; and a verification module, which is used for performing consistency verification on the translation results and the translation path fingerprints output by the device under test. The system provided in the application embodiment can realize structured simulation and consistency verification of the MSI address translation process.

The application relates to the technical field of integrated circuit design and verification, in particular to a service test system for a texture block level, which generates a plurality of accurate controllable screen coordinates through a simulation geometry processing module and a simulation rasterization module and provides the screen coordinates to a texture processing module, so that the texture processing module can independently verify the logic of texture processing based on the generated screen coordinates, the reliability of the texture processing module does not need to be tested through system-level verification for service testing, the test requirement is lowered to the texture block level, thus the workload of system-level testing can be saved, the influence of problems of other modules on the texture processing module testing is avoided, the test difficulty is reduced, and the test efficiency and problem positioning accuracy of the texture block level service test are improved.

This invention discloses a high-speed, high-precision voltage descent monitoring circuit, solving the problem of accurate and timely monitoring of voltage descent phenomena in large-scale integrated circuits, belonging to the fields of digital integrated circuit design and power management. This invention provides an optimized design method for ring oscillator point circuits, using standard cell type, threshold, drive capability, and power consumption as variables to find the ring oscillator circuit design with the highest voltage sensitivity, improving the resolution of the voltage descent monitoring circuit; it provides a one-fold, compact ring oscillator layout design to ensure load balance between nodes; it provides a Nyquist counter design to count the number of times nodes flip over a period of time, improving the voltage monitoring range and solving the metastable sampling problem of traditional counters; and it provides a high-speed voltage quantization circuit that processes coarse and fine quantization in parallel, improving the maximum sampling rate and quantization rate of the voltage descent monitoring circuit.

The application discloses a cross-clock domain register synchronization method and device. It relates to the technical field of digital integrated circuit design. The method comprises the following steps: when the target clock domain is unavailable, routing the bus read-write request to a shadow register array driven by a system clock, and writing a write transaction log into a log queue when the write transaction is completed, the write transaction log comprising a target address, write data and byte enable; when the target clock domain changes from unavailable to available and the log queue is not empty, setting the handshake signal of the bus interface to invalid, reading the write transaction log from the log queue according to the write sequence, and writing the write data into the target register through a byte mask circuit according to the target address in the write transaction log; when the target clock domain is available and the log queue is empty, routing the bus read-write request to the target register, and setting the handshake signal of the bus interface to valid. The method realizes register access integrity and sequential consistency in the target clock dynamic change scenario.

The invention discloses a wetting current circuit and an interface circuit, relates to the field of integrated circuit design, and solves the problems that an interface chip cannot normally output wetting current under a specific working condition, and even the interface chip is damaged. The wetting current circuit comprises: a current port for outputting a wetting current; a first end of the first current source module is connected with a first control signal, a second end is grounded, a third end is connected with the current port, and the first current source module is used for outputting pull current according to the first control signal; one end of the first anti-reverse module is connected to the chip power supply, the other end is connected with the first current source module, and the first anti-reverse module is used for isolating a forward path from the current port to the chip power supply; one end of the second current source module is connected to a second control signal, and the other end is grounded for outputting sink current according to the second control signal; and one end of the second anti-reverse module is connected with the second current source module, the other end of the second anti-reverse module is connected with the current port and the first current source module, and the second anti-reverse module is used for isolating a forward path from the chip ground to the current port.

The invention discloses a hardware acceleration device and method for high-throughput lossless data compression, and relates to the field of integrated circuit design. The device comprises a front-end LZ77 compression module, a middle buffer module and a rear-end entropy coding module, wherein the front-end LZ77 compression module is configured to search and match input data; the intermediate buffer module is configured to realize decoupling of front and rear end processing time domains through an asynchronous symbol buffer; the back-end entropy coding module is configured to receive an output of the intermediate buffer module, construct a microcode packet intermediate representation containing codeword information, and parse the microcode packet to generate a serial compressed bit stream. According to the method, invalid memory reading and assembly line pause can be effectively eliminated, the throughput and the energy efficiency ratio of the hardware compressor are remarkably improved on the premise of not sacrificing the compression rate, and the method is suitable for unloading acceleration of a high-performance solid state disk controller, an intelligent network card and a cloud server.