1908 results about "Integrated circuit design" patented technology

Some embodiments provide a method for optimizing a mask layout generated from a design layout of an integrated circuit (IC). The method generates, based on a first mask layout, a simulated wafer image having predicted manufactured shapes representing IC components that are to be manufactured on a first layer of the IC. The method identifies a cross-sectional overlap between a first shape of a first IC component in the simulated wafer image and a second shape of a second IC component in a wafer image for a second layer of the IC. The first and second IC components are related components in the IC. Based on the cross-sectional overlap, the method modifies the first mask layout to generate a modified second mask layout for the first layer.

The invention discloses an automatic fault detection and repair integrated circuit design method based on a neural network. The method comprises the following steps: S1, obtaining and preprocessing operation data of an integrated circuit; s2, analyzing the preprocessed data by using a trained neural network model, and dynamically optimizing the model through an adaptive weight pruning algorithm; s3, inputting circuit operation data in real time, automatically identifying fault types and positions, and storing fault information; s4, starting an automatic repair mechanism based on the stored fault information, and generating a repair strategy through a multi-target collaborative optimization algorithm; s5, logic reconstruction is executed according to the repair strategy, a redundant circuit and parameter adjustment are started, and a repair path is optimized through deep reinforcement learning; s6, after repairing is completed, the neural network model is used for detecting and verifying the repairing effect again; and S7, after the repair verification is passed, updating the fault historical database. According to the invention, the automation level of fault detection and repair of the integrated circuit is improved, and the reliability and efficiency of the system are enhanced.

The invention discloses an RISC-V vector optimization method, device and equipment based on thread scheduling, relates to the field of digital integrated circuit design, and is used for solving the problems of operation resource waste, relatively low operation efficiency and performance reduction caused by memory access performance limitation in the prior art. Comprising the following steps: acquiring an RISC-V vector instruction, extracting decoding information from the RISC-V vector instruction, and acquiring register configuration information in a vector state; determining thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and hardware configuration; executing a corresponding thread task according to the thread scheduling information; after execution is finished, if the thread task of the current instruction is executed, updating the state and delivering the current instruction; otherwise, updating the state and executing the next thread task until all the thread tasks are executed, writing back the data, completing instruction delivery and ending the instruction cycle. According to the method, the vector instruction execution performance under memory access performance limitation can be effectively improved, and the overall operation performance is improved.

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

The invention belongs to the field of integrated circuit design, and particularly relates to a chip layout optimization method, system and device based on improved reinforcement learning. The method comprises the following steps: S1, constructing a layout optimization model comprising a feature coding module, a feature fusion module, an experience pool, a strategy network and a value network; the feature coding module is used for extracting a position mask, a line mask and a view mask of the netlist file; the feature fusion module extracts local features and global features and generates comprehensive features; the experience pool, the strategy network and the value network form a reinforcement learning framework. S2, using a large number of random netlists as sample data for training a layout optimization model; and S3, inputting a chart file to be optimized into the trained layout optimization model, outputting an optimized netlist file by the layout optimization model, and generating a corresponding optimized circuit layout chart according to the netlist file. The chip layout optimization method solves the problems that an existing chip layout optimization method is low in efficiency and insufficient in generalization.

The invention relates to the technical field of energy storage technology, integrated circuit design and battery management systems, and discloses a passport-sensing integrated battery management chip and a battery management system architecture, battery information is collected based on the passport-sensing integrated battery management chip, and unique battery passport information is generated. And then real-time interaction with the BMS main control module is carried out through the daisy chain communication module, so that the health state of the battery is evaluated and managed. The battery cell state data acquisition and traceability functions are realized through the battery cell slave board, the BMS master control module has a fine management function on the battery state, battery safety early warning and daisy chain communication channels are provided to realize real-time interaction between the battery cell slave board information and the BMS master control module information, online and offline information disclosure modes are fused, a collaborative management architecture is established, and the battery cell state data acquisition and traceability functions are realized. Intelligent management and data tracking of the whole life cycle of the battery are realized, and the safety, reliability and traceability of the battery are improved.

The invention provides an in-orbit integrated circuit aging fault diagnosis method and diagnosis system, and relates to the technical field of integrated circuit design, and the method comprises the steps: ground training: collecting characteristic parameters, carrying out the characteristic parameter processing based on an SPI protocol algorithm, a digital signal recovery fixed-point decimal algorithm, a wavelet transform filtering algorithm and a deviation standardization algorithm, and carrying out the fault diagnosis; constructing an aging failure fault data set, training through a back propagation algorithm to obtain feed-forward neural network parameters, and transplanting the feed-forward neural network parameters to a feed-forward neural network constructed based on Pytorch and a feed-forward neural network constructed based on FPGA for joint testing; and in-orbit testing: data enters a data buffer area, training data is provided for a learning training module, feedforward neural network parameters are periodically updated by using an exponential weighted moving average algorithm, and the feedforward neural network parameters are transplanted to a feedforward neural network established based on Pytorch and a feedforward neural network established by an FPGA for joint testing. Continuous learning of on-orbit data is realized, and the method adapts to irregular periodic electromagnetic influence of a space environment.

The invention relates to a preparation method of a memory cell and a memory, and relates to the technical field of integrated circuit design and manufacturing, the memory cell comprises an active column, a capacitor, a first grid electrode and a second grid electrode, the active column has a first end surface and a second end surface deviating from each other along a first direction, and the first end surface is used for being connected with a bit line; the active column internally comprises a first doped region, a channel region and a second doped region which are sequentially arranged along a first direction, the channel region is provided with a first outer surface and a second outer surface which are deviated from each other along a second direction, and the channel region internally comprises a stress structure which penetrates through the active column along a third direction; the first direction and the second direction intersect and are perpendicular to the third direction; the capacitor covers the second end surface and circumferentially surrounds part of the side surface of the active column; the first grid electrode is located on the first outer surface of the channel region; the second grid electrode is located on the second outer surface of the channel region, and the performance and reliability of the memory cell can be improved at least under the condition that the size of the memory cell is reduced.

The invention relates to the technical field of integrated circuit design, and particularly discloses a low-noise programmable amplifier, which comprises a first fully-differential amplifier, a second fully-differential amplifier, a third fully-differential amplifier and a fourth fully-differential amplifier, the second fully differential amplifier comprises a pair of differential input ends and is electrically connected with the first fully differential amplifier through an interstage chopper switch; a pair of input chopping switches, wherein the input end of each input chopping switch is electrically connected with a differential input signal; the output end of each output chopping switch is electrically connected with the output end of the second fully differential amplifier; the input capacitance network is positioned between the pair of input chopping switches and the two pairs of differential input ends; the feedback capacitance network is positioned between the pair of output chopping switches and the two pairs of differential input ends; and the plurality of zeroing switches are positioned between the input and the output of the first fully differential amplifier. The two transconductance amplifiers in the first fully-differential amplifier share the same current, the overall transconductance is doubled compared with single-pair differential input, and the noise of the amplifier is reduced.

The invention relates to the technical field of integrated circuit design verification, and provides a chip power consumption analysis optimization method and system, and the method comprises the steps: obtaining circuit structure information of a chip, carrying out the analysis of the circuit structure information, generating and analyzing a module topological graph and a function logic graph of a circuit, and obtaining static power consumption data and dynamic power consumption data; after a preset analysis model is input and working mode parameters are obtained, a key path in the circuit structure information is reconstructed, based on the reconstructed circuit structure information, dynamic behavior simulation is carried out on the function logic diagram again, simulation power consumption data are generated, the simulation power consumption data and the dynamic power consumption data are subjected to comparative analysis, and the simulation power consumption data are obtained. And generating a power consumption optimization scheme based on the comparison result. By acquiring and analyzing the circuit structure information of the chip, a power consumption optimization scheme is generated, the energy efficiency ratio of the chip is improved, and the problem that an optimization path is difficult to quickly generate for a complex circuit structure during positioning of a power consumption hot spot and circuit optimization reconstruction is solved.

The invention belongs to the technical field of integrated circuit design automation, and discloses an anti-radiation standard unit automatic layout method, which adopts a two-stage reinforcement learning strategy: in the first stage, training a device layout strategy model, extracting MOS device information by analyzing a CDL file, and constructing a circuit diagram structure as state representation; generating a preliminary device layout result by using a dynamic action mask mechanism; and in the second stage, independently training the guard band insertion strategy model, and optimizing the guard band insertion position and sequence based on the candidate insertion point set so as to meet the anti-radiation design rule and reduce the wiring difficulty. The two stages both adopt a Maskable PPO algorithm, encourages gate alignment, source-drain proximity and shortest connection path through a reward function, and punishes layout conflicts and DRC violations. According to the invention, by means of the two-stage design of division of labor and cooperation, the layout efficiency and compliance of the anti-radiation standard unit are significantly improved, and the method has the characteristics of high efficiency, self-adaption and high engineering practicability.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

The invention discloses a 10T-SRAM (10 T-Static Random Access Memory) in-memory multiplication unit, an in-memory operation unit and a circuit, and relates to the technical field of integrated circuit design. The invention provides a 10T-SRAM in-memory multiplication unit consisting of a 6T-SRAM part and an MAC (Media Access Control) calculation part consisting of four NMOS (N-channel Metal Oxide Semiconductor) tubes, on one hand, a 1bit weight is stored in the 6T-SRAM part, on the other hand, a 4bit unsigned number is divided into high 2bit input X [3: 2] and low 2bit input X [1: 0], and the high 2bit input X [3: 2] and the low 2bit input X [1: 0] are respectively input into the MAC calculation part, so that the multiplication of the 4bit unsigned number and the 1bit weight is realized in an in-memory calculation mode, and the calculation efficiency is improved. And the voltage drop is reflected through bit lines RBLN and RBLP. The in-memory multiplication circuit solves the problem that the existing in-memory multiplication circuit has few input bits and cannot meet the calculation requirement.

An exemplary integrated circuit design lockout system comprises an integrated circuit and a key obfuscated circuit embedded with the integrated circuit. The key obfuscated circuit is configured to verify that a user provides a valid key for the integrated circuit before the user is allowed to operate the integrated circuit. The exemplary integrated circuit design lockout system further comprises a lockout circuit embedded with the key obfuscated circuit, wherein the lockout circuit is configured to allow for a threshold number of failed attempts for the user to provide the valid key before the lockout circuit prohibits the user from making any further attempts at providing the valid key for the integrated circuit.

A system includes a processor for performing a thermal analysis for an IC layout, which includes a redistribution structure having a plurality of conductive layers stacked one upon another in a thickness direction. In response to a property of a first conductive layer satisfying a first condition, the processor applies a first modeling rule to the first conductive layer to obtain a first model, and, in response to the property of a second conductive layer satisfying a second condition but not the first condition, the processor applies a second modeling rule different from the first modeling rule to the second conductive layer to obtain a second model. The processor performs a thermal simulation for the IC layout based on the first and second models, and, based on the thermal simulation result, modifies the IC layout or proceeds with manufacturing one or more IC devices corresponding to the IC layout.

The invention discloses a clock domain crossing circuit timing sequence closed-loop optimization method and system, and relates to the technical field of integrated circuit design, and the method comprises the steps: reading a circuit netlist and timing sequence constraints, recognizing a converged path, and carrying out the clustering analysis to form a plurality of path groups; establishing a time sequence analysis model, and dynamically calculating the maximum delay constraint of the data signal in the path group; matching and executing at least one time sequence optimization strategy for each path group; and carrying out closed-loop time sequence verification, retaining a legacy path set which does not meet the constraint, and repeatedly executing the time sequence optimization strategy until a convergence condition is reached or the maximum preset number of iterations is reached. According to the method disclosed by the invention, the cross-domain path needing to be optimized in the DMUX structure can be accurately positioned without manual intervention, so that the path identification efficiency is improved, constraint omission or grouping deviation caused by manual operation is avoided, design defects are reduced from the source, and the design reliability of a chip is improved.

The invention discloses a high-speed level conversion circuit, and belongs to the technical field of integrated circuit design, the circuit mainly comprises an input signal processing module, a voltage boosting module, a differential signal generation module, a signal amplification module and an output module, the input signal processing module converts a low-voltage input signal into a complementary logic signal pair; the voltage boosting module raises the voltage amplitude of the complementary logic signal by using a charge pump principle; the lifted signal drives a thick gate transistor in the differential signal generation module to generate a differential signal; the signal amplification module adopts a cross coupling structure to quickly amplify the differential signal; and finally, the output module outputs a high-voltage domain signal in an inverted manner. By introducing voltage bootstrap before gate driving, the overdrive voltage of a core switch tube is remarkably increased, so that the problem of low conversion speed of a traditional level conversion circuit is effectively solved on the premise of not increasing the device size and static power consumption, and high-speed and high-efficiency level conversion is realized.

The invention discloses an automatic batch interface connection method, which relates to the technical field of interface connection, and comprises the following steps: S1, confirming an input / output port; s2, parameterizing macro definition; s3, a connection code is generated; s4, generating interfaces in batches; and S5, carrying out batch connection. According to the method, automatic generation of batch interface connections is achieved through parameterized macro definition, the requirement for manual coding is reduced, the risk of human errors is reduced, the efficiency of the verification process is improved, a designer only needs to specify macro parameters in the configuration file, a large number of different interface connections can be rapidly configured, complex connection codes do not need to be written, and the method is convenient and fast to operate. The reusability of codes is enhanced through parameterized macro definition, the same macro definition can be repeatedly used in different items or different verification platforms, high flexibility is provided through the parameterized macro definition, interface connection is supported to be rapidly modified and adapted, and the large-scale integrated circuit design method and device can adapt to various complex scenes in the large-scale integrated circuit design process.

The invention discloses a finger-storage-multiply-accumulate three-stacked floating-point number in-memory computing system, and belongs to the field of application-specific integrated circuit design. According to the system, a three-stack type floating-point number calculation framework is designed, a pointing shift and mantissa multiply-accumulate module is designed, and floating-point number multiply-accumulate calculation of global pointing is supported. Compared with a traditional parallel floating-point multiply-accumulate circuit, the parallel floating-point multiply-accumulate circuit has the advantages that a calculation process of global alignment shifting and mantissa multiply-accumulate in sequence and a three-stack type calculation framework are adopted, similar calculation precision is achieved with smaller hardware overhead, low hardware overhead and high calculation precision are both considered, and the comprehensive performance of the calculation framework and the circuit is improved.

The invention relates to a core particle thermal simulation finite element mesh generation method based on a neural network. The method comprises a geometric and thermal feature extraction module, a temperature distribution prediction module and an intelligent grid optimization module. The geometric and thermal feature extraction module realizes accurate prediction of chip temperature distribution through tensor construction in combination with multi-scale convolution, pyramid pooling and deformable convolution; the intelligent grid optimization module adaptively optimizes a finite element grid through coupling of thermal gradient and geometric constraint, reduces the number of grid units and improves calculation efficiency. According to the method, deep learning and finite element mesh generation are combined for the first time, a traditional iterative mesh refinement process is replaced by predicting heat distribution through a neural network, the mesh generation speed is remarkably increased, and meanwhile, the thermal simulation precision is kept within 0.8%. The method is particularly suitable for a complicated 2.5 D / 3D chip packaging structure, can effectively cope with thermal management challenges in modern integrated circuit design, and provides a rapid and accurate thermal simulation tool for chip design.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

The invention is applicable to the technical field of integrated circuit design, and provides a method for repairing crosstalk noise violation on a data path, which comprises the following steps of: reading a crosstalk noise violation report of a static time sequence analysis STA tool; finding an interconnection line corresponding to each violation in the report from a layout wiring tool, and finding adjacent interconnection line position information and connected logic unit information of the current interconnection line; selecting a corresponding repairing scheme according to the specific conditions of the interconnection lines and the connected logic units, and executing and adjusting the repairing scheme so as to repair crosstalk noise on a data path; and after a round of repair is completed, if crosstalk noise violation is also detected in the STA tool, the steps need to be executed again until all crosstalk noise problems are solved. According to the method provided by the invention, the crosstalk problem is efficiently identified and solved through an automatic process, the signal integrity and the function correctness of circuit design are ensured, and compared with a traditional scheme, the method is more targeted, and the gain brought by single change is favorably improved.

The invention provides a circuit optimization method, system and device based on model predictive control and a medium, and relates to the technical field of integrated circuit design, and the method comprises the steps: constructing a circuit knowledge graph and a simulation data lookup table according to a circuit design experience document and circuit simulation data; initializing a search feasible region of design points according to the circuit knowledge graph and the simulation data lookup table, and performing multi-point exploration Bayesian optimization to obtain a candidate design point set of the current circuit; and according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, in combination with a model prediction control framework, executing a reinforcement learning method to obtain an optimal design point of the current circuit, and providing optimal configuration of the current circuit. According to the method, the consumption of simulation computing resources is effectively reduced, the optimization efficiency is improved, and meanwhile, the design is ensured to meet the multi-target performance requirements of gain, power consumption, bandwidth and the like.

The invention relates to the technical field of integrated circuit design and verification, and discloses a chip simulation verification acceleration method, device and equipment and a storage medium, and the method comprises the steps: obtaining simulation analysis of a tested design file and excitation, obtaining a corresponding simulation result, analyzing a module occupying the most simulation time and memory according to the simulation result, and obtaining a simulation result; the method comprises the following steps of: decomposing a simulation process of a whole chip into a plurality of simulation operation tasks by combining a design requirement and a function definition of the chip; distributing the disassembled operation tasks to a multi-core processor for block simulation; and setting a dynamic performance optimization option DPO, performing multiple tests to collect data, and generating a simulation verification result based on a simulation result and an original design expectation. According to the method, the to-be-tested design is disassembled for layered compiling simulation, and the DPO is set for dynamic performance optimization, so that the simulation speed is increased, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.

An integrated circuit design may be generated for an integrated circuit. The integrated circuit design may include an instance of a module description that describes a functional operation of a module. The integrated circuit design may be encoded in an intermediate representation (IR) data structure. A parameter comprising metadata associated with the instance may be received. A compiler may compile the IR data structure to produce a register-transfer level (RTL) data structure. The RTL data structure may encode a logic description associated with the instance. Compiling the IR data structure may include associating the parameter comprising metadata with the logic description.

The invention relates to the technical field of electrical variable monitoring and analysis, in particular to a wide-temperature-range electrical variable monitoring method and system. The method comprises the following steps: acquiring design data of the thick film integrated circuit; performing circuit distribution functional feature analysis based on the thick film integrated circuit design data to generate circuit distribution functional feature data; acquiring a temperature partition electric variable distribution signal; potential representation quantitative data analysis of abnormal multi-temperature-zone electrical variable distribution is carried out based on the temperature partition electrical variable distribution signals, and potential quantitative data of abnormal multi-temperature-zone electrical variable distribution are generated; analyzing circuit distribution passive chip signal compensation mapping data according to the abnormal multi-temperature-zone electrical variable distribution potential quantitative data; and performing iterative closed-loop monitoring on the temperature partition electrical variable distribution signal based on the circuit distribution passive chip signal compensation mapping data to generate an iterative temperature partition electrical variable distribution signal. According to the invention, accurate monitoring of electrical variable parameters of temperature change in a complex circuit system is realized.

The invention discloses a band-gap reference source high-order curvature compensation method based on an operational amplifier, and belongs to the technical field of high-precision analog integrated circuit design, and the method comprises the steps: generating an absolute temperature proportion PTAT current and an absolute temperature complementary CTAT current; generating a high-order curvature compensation voltage based on the PTAT current and the CTAT current; amplifying the generated high-order curvature compensation voltage through an operational amplifier, and superposing the amplified high-order curvature compensation voltage to a band-gap reference output stage to obtain compensated band-gap reference output voltage; and carrying out band-gap reference output calibration on the compensated band-gap reference output voltage so as to ensure that the temperature drift coefficient of the output band-gap reference voltage in the preset temperature range is smaller than a preset threshold value. According to the invention, high-order elimination of base-emitter voltage nonlinearity can be realized in a wide temperature range, and a relatively low temperature coefficient and low noise are achieved.

The invention discloses a fault-considered spacecraft integrated chip interface circuit potential path analysis method, a storage medium and equipment, and belongs to the technical field of integrated circuit design and fault analysis. The method aims at solving the problem that an analysis method for a path under a failure mechanism under different environmental stresses is lacked. The method comprises the following steps: constructing an interface circuit simulation model of an integrated device based on a common interface circuit and a potential path structure in a spacecraft electronic system, then supplementing degradation mechanisms in various task stress environments, and determining a fault mode table of the interface circuit of the integrated device; a circuit simulation method is adopted to carry out potential path analysis considering fault factors on an interface circuit under a typical task profile, a fault path response feature library of the interface circuit under the task profile is obtained, then a constraint clue table for interface circuit design is formed, an interface circuit failure associated fault tree model is constructed, and the interface circuit failure associated fault tree model is constructed. And calibrating a relation path between various potential paths and device degradation or local failure for failure positioning and path checking.