1244 results about "Integrated circuit design" patented technology

The invention belongs to the technical field of integrated circuit design verification, and particularly discloses an SoC performance verification method and device based on dynamic QoS regulation and control, a medium and equipment, and the method comprises the steps: analyzing a chip architecture, and obtaining a chip resource mapping table; constructing an automatic verification environment based on the chip resource mapping table and performing testing; scene parameter configuration is carried out according to a target application scene and based on the chip resource mapping table; and performing dynamic QoS regulation and control based on the configured scene parameters in a tested automatic verification environment so as to verify the performance of the SoC. According to the invention, the accuracy and efficiency of SoC performance verification and the consistency of the result and the actual application scene can be improved.

The invention discloses a clock tree synthesis method and system based on clustering, and the method comprises the steps: carrying out the preliminary grouping of registers through employing a K-means clustering method, generating the position of a first-stage buffer under the condition that the maximum fan-out number limitation constraint, the maximum RC constraint and the position overlapping constraint are satisfied, and generating a second-stage buffer based on the position, and then constructing a subsequent clock tree by adopting a DME algorithm. The problem of clock signal distribution in large-scale integrated circuit design is solved, clock delay, clock skew and the number of buffers can be reduced, and the comprehensive quality of the clock tree is improved.

The invention discloses a digital back-end full-process script design method, and relates to the field of digital integrated circuit design, and the method comprises the steps: receiving an RTL behavior level netlist, a process library file and a constraint file as input, and generating a library configuration file valeeb.tcl; a gate-level netlist and a corresponding comprehensive report are generated by using a library configuration file valerib.tcl; performing logic synthesis according to the behavior level netlist and the make syn to generate a gate level netlist, and generating layout and wiring data through make out; according to the layout and wiring data, antenna inspection is carried out through a make ant command, design rule inspection is carried out through a make drc command, and comparison inspection of a generated layout and a schematic diagram is carried out through a make lvs command; performing power consumption analysis according to the layout and wiring data; and performing IR analysis according to the parasitic parameters. Aiming at the problem that the chip digital back-end design process is low in efficiency in the prior art, the design efficiency is improved.

The invention relates to the technical field of energy storage technology, integrated circuit design and battery management systems, and discloses a passport-sensing integrated battery management chip and a battery management system architecture, battery information is collected based on the passport-sensing integrated battery management chip, and unique battery passport information is generated. And then real-time interaction with the BMS main control module is carried out through the daisy chain communication module, so that the health state of the battery is evaluated and managed. The battery cell state data acquisition and traceability functions are realized through the battery cell slave board, the BMS master control module has a fine management function on the battery state, battery safety early warning and daisy chain communication channels are provided to realize real-time interaction between the battery cell slave board information and the BMS master control module information, online and offline information disclosure modes are fused, a collaborative management architecture is established, and the battery cell state data acquisition and traceability functions are realized. Intelligent management and data tracking of the whole life cycle of the battery are realized, and the safety, reliability and traceability of the battery are improved.

The invention belongs to the technical field of integrated circuit design automation, and discloses an anti-radiation standard unit automatic layout method, which adopts a two-stage reinforcement learning strategy: in the first stage, training a device layout strategy model, extracting MOS device information by analyzing a CDL file, and constructing a circuit diagram structure as state representation; generating a preliminary device layout result by using a dynamic action mask mechanism; and in the second stage, independently training the guard band insertion strategy model, and optimizing the guard band insertion position and sequence based on the candidate insertion point set so as to meet the anti-radiation design rule and reduce the wiring difficulty. The two stages both adopt a Maskable PPO algorithm, encourages gate alignment, source-drain proximity and shortest connection path through a reward function, and punishes layout conflicts and DRC violations. According to the invention, by means of the two-stage design of division of labor and cooperation, the layout efficiency and compliance of the anti-radiation standard unit are significantly improved, and the method has the characteristics of high efficiency, self-adaption and high engineering practicability.

The invention relates to the technical field of integrated circuit design and artificial intelligence hardware acceleration, and particularly discloses a quantization precision adaptive switching hardware acceleration architecture. Hardware is divided into a static area and a dynamic area, wherein the static area comprises a pre-processing module, a post-processing module, a control module and a reconfigurable logic loading control block which run all the time; the dynamic region bears a quantization and inverse quantization module composed of a plurality of reconfigurable logic units. The method is characterized in that a model precision instruction is analyzed through a control module, and a reconfigurable logic file with corresponding precision is dynamically loaded to a dynamic area from external starting equipment by a loading control block according to an internal address mapping table, so that seamless switching of different quantization precision is realized on the hardware level, and the whole chip does not need to be burnt again. According to the design, through a modularized and reconfigurable hardware structure, the limitation of fixed-precision hardware in coping with diversified AI models is effectively solved, and the deployment flexibility and energy efficiency are remarkably improved.

The invention discloses a 10T-SRAM (10 T-Static Random Access Memory) in-memory multiplication unit, an in-memory operation unit and a circuit, and relates to the technical field of integrated circuit design. The invention provides a 10T-SRAM in-memory multiplication unit consisting of a 6T-SRAM part and an MAC (Media Access Control) calculation part consisting of four NMOS (N-channel Metal Oxide Semiconductor) tubes, on one hand, a 1bit weight is stored in the 6T-SRAM part, on the other hand, a 4bit unsigned number is divided into high 2bit input X [3: 2] and low 2bit input X [1: 0], and the high 2bit input X [3: 2] and the low 2bit input X [1: 0] are respectively input into the MAC calculation part, so that the multiplication of the 4bit unsigned number and the 1bit weight is realized in an in-memory calculation mode, and the calculation efficiency is improved. And the voltage drop is reflected through bit lines RBLN and RBLP. The in-memory multiplication circuit solves the problem that the existing in-memory multiplication circuit has few input bits and cannot meet the calculation requirement.

The invention discloses a clock domain crossing circuit timing sequence closed-loop optimization method and system, and relates to the technical field of integrated circuit design, and the method comprises the steps: reading a circuit netlist and timing sequence constraints, recognizing a converged path, and carrying out the clustering analysis to form a plurality of path groups; establishing a time sequence analysis model, and dynamically calculating the maximum delay constraint of the data signal in the path group; matching and executing at least one time sequence optimization strategy for each path group; and carrying out closed-loop time sequence verification, retaining a legacy path set which does not meet the constraint, and repeatedly executing the time sequence optimization strategy until a convergence condition is reached or the maximum preset number of iterations is reached. According to the method disclosed by the invention, the cross-domain path needing to be optimized in the DMUX structure can be accurately positioned without manual intervention, so that the path identification efficiency is improved, constraint omission or grouping deviation caused by manual operation is avoided, design defects are reduced from the source, and the design reliability of a chip is improved.

The invention discloses a high-speed level conversion circuit, and belongs to the technical field of integrated circuit design, the circuit mainly comprises an input signal processing module, a voltage boosting module, a differential signal generation module, a signal amplification module and an output module, the input signal processing module converts a low-voltage input signal into a complementary logic signal pair; the voltage boosting module raises the voltage amplitude of the complementary logic signal by using a charge pump principle; the lifted signal drives a thick gate transistor in the differential signal generation module to generate a differential signal; the signal amplification module adopts a cross coupling structure to quickly amplify the differential signal; and finally, the output module outputs a high-voltage domain signal in an inverted manner. By introducing voltage bootstrap before gate driving, the overdrive voltage of a core switch tube is remarkably increased, so that the problem of low conversion speed of a traditional level conversion circuit is effectively solved on the premise of not increasing the device size and static power consumption, and high-speed and high-efficiency level conversion is realized.

The invention discloses an automatic batch interface connection method, which relates to the technical field of interface connection, and comprises the following steps: S1, confirming an input / output port; s2, parameterizing macro definition; s3, a connection code is generated; s4, generating interfaces in batches; and S5, carrying out batch connection. According to the method, automatic generation of batch interface connections is achieved through parameterized macro definition, the requirement for manual coding is reduced, the risk of human errors is reduced, the efficiency of the verification process is improved, a designer only needs to specify macro parameters in the configuration file, a large number of different interface connections can be rapidly configured, complex connection codes do not need to be written, and the method is convenient and fast to operate. The reusability of codes is enhanced through parameterized macro definition, the same macro definition can be repeatedly used in different items or different verification platforms, high flexibility is provided through the parameterized macro definition, interface connection is supported to be rapidly modified and adapted, and the large-scale integrated circuit design method and device can adapt to various complex scenes in the large-scale integrated circuit design process.

The invention discloses a finger-storage-multiply-accumulate three-stacked floating-point number in-memory computing system, and belongs to the field of application-specific integrated circuit design. According to the system, a three-stack type floating-point number calculation framework is designed, a pointing shift and mantissa multiply-accumulate module is designed, and floating-point number multiply-accumulate calculation of global pointing is supported. Compared with a traditional parallel floating-point multiply-accumulate circuit, the parallel floating-point multiply-accumulate circuit has the advantages that a calculation process of global alignment shifting and mantissa multiply-accumulate in sequence and a three-stack type calculation framework are adopted, similar calculation precision is achieved with smaller hardware overhead, low hardware overhead and high calculation precision are both considered, and the comprehensive performance of the calculation framework and the circuit is improved.

The invention relates to the technical field of integrated circuit design, in particular to a three-dimensional stacked memory controller supporting lateral expansion, which comprises a memory control logic unit connected with an interface expansion unit and a mode configuration unit, the interface expansion unit and the mode configuration unit are connected with a near memory calculation unit, the near memory calculation unit is connected with the memory control logic unit, and the memory control logic unit is connected with the interface expansion unit. And the on-chip cache unit is connected with the memory control logic unit. The on-chip cache unit is used for storing high-frequency access data; the memory control logic unit is used for forming a hierarchical memory architecture; the interface expansion unit is used for transversely accessing the low-speed memory; the mode configuration unit enables on-chip high-speed cache, three-dimensional stacked memory and low-speed memory access to be independently Bypass; the near memory calculation unit is used for providing transposition, stepping, compression and direct memory calculation functions. Therefore, the problems that in the prior art, a three-dimensional stacked memory and a low-speed memory cannot be efficiently organized and matched, development is complex, and a hierarchical framework is missing are solved.

The invention provides a circuit optimization method, system and device based on model predictive control and a medium, and relates to the technical field of integrated circuit design, and the method comprises the steps: constructing a circuit knowledge graph and a simulation data lookup table according to a circuit design experience document and circuit simulation data; initializing a search feasible region of design points according to the circuit knowledge graph and the simulation data lookup table, and performing multi-point exploration Bayesian optimization to obtain a candidate design point set of the current circuit; and according to the simulation data lookup table, the circuit knowledge graph and the candidate design point set, in combination with a model prediction control framework, executing a reinforcement learning method to obtain an optimal design point of the current circuit, and providing optimal configuration of the current circuit. According to the method, the consumption of simulation computing resources is effectively reduced, the optimization efficiency is improved, and meanwhile, the design is ensured to meet the multi-target performance requirements of gain, power consumption, bandwidth and the like.

The invention relates to the technical field of integrated circuit design and verification, and discloses a chip simulation verification acceleration method, device and equipment and a storage medium, and the method comprises the steps: obtaining simulation analysis of a tested design file and excitation, obtaining a corresponding simulation result, analyzing a module occupying the most simulation time and memory according to the simulation result, and obtaining a simulation result; the method comprises the following steps of: decomposing a simulation process of a whole chip into a plurality of simulation operation tasks by combining a design requirement and a function definition of the chip; distributing the disassembled operation tasks to a multi-core processor for block simulation; and setting a dynamic performance optimization option DPO, performing multiple tests to collect data, and generating a simulation verification result based on a simulation result and an original design expectation. According to the method, the to-be-tested design is disassembled for layered compiling simulation, and the DPO is set for dynamic performance optimization, so that the simulation speed is increased, the chip design period is shortened, the development cost is reduced, and the requirement for rapid development of modern large-scale chips is met.

The invention discloses a band-gap reference source high-order curvature compensation method based on an operational amplifier, and belongs to the technical field of high-precision analog integrated circuit design, and the method comprises the steps: generating an absolute temperature proportion PTAT current and an absolute temperature complementary CTAT current; generating a high-order curvature compensation voltage based on the PTAT current and the CTAT current; amplifying the generated high-order curvature compensation voltage through an operational amplifier, and superposing the amplified high-order curvature compensation voltage to a band-gap reference output stage to obtain compensated band-gap reference output voltage; and carrying out band-gap reference output calibration on the compensated band-gap reference output voltage so as to ensure that the temperature drift coefficient of the output band-gap reference voltage in the preset temperature range is smaller than a preset threshold value. According to the invention, high-order elimination of base-emitter voltage nonlinearity can be realized in a wide temperature range, and a relatively low temperature coefficient and low noise are achieved.

The invention discloses a fault-considered spacecraft integrated chip interface circuit potential path analysis method, a storage medium and equipment, and belongs to the technical field of integrated circuit design and fault analysis. The method aims at solving the problem that an analysis method for a path under a failure mechanism under different environmental stresses is lacked. The method comprises the following steps: constructing an interface circuit simulation model of an integrated device based on a common interface circuit and a potential path structure in a spacecraft electronic system, then supplementing degradation mechanisms in various task stress environments, and determining a fault mode table of the interface circuit of the integrated device; a circuit simulation method is adopted to carry out potential path analysis considering fault factors on an interface circuit under a typical task profile, a fault path response feature library of the interface circuit under the task profile is obtained, then a constraint clue table for interface circuit design is formed, an interface circuit failure associated fault tree model is constructed, and the interface circuit failure associated fault tree model is constructed. And calibrating a relation path between various potential paths and device degradation or local failure for failure positioning and path checking.

The invention discloses a balanced three-valued dynamic logic gate implementation circuit based on memristors. The balanced three-valued dynamic logic gate implementation circuit comprises a balanced three-valued dynamic NOT gate circuit, a balanced three-valued dynamic NOR gate circuit and a balanced three-valued dynamic NAND gate circuit which are implemented according to the memristors. The dynamic logic circuit provided by the invention is widely applied to the design of a super-large-scale integrated circuit, and can reduce the circuit area and improve the circuit speed.

The invention relates to the technical field of data processing, and discloses an integrated circuit design optimization method and system based on data mining. The method comprises the following steps: extracting a multi-process node transistor parameter vector set through an EDA tool, performing data enhancement by using a double-layer process perception generative adversarial network to obtain a cross-node circuit sample library, and inputting the sample library into an R-PTT prediction model to obtain a performance prediction matrix; based on the matrix, optimizing through a multi-target genetic algorithm to obtain an optimal device size combination, and finally performing SPICE simulation verification to obtain verified integrated circuit design parameters. According to the method, the problems of data scarcity and poor model generalization ability during cross-process node application of an existing integrated circuit design optimization method based on data mining are solved, and the accuracy and efficiency of design optimization under new process nodes are improved.

The invention discloses an ultrahigh-precision low-noise band-gap reference circuit, and relates to the technical field of integrated circuit design, the ultrahigh-precision low-noise band-gap reference circuit comprises a starting turn-off circuit, a reference core circuit, a high-order temperature compensation circuit and a digital trimming circuit, the starting turn-off circuit is connected with the reference core circuit, and the high-order temperature compensation circuit is connected with the digital trimming circuit through a Brokaw type band-gap reference topological structure. Accurate compensation of the voltage is achieved through deep negative feedback of the operational amplifier and a high-order temperature compensation circuit, and the temperature drift of the reference voltage is as low as 0.5-2 ppm / DEG C (-40 DEG C to 130 DEG C) and is increased by 5-10 times compared with a traditional band-gap reference (5-10 ppm / DEG C). The power consumption of the system can be saved by turning off the circuit when the circuit is not used, meanwhile, the digital trimming module is added to replace laser trimming in traditional engineering, the upper limit of the trimming range is improved, high-order temperature compensation and the digital trimming circuit are introduced, the precision of output voltage is improved, different devices are replaced, and the noise of the circuit is reduced. The problems that a traditional high-voltage band-gap reference temperature coefficient is high and noise is large are solved.

The invention discloses a code generation method and system based on multi-objective reinforcement learning, and belongs to the technical field of digital integrated circuit design, and the method comprises the following steps: S1, generating an SFT training data set; s2, generating an MORL data set; s3, performing supervision and fine tuning on the model by taking the SFT training data set as input, so that the model masters the basic RTL code generation capability; s4, taking the MORL data set as input to train the model after supervision and fine tuning in the S3, and realizing multi-objective optimization; and S5, according to a user demand, describing a multi-target constraint through vector rewards, screening non-dominated candidate codes by using Pareto optimization to obtain an optimal RTL code, and outputting the optimal RTL code, vector reward details and a PPA equilibrium curve. According to the method and the system, basic constraints are met, and meanwhile generation of RTL codes with PPA indexes capable of being customized according to requirements is achieved.

The invention discloses a high-precision analog domain gain error shaping analog-to-digital converter and an implementation method thereof, and relates to the field of integrated circuit design. The high-precision analog domain gain error shaping analog-to-digital converter adopts a fully differential structure; comprising a first-stage sub analog-to-digital converter, a residual error amplifier and a second-stage sub analog-to-digital converter which are connected in sequence. A first-stage sub analog-to-digital converter is designed into a coarse-fine quantization architecture of an NS SAR ADC and a DAC, an input signal is sampled and quantized through the coarsely quantized NS SAR ADC to generate a first-stage digital code, and then the first-stage digital code is read to the finely quantized DAC. And the finely quantized DAC performs DAC array switching according to the first-stage digital code, and directly obtains the shaped first-stage quantization noise to realize gain error shaping. The method does not need to predict the first-stage quantization noise any more, solves the problem that the truncation error is not matched with the gain, and achieves a better gain error shaping effect.

A method is performed at least partially by a processor and includes, based on design specifications of a voltage regulator, determining parameters of the voltage regulator. The method further includes, based on the parameters of the voltage regulator, determining model parameters of a voltage regulator (VR) model of the voltage regulator. The VR model is free of non-linear circuit components. The method further includes performing a simulation of the voltage regulator, using the model parameters of the VR model.

The invention belongs to the technical field of analog integrated circuit design and memory read-write, and provides a multi-valued RRAM read-write circuit with a write-and-read function. The multi-valued RRAM read-write circuit is a multi-port device capable of performing read-write simultaneously, in write operation, a low dropout regulator is utilized to provide voltage for the RRAM circuit and the standard resistance circuit, mirror current is generated, the resistance value of the RRAM is set to be the total resistance of the standard resistance circuit, an operational amplifier is connected into the circuit through a CMOS switch, and feedback is formed to stabilize the voltage at the two ends of the RRAM; and in the read operation, the CMOS switch is used for disconnecting the operational amplifier, and the voltage at the two ends of the RRAM device is directly read. Compared with an existing multi-valued read-write circuit, the multi-valued RRAM read-write circuit has the advantages that write-and-read multi-valued RRAM read-write is realized, and meanwhile, the read-write circuit is not separated, so that the write-in speed is increased, and the area of the read-write circuit is saved.

The invention discloses a combinational logic clustering optimization method and system based on reinforcement learning. The method comprises the following steps: S1, counting fan-out information of registers and combinational logic units in a circuit netlist; s2, according to the fan-out information, screening out registers and combinational logic units of which the fan-out quantity is greater than a first preset threshold and the worst time sequence path time sequence violation value of the output signal is smaller than a second preset threshold, and generating a target unit list; s3, acquiring fan-out combinational logic information of each unit in the target unit list; s4, on the basis of the fan-out combinatorial logic information, clustering operation is carried out on fan-out logic units on the basis of a reinforcement learning algorithm; s5, after logic clustering is completed, revising the netlist of the circuit; after the revision is completed, carrying out equivalence check; and S6, rearranging and wiring the circuit according to the modified netlist. The method can effectively reduce key path delay, optimizes circuit performance, and is especially suitable for large-scale integrated circuit design.

The invention discloses a parameter determination method and device of an analog circuit, a medium and a product, and relates to the technical field of integrated circuit design. Local performance feedback and global topology perception of performance index parameters are used as input parameters, and pertinence and generalization ability of parameter adjustment are remarkably improved. Through a strategy function, a parameter candidate set of a target analog circuit is obtained, through multi-group sampling processing, variance of strategy gradient estimation is reduced, and training stability and convergence speed are improved. Depending on a value network is not needed, and training resource overhead is reduced. And applying the parameter candidate set output by the strategy function to the simulation processing scene to realize the accuracy of simulation processing evaluation. The target performance indexes are extracted from the simulation result, optimization of the performance indexes is achieved, the multiple target performance indexes are processed according to the multi-target reward function, balance selection and rejection are achieved in the multiple performance indexes, the parameter combination corresponding to the highest advantage value is obtained, and the reliability of the analog circuit parameter determination process is improved.

The invention relates to the technical field of integrated circuit design, computer system structures and embedded systems, in particular to a high-real-time interrupt management system and method based on an RISC-V. The system comprises an improved platform-level interrupt controller and an optimized processor internal interrupt processing unit. The system and the method are in tight coupling cooperative work through a special interruption field interface and a system bus, and the system further comprises a core local interrupter, an SRAM, an APB bus matrix and other components. The improved platform-level interrupt controller is responsible for sampling, gating, arbitration, flow control and direct memory access transmission of external interrupt, and a plurality of functional modules are arranged in the improved platform-level interrupt controller; an interrupt processing unit in the processor is responsible for hardware handshake, vector jump, nested control and tail biting mechanism implementation. Through hardware field management, multi-level priority arbitration, hardware nesting and tail biting mechanisms, delay and overhead caused by software intervention in a traditional architecture are eliminated, nanosecond response is achieved, the system throughput rate is increased, the software development threshold is lowered, and the method is suitable for strong real-time scenes.

A clock tree generated through clock tree synthesis (CTS) for an integrated circuit (IC) design is stored in memory. The IC design includes a post post-CTS clock tree that includes a plurality of clock nets. A request to add a user-specified clock instance to the post-CTS clock tree is received and all logically equivalent clock nets in the post-CTS clock tree detected to generate a set of candidate clock nets. A reduced set of candidate clock nets is generated from the set of candidate clock nets based on a distance between each candidate clock net and the clock instance. One candidate clock net in the reduced set is selected based on a length of conductive traces required to interconnect the corresponding candidate clock net and the clock instance. The post-CTS clock tree is restructured to connect the clock instance to the selected one of the candidate clock nets.

The invention relates to the field of integrated circuit design, and discloses an SAR ADC full-automatic size optimization design method based on formula constraint, which is used for solving the problems that the traditional manual design is low in efficiency, depends on experience and is difficult to optimize high-dimensional parameters. The method comprises the following steps: 1) establishing an analytic mapping relation between system-level indexes and sub-circuit specifications, and decomposing performance indexes to each sub-circuit module through a mathematical equation; 2) constructing a directed acyclic dependency graph, representing design variables by nodes, and representing constraint relationships by edges; 3) carrying out topological sorting on the dependency graph, and generating an execution sequence containing simulation verification, knowledge calculation and size optimization; and 4) adopting a double-layer optimization mechanism: verifying the performance of the sub-circuit and the system through circuit simulation, and performing iterative optimization until a device size scheme meeting all indexes is output when the performance does not reach the standard. According to the method, the full-automatic optimization design of the SAR ADC from the system index to the transistor size is realized.

The invention relates to the technical field of integrated circuit design, in particular to a latch circuit capable of effectively self-recovering three-node data flipping and a chip. The circuit comprises a pull-up tube part, a pull-down tube part, a signal inverting part, a clock control inverting part, a transmission tube part and a transmission gate part. According to the latch circuit capable of effectively self-recovering three-node data flipping provided by the invention, the eight storage nodes S1 to S8 are correspondingly reinforced by adopting a means of combining polarity reinforcement and source isolation reinforcement, and are matched with the signal inverting part, the clock control inverting part, the transmission tube part and the transmission gate part for use, so that the circuit has complete SNU, DNU and TNU self-recovery capability, and the reliability of the circuit is improved. And the power consumption is low. According to the invention, the problem that the existing circuit cannot reduce the power consumption under the condition of resisting SNU, DNU and TNU at the same time is solved.

The invention provides an intelligent clock gating NoC system based on AXI interconnection and a dynamic power consumption management method, and belongs to the technical field of integrated circuit design, the system is characterized in that an AXI interconnection matrix module is provided with a crossbar switch, a master port and a slave port, and the master port and the slave port are connected with the crossbar switch through an AXI bus; each router node in the 2D Mesh network module is provided with a local port and a peripheral port, and each router node is connected with an adjacent router node through the peripheral port; the intelligent clock gating module monitors the channel flow of the AXI interconnection matrix module and the data load of each router node in the 2D Mesh network module in real time, and dynamically controls a clock signal; and the dynamic power management module adjusts the power consumption state according to the global power optimization signal and the local optimization signal. The overall power consumption of the system-on-chip is reduced, and the stability and efficiency of data transmission are enhanced.