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2948 results about "Nano structuring" patented technology

A complementary field-effect transistor device

The disclosure relates to a CFET device (100) comprising: a bottom FET device (130) and a top FET device (140) stacked on top of the bottom FET device (130), the bottom FET device (130) comprising a bottom channel nanostructure (132) and a bottom gate electrode (134) comprising a side gate portion (134a) arranged along a first side surface (132a) of the bottom channel nano structure, and the top FET device (140) comprising a top channel nanosheet (142) and a top gate electrode (144) configured to define a tri-gate with respect to the top channel nanosheet and comprising a side gate portion (144b) arranged along a second side surface (142b) of the top channel nanosheet, wherein the side gate portion (134a) of the bottom gate electrode (134) defines a via contact portion protruding outside the top gate electrode (144) and the first side surface (142a) of the top channel nanosheet (142); and atop gate contact via (146) for coupling the top gate electrode (144) to a first conductive line (124) over the top FET device (140) and a bottom gate contact via (136) for coupling the via contact portion (134a) of the bottom gate electrode (134) to a second conductive line (128) over the top FET device (140).
Owner:INTERUNIVERSITAIR MICRO ELECTRONICS CENT (IMEC VZW) +1

ARVR resin wafer technology

The invention discloses an ARVR resin wafer process which comprises the following steps: preparing a to-be-detected resin wafer and a reference test piece, and carrying out positioning marking on a micro-nano structure area of the to-be-detected resin wafer to obtain a detection sample; performing multi-dimensional spectrum characterization on the detection sample and the reference test piece, determining a material non-uniform distribution area of the detection sample through comparative analysis, and obtaining molecular structure characterization data; carrying out stress field detection and dynamic response analysis on the material non-uniform distribution area to obtain mechanical property characterization data and high-risk defect points; carrying out microstructure and morphology analysis on the high-risk defect points to obtain defect feature data; and performing system evaluation according to the molecular structure characterization data, the mechanical property characterization data and the defect characteristic data to obtain a health degree evaluation result of the resin wafer. According to the technical scheme, multi-scale characteristic characterization can be carried out on the micro-nano structure area in the resin wafer for AR / VR, and systematic detection of the characteristics such as the molecular state, the interface stress and the phase change of the material is achieved.
Owner:东莞市元立光电股份有限公司

Chip cooling platform based on micro-nano structure

The disclosure discloses a chip cooling platform based on micro-nano structure, including a platform body, a cooling pipeline and an outer heat dissipation device, where the cooling pipeline is in a closed-loop structure, and part of the cooling pipeline is arranged in the platform body; the cooling pipeline is filled with cooling medium, and an inner wall of the cooling pipeline located in the platform body is provided with a turbulence structure; and a unidirectional hydraulic pump I is installed on the cooling pipeline arranged outside the platform body; the outer heat dissipation device is used for radiating the cooling medium in the cooling pipeline.
Owner:GUANGDONG OCEAN UNIVERSITY

Ultrahigh-transmittance anti-reflection multifunctional coated photovoltaic glass and preparation method thereof

The invention relates to ultrahigh-transmittance anti-reflection multifunctional coated photovoltaic glass and a preparation method thereof, and belongs to the technical field of photovoltaic glass, the photovoltaic glass comprises a photovoltaic glass substrate, the photovoltaic glass substrate is provided with a high-transmittance reflective coating, the high-transmittance reflective coating comprises a silicon dioxide layer, a titanium dioxide layer and a nanometer material layer, and the nanometer material layer is arranged on the silicon dioxide layer. The silicon dioxide layer and the titanium dioxide layer are arranged between the photovoltaic glass substrate and the nanometer material. The preparation method comprises the following steps: S1, preparing raw materials; s2, preparing a coating; s3, coating process; s4, performing surface treatment on the nano structure; s5, coating curing and surface treatment; and S6, testing and evaluating the performance. According to the ultrahigh-transmittance anti-reflection multifunctional coated photovoltaic glass, the performance and durability of a photovoltaic cell can be remarkably improved, by arranging the high-transmittance anti-reflection coating, the light transmittance of the photovoltaic glass is improved, the overall photoelectric conversion efficiency can be improved by 5-8%, and light reflection loss is remarkably reduced.
Owner:FLAT GLASS GROUP CO LTD

Manufacturing process of high-performance monocrystalline silicon nano wafer

The invention relates to the field of microelectronic manufacturing, and discloses a high-performance monocrystalline silicon nano wafer manufacturing process which comprises the following steps: preparing a monocrystalline silicon wafer, and obtaining a high-quality monocrystalline silicon wafer through fine cutting, chemical mechanical polishing and surface residual stress elimination treatment; multi-stage cleaning and surface treatment are carried out, and surface pollutants are removed through combination of molecular chromatography, electric field assisted ultrasonic cleaning and low-temperature plasma cleaning; and manufacturing a nano structure, and forming a complex nano structure by adopting multi-stage electron beam lithography, segmented reactive ion etching and self-adaptive deep etching regulation and control. The surface quality, the mechanical strength and the electrical property of the wafer are remarkably improved through the technologies of refined monocrystalline silicon wafer preparation, multi-stage cleaning, advanced nanostructure manufacturing, self-adaptive heat treatment and the like; and through surface functionalization and multi-layer high-precision packaging, the environmental tolerance and long-term reliability of the nanostructure are enhanced.
Owner:GUANG ZHOU NA WEI NA MI JI SHU YOU XIAN GONG SI

Rigid-flex circuit board slotting process based on laser depth control technology

The invention discloses a rigid-flex circuit board slotting process based on a laser depth control technology. The rigid-flex circuit board slotting process comprises the steps that the surface of a rigid layer of a rigid-flex circuit board is pretreated, and a laser sensitive layer is sprayed; cNC depth-controlled milling is adopted to form a grooved rough blank structure on the surface of the pretreated rigid layer; positioning laser is used for scanning, a three-dimensional model is established through collected reflected signals, then layered depth-controlled ablation is conducted, second-power laser is sequentially adopted for fine cutting, third-power laser is sequentially adopted for depth calibration, and a groove body structure is formed; cleaning an interface, scanning a groove bottom area and synchronously introducing low-temperature gas; performing morphology repairing treatment, and generating a periodic micro-nano structure on the groove wall by adopting short pulse laser to form a stress concentration resistant surface; depositing an insulating medium layer, and forming a continuous packaging protection layer on the groove wall and the bottom through a vacuum coating process; the high-precision depth-controlled slotting of the rigid-flex circuit board is realized, and meanwhile, the ultra-low thermal damage and anti-fatigue structure and long-acting environmental stability are realized.
Owner:SHEN ZHEN REN CHUANG YI ELECTRONIC CO LTD

Corrosion-resistant aluminum material for automobile and preparation method of corrosion-resistant aluminum material

The invention relates to the field of aluminum materials, and provides an automobile corrosion-resistant aluminum material and a preparation method thereof.The automobile corrosion-resistant aluminum material is prepared from cerium oxide loaded aluminum oxide nanorods, scandium / boron nitride nanotubes, zirconium powder, magnesium powder, copper powder, manganese powder, silicon carbide nanoparticles, TiB2 nanoparticles, aluminum powder and stearic acid. Wherein the cerium oxide loaded aluminum oxide nanorod is composed of an aluminum oxide nanorod and cerium oxide nanoparticles loaded on the surface of the aluminum oxide nanorod, and the scandium / boron nitride nanotube is composed of a boron nitride nanotube and a scandium nanolayer uniformly coated on the surface of the boron nitride nanotube. The material is prepared through mechanical ball milling, cold isostatic pressing forming, vacuum sintering and aging treatment, and finally the aluminum-based composite material containing the Al3Sc nano precipitated phase and the boron nitride nanotube reinforced phase is formed. And an Al3Sc precipitated phase and an aluminum matrix form a coherent interface, so that the strength, the corrosion resistance and the wear resistance of the material are improved. Through nanostructure optimization, high performance of the aluminum alloy is achieved, and the aluminum alloy is suitable for the fields of automobiles, aerospace and the like.
Owner:ZHAOQING XINLIANCHANG METAL IND CO LTD

Semiconductor device with isolation transistors and back side voltage metal lines

A semiconductor device includes circuit cells, isolation transistors at cell boundaries of the circuit cells, a first metal line under the isolation transistors, and connection structures connecting gate structures of the isolation transistors to the first metal line. Each of the circuit cells includes functional transistors having source / drain features and nanostructures. The isolation transistors electrically isolate the circuit cells from each other. Nanostructures of the isolation transistors, the source / drain features of the functional transistors, and the nanostructures of the functional transistors are connected with each other into a continuous rectangular shape from a top view.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

Strengthening device and processing method for improving fatigue, wear and corrosion performance of metals

Disclosed are a strengthening device and method for improving fatigue, wear and corrosion performance of metals. In the present disclosure, a femtosecond laser device, an optical transmission module, an optical platform, a five-axis mobile platform, a femtosecond laser processing head, and a central processing unit are included, where laser scanning processing is completed by means of the synergy of the five-axis mobile platform and a scanning galvanometer. A femtosecond laser processing process method for regulating and controlling shock wave pressure and surface self-organizing structure characteristics is proposed by the present disclosure, where a work-hardening layer and a wear-resistant and hydrophobic micro-nano structure are prepared on a surface of the metal in one step by means of the femtosecond laser, and simultaneous improvement of the fatigue, wear and corrosion performance of the metals is achieved.
Owner:AIR FORCE UNIV PLA

Stacked transistor isolation features and methods of forming the same

In an embodiment, a method includes: patterning a lower semiconductor nanostructure, an upper semiconductor nanostructure, and a dummy nanostructure, the dummy nanostructure disposed between the lower semiconductor nanostructure and the upper semiconductor nanostructure, the dummy nanostructure including doped silicon; forming an opening between the lower semiconductor nanostructure and the upper semiconductor nanostructure by etching the doped silicon of the dummy nanostructure; forming an isolation structure in the opening; and depositing a gate dielectric around the isolation structure, the upper semiconductor nanostructure, and the lower semiconductor nanostructure.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

Amorphous tungsten superconducting nanowire single-photon detector

The invention discloses an amorphous tungsten superconducting nanowire single-photon detector, which comprises a photosensitive component, and is characterized in that the photosensitive component is an amorphous tungsten superconducting nanowire; the amorphous tungsten superconducting nanowire is prepared by the following steps: (1) growing an amorphous tungsten film on a substrate; and (2) etching the amorphous tungsten film into a roundabout nanowire structure by using electron beam exposure and reactive ion etching methods to obtain the amorphous tungsten superconducting nanowire. According to the invention, the tungsten nanowire with good stability is used as the main body material of the SNSPD, so that the robustness of the SNSPD preparation process is improved, and the service life of the SNSPD device in practical application is prolonged.
Owner:NANJING UNIV +1

Semiconductor device

A semiconductor device includes circuit cells having transistors. Each of the transistors includes nanostructures vertically stacked from each other in a Z-direction, a gate structure wrapping around the nanostructures and extending in a Y-direction, and source / drain features on opposite sides of the gate structure in an X-direction. The semiconductor device further includes silicide features over and in contact with the source / drain features. The silicide features extend lower than bottom surfaces of topmost nanostructures of the nanostructures. The semiconductor device further includes source / drain contacts over and in contact with the silicide features. Each of bottom surfaces of the source / drain contacts has a V-shape in an X-Z cross-sectional view.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

On-chip metasurface and multi-dimensional multiplexing holographic method based on on-chip metasurface

The invention belongs to the technical field of micro-nano optics, and discloses an on-chip metasurface and a multi-dimensional multiplexing holographic method based on the on-chip metasurface. Firstly, a unit structure of the on-chip metasurface is constructed, the unit structure comprises a substrate layer, an optical waveguide layer and a nanometer structure layer which are sequentially arranged from bottom to top, and the nanometer structure layer comprises a nanometer brick of a rectangular structure; a plurality of nano bricks with the same size contained in the on-chip metasurface form a nano brick array; and then according to a plurality of set target holographic images, the arrangement of the position and the corner of each nano brick in the nano brick array is obtained by using the combined coding of the circuitous phase and the geometric phase, a final on-chip metasurface is obtained after the arrangement is completed, and the three-dimensional multiplexing holography of the incident angle, the wavelength and the polarization is realized by using the on-chip metasurface. According to the invention, not only is the limitation of incidence in the orthogonal direction overcome, but also the information storage capacity and the information security are remarkably improved.
Owner:WUHAN UNIV

Surface modified carbon fiber as well as preparation method and application thereof

The invention provides a surface modified carbon fiber as well as a preparation method and application thereof, and belongs to the technical field of battery materials. Physical or chemical treatment on the surface of the carbon fiber is realized by performing one or more of accurate plasma treatment, chemical etching, coupling agent treatment and nano particle deposition on the surface of the carbon fiber, so that functional groups are introduced or a rough nano structure is formed; a functional layer with a specific functional group and a rough structure which are beneficial to attachment of positive electrode material slurry are formed on the surface of the carbon fiber, and then a stable and well-attached surface modified layer is obtained through heat treatment, so that the surface modified carbon fiber is prepared. According to the method disclosed by the invention, the surface roughness and the functional group richness can be improved on the premise that the mechanical property of the fiber is not obviously damaged, so that the adhesiveness and the electrical property of the positive electrode material slurry are enhanced, and a foundation is laid for the preparation of a carbon fiber positive electrode material and a structure-energy storage integrated composite structure.
Owner:SHENZHEN NO 1 FINE CHEM CO LTD

Multi-level micro-nano structure flexible wearable pressure sensor inspired by skin and preparation method and application thereof

The invention discloses a multi-stage micro-nano structure flexible wearable pressure sensor inspired by skin, and a preparation method and application of the multi-stage micro-nano structure flexible wearable pressure sensor. The sensor is composed of a piezoresistive layer, an electrode layer and a packaging layer. The piezoresistive layer takes polydimethylsiloxane (PDMS) as a flexible substrate, a submillimeter-level cylindrical array main structure and a micron-level skin-like spinous secondary microstructure randomly distributed at the top end of the submillimeter-level cylindrical array main structure are constructed through a composite mold, and a nano-level conductive network is formed by adopting an MXene / MWCNT hybrid material through a dispensing process, so that multi-scale stress synergistic response is realized; the electrode layer takes a degradable lignocellulose biological plastic film prepared from bagasse as a base material, and a silver paste interdigital electrode is loaded through a screen printing process; the packaging layer is fully coated with a medical-grade polyurethane (PU) film so as to ensure signal stability. The sensor shows ultrahigh sensitivity, wide detection range and low detection limit through the synergistic effect of the submillimeter-micron-nano multilevel structure, and can be applied to the fields of human motion monitoring, intelligent electronic skin and the like.
Owner:QUFU NORMAL UNIV

Liquid metal enhanced triboelectric material with bionic surface and preparation method of liquid metal enhanced triboelectric material

The invention discloses a liquid metal enhanced triboelectric material with a bionic surface and a preparation method of the liquid metal enhanced triboelectric material, and belongs to the technical field of triboelectric materials. The preparation method comprises the following steps: mixing an interface stabilizer TEMPO oxidized nanocellulose with a liquid metal gallium-indium alloy to obtain TOCNF (at) LM liquid metal-based micro-nano liquid drops; and doping the obtained TOCNF-coated LM liquid metal-based micro-nano liquid drops into a base material waterborne polyurethane, and constructing a bionic rose petal micro-mastoid process structure by adopting a template method, so as to obtain the liquid metal enhanced triboelectric material with a bionic surface. The composite material with the rose petal micro-nano structure is prepared through bionic design, the micro-mastoid structure of rose petals is successfully re-carved, and the triboelectric property of the waterborne polyurethane is remarkably improved by utilizing TOCNF at LM liquid metal-based micro-nano liquid drops, so that the open-circuit voltage of the prepared composite material reaches 250V, the short-circuit current reaches 8.19 mu A, and the triboelectric property of the waterborne polyurethane is remarkably improved. The short-circuit transfer charge quantity reaches 95nC, and theoretical and practical guidance is provided for the design of a high-performance triboelectric material.
Owner:GUANGXI UNIV

Silicon carbide MOSFET high-temperature ion implantation method and device

The invention relates to the technical field of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) preparation, and discloses a silicon carbide MOSFET high-temperature ion implantation method and a silicon carbide MOSFET high-temperature ion implantation device. According to the method, a substrate is pretreated, specification and performance parameters are obtained, a high-temperature ion implantation scheme is designed according to the parameters, a nano structure is prepared on the surface of the substrate to guide ion implantation, and the substrate is heated to a working state. According to the method, high-temperature ion implantation is carried out through the nanostructure, implantation effect data are collected and analyzed in real time, and the implantation effect is optimized by adjusting parameters until preparation of the substrate in the intermediate state is completed. The problem that in the prior art, precision of high-temperature ion implantation of silicon carbide is insufficient is solved.
Owner:SHENZHEN XINDIANYUAN TECH CO LTD

Metal organic framework material, preparation method thereof and perovskite battery

The invention discloses a metal organic framework material, a preparation method thereof and a perovskite battery, and belongs to the technical field of perovskite batteries. The preparation method comprises the following steps: dissolving 1, 2, 4, 5-benzene tetracarboxylic acid in an organic solvent, adding ZrCl4 and a regulator acetic acid, carrying out a heating reaction to obtain a reactant, and carrying out centrifugation, washing and vacuumizing on the reactant to obtain the metal organic framework material. The metal organic framework material has high-density free carboxyl and a nano structure, the high-density free carboxyl can achieve the purpose of adsorbing lithium ions, and the nano structure can obtain better dispersity. When the metal organic framework material is applied to a hole transport layer of a perovskite battery, lithium ions can be well adsorbed, free carboxyl groups can also form chemical bonds with Pb ions of a perovskite active layer, surface defects and unsaturated bonds of the perovskite active layer are reduced, compounding of electrons and holes is prevented, and the performance of the perovskite battery is improved. Therefore, the electrochemical performance and the stability of the perovskite battery are improved.
Owner:旗滨新能源发展(深圳)有限责任公司

Method for preparing iron-nickel-molybdenum electrocatalyst through combination of electrodeposition and rapid Joule heat and application of iron-nickel-molybdenum electrocatalyst

The invention discloses a method for preparing an iron-nickel-molybdenum-based electrocatalyst through combination of electrodeposition and rapid Joule heat and application of the method. The method comprises the steps that S1, a porous nickel substrate is pretreated, and the pretreated porous nickel substrate is obtained; s2, obtaining a nickel salt solution, a molybdenum salt solution and a ferric salt solution; s3, obtaining a mixed solution; s4, putting the mixed solution serving as electrolyte into a dual-electrode electrolytic tank, carrying out electro-deposition treatment by taking the pretreated porous nickel substrate as a cathode and an inert electrode as an anode, and washing and drying to obtain a Fe-Ni-Mo-LDH precursor; and S5, carrying out Joule thermal pyrolysis treatment on the Fe-Ni-Mo-LDH precursor, so as to obtain the iron-nickel-molybdenum based electrocatalyst. The preparation method can effectively regulate and control the size structure of the catalyst, and is suitable for preparing iron-nickel-molybdenum-based electrocatalysts with different substrates and different sizes; and the electrocatalyst has the advantages of uniform and stable nanostructure and high loading capacity. Meanwhile, the preparation method is short in reaction time, high in heating efficiency, high in repeatability and suitable for industrial large-scale production.
Owner:OCEAN UNIV OF CHINA

On-chip metasurface and design method thereof, and method for realizing color routing based on on-chip metasurface

The invention belongs to the technical field of micro-nano optics, and discloses an on-chip metasurface and a design method thereof, and a method for realizing color routing based on the on-chip metasurface. A unit structure of the on-chip metasurface comprises a nano structure layer, an optical waveguide layer and a dielectric substrate layer, wherein the nano structure layer is composed of diatomic nano bricks and has geometric asymmetry; a plurality of diatomic nano bricks contained in the on-chip metasurface form one or more groups of nano brick arrays; the geometric sizes of all diatomic nano bricks contained in each group of nano brick arrays are the same, and the geometric sizes of the diatomic nano bricks contained in different groups of nano brick arrays are different; each group of nano brick arrays is used for selectively extracting a certain narrow-band spectrum, and the nano brick arrays of different groups are used for selectively extracting different spectrum ranges; and coding the color information of the image into the on-chip metasurface by taking the geometric dimension of the diatomic nano brick as an adjusting parameter. According to the invention, wavelength selective extraction and multicolor routing image display are realized based on the on-chip metasurface.
Owner:WUHAN UNIV

Preparation method of proton exchange membrane water electrolysis hydrogen production membrane electrode

The invention discloses a preparation method of a proton exchange membrane water electrolysis hydrogen production membrane electrode, and belongs to the technical field of proton exchange membranes, a catalyst carrier is prepared, S101, a polyimide membrane is inversely fixed in a magnetron sputtering vacuum coating chamber, a cavity cover of the magnetron sputtering vacuum coating chamber is closed, vacuumizing is performed, and a substrate is heated; and S102, argon is introduced into a cavity of the magnetron sputtering vacuum coating chamber, coating is started, the power of the bismuth metal target is set to be 0.2-0.5 kW, and the deposition time is 60-1800 s. In the invention, the physical vapor deposition method is utilized to load the catalyst on the surface of the metal oxide carrier with high specific surface area and ordered nanostructure, so that the exposure of active sites of the catalyst is increased, the dosage of the noble metal catalyst is reduced, and the bonding strength between the catalyst and the carrier is enhanced; the catalyst is not easy to separate from the surface of the carrier, and large-scale slurry agglomeration is avoided.
Owner:HUAXIN CHUANGNENG (GUANGDONG) TECHNOLOGY CO LTD

Low Ge isolated epitaxial layer growth over nano-sheet architecture design for RP reduction

A nano-FET and a method of forming is provided. In some embodiments, a nano-FET includes an epitaxial source / drain region contacting ends of a first nanostructure and a second nanostructure. The epitaxial source / drain region may include a first semiconductor material layer of a first semiconductor material, such that the first semiconductor material layer includes a first segment contacting the first nanostructure and a second segment contacting the second nanostructure, wherein the first segment is separated from the second segment. A second semiconductor material layer is formed over the first segment and the second segment. The second semiconductor material layer may include a second semiconductor material having a higher concentration of dopants of a first conductivity type than the first semiconductor material layer. The second semiconductor material layer may have a lower concentration percentage of silicon than the first semiconductor material layer.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

Methods of forming transistor source / drain regions comprising carbon liner layers

In an embodiment, a device includes: a first nanostructure; a source / drain region adjoining a first channel region of the first nanostructure, the source / drain region including: a main layer; and a first liner layer between the main layer and the first nanostructure, a carbon concentration of the first liner layer being greater than a carbon concentration of the main layer; an inter-layer dielectric on the source / drain region; and a contact extending through the inter-layer dielectric, the contact connected to the main layer, the contact spaced apart from the first liner layer.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

Semiconductor memory devices with dielectric fin structures

A device includes a memory cell that randomly presents either a first logic state or a second logic state. The memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

Anode material for adipic acid monoester electrolysis and preparation method thereof

The invention discloses an anode material for adipic acid monoester electrolysis and a preparation method of the anode material, the electrode solves the key problems that a platinum layer is easy to fall off, the catalytic activity is low, the organic matter poisoning resistance is poor and the like of a traditional titanium platinum-plated electrode through multi-scale interface strengthening and nano structure regulation and control; the preparation method comprises the following core steps: constructing a porous ZrO2-TiO2 composite oxide layer on the surface of a titanium substrate by adopting a micro-arc oxidation-hydrothermal composite process, and generating platinum nanoparticles in situ to pre-fill pores, so that the anchoring effect of a platinum layer is remarkably enhanced; depositing a platinum / carbon nano tube (Pt / CNT) composite catalyst layer on the surface of the oxide layer through a pulse-ultrasonic synergistic electroplating technology, wherein the carbon nano tube is used as a conductive framework to inhibit platinum agglomeration; through vacuum annealing and electrochemical activation treatment, the interface bonding force and active site exposure are further optimized; the electrode shows excellent performance in an adipic acid monoester electrolysis system, and efficient electrocatalytic conversion from adipic acid monomethyl ester to dimethyl sebacate is achieved.
Owner:宿迁联盛助剂有限公司

Integrated circuit with nanostructure transistors and bottom dielectric insulators

An integrated circuit includes a first nanostructure transistor including a plurality of first semiconductor nanostructures over a substrate and a source / drain region in contact with each of the first semiconductor nanostructures. The integrated circuit includes a second nanostructure transistor including a plurality of second semiconductor nanostructures and a second source / drain region in contact with one or more of the second semiconductor nanostructures but not in contact with one or more other second semiconductor nanostructures.
Owner:TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

Preparation method, application and testing device and method of high-temperature heat dissipation material Ti-6Al-4V

The invention relates to a high-temperature heat dissipation material Ti-6Al-4V and a preparation method, application and a testing device and method thereof, and the method comprises the following steps: ablating a polished and cleaned Ti-6Al-4V material by using a femtosecond laser, and preparing a series of parallel grooves in the surface of the material by using accurate laser parameters, the depth of the grooves being 56 [mu] m, and the distance between the adjacent grooves being 90 [mu] m; performing a vertical evaporation test on the prepared Ti-6Al-4V material at a high temperature to obtain evaporation rates and water film states of the Ti-6Al-4V material at different temperatures; benefited from rich micro-nano structures on the surface of the Ti-6Al-4V material, the Ti-6Al-4V material shows good water absorption and evaporation functions under an extreme high-temperature condition, the test temperature breaks through the 150 DEG C high-temperature limit of the current M-cycle, a gate is opened for higher-temperature M-cycle technology application, and the material has good application prospects. And the heat dissipation requirements of high-temperature scenes such as an industrial cooling system and a nuclear power station are met.
Owner:CHONGQING UNIV OF POSTS & TELECOMM

Preparation method of nano needle tip split ring 3D structure periodic array

The invention belongs to the field of micro-nano structures, and relates to a preparation method of a nano needle tip split ring 3D structure periodic array. According to the method, after a reflecting layer and a supporting layer are deposited on a silicon substrate, polystyrene nanospheres are self-assembled, the volume of the nanospheres is reduced through reactive ion etching, then two times of inclined magnetron sputtering are carried out, deposited precious metal is etched through a reactive ion etching machine, and the silicon substrate is obtained. And removing the nanosphere mask to obtain the 3D structure periodic array of the nanotip split ring. The method has the characteristics of simple preparation process, good uniformity, high order degree and strong repeatability, and has wide application potential in the fields of SERS (Surface Enhanced Raman Scattering), photoelectric property detection and the like.
Owner:HANGZHOU DIANZI UNIV +2