141 results about "Chemical-mechanical planarization" patented technology

Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates; low oxide trench dishing, and high oxide: SiN selectivity. Dual chemical additives comprise at least one silicone-containing compound comprising at least one of (1) ethylene oxide and propylene oxide (EO-PO) group, and at least one of substituted ethylene diamine group on the same molecule; and (2) at least one non-ionic organic molecule having at least two, preferably at least four hydroxyl functional groups.

Various techniques and apparatus permit fabrication of superconductive circuits. A niobium / aluminum oxide / niobium trilayer may be formed and individual Josephson Junctions (JJs) formed. A protective cap may protect a JJ during fabrication. A hybrid dielectric may be formed. A superconductive integrated circuit may be formed using a subtractive patterning and / or additive patterning. A superconducting metal layer may be deposited by electroplating and / or polished by chemical-mechanical planarization. The thickness of an inner layer dielectric may be controlled by a deposition process. A substrate may include a base of silicon and top layer including aluminum oxide. Depositing of superconducting metal layer may be stopped or paused to allow cooling before completion. Multiple layers may be aligned by patterning an alignment marker in a superconducting metal layer.

The invention provides a wafer cleaning and drying method, which comprises the following steps of: S100, feeding a wafer subjected to chemical planarization treatment into a pre-cleaning station, and pre-cleaning the wafer by adopting a pre-cleaning solution; s200, feeding the pre-cleaned wafer into a megasonic cleaning station, and performing megasonic cleaning on the wafer; s300, feeding the wafer subjected to the step S200 into a first cleaning station, and cleaning the wafer by adopting a first cleaning solution; s400, feeding the wafer subjected to the step S300 into a second cleaning station, and cleaning the wafer by adopting a second cleaning solution; s500, putting the wafer subjected to the step S400 into a spin-drying station, and removing residual liquid on the wafer; s600, putting the spin-dried wafer into a wafer box; in the step S200 and / or the step S300, the cleaned wafer is sent to a spin-drying station, and residual liquid on the wafer is removed. The wafer cleaning and drying method provided by the invention aims to solve the problems that stains remain on the surface of a wafer and the yield is relatively low due to the fact that the existing wafer is not thoroughly cleaned.

The utility model provides chemical mechanical planarization equipment, and belongs to the technical field of semiconductor device manufacturing. The chemical mechanical planarization equipment comprises a front end unit, a cleaning unit, a polishing unit, a first transfer assembly arranged between the front end unit and the cleaning unit, a second transfer assembly arranged on the cleaning unit and a third transfer assembly arranged on the polishing unit which are sequentially arranged along a first linear path, the number of the cleaning units is equal to that of the polishing units, each polishing unit comprises a rotating frame, a plurality of polishing heads fixedly connected to the rotating frame and a plurality of polishing tables located below the polishing heads, and the polishing heads are evenly distributed on a rotating shaft of the rotating frame in a sleeving mode. The number of the polishing tables is one less than that of the polishing heads so as to form a loading and unloading position, the third transfer assembly is provided with a first working point position and a second working point position, and the first working point position is the loading and unloading position.

The invention discloses a wafer chemical-mechanical planarization control system, which is characterized by comprising a chemical-mechanical planarization system, a chemical-mechanical planarization control system, a chemical-mechanical planarization control system, a chemical-mechanical planarization control system and a chemical-mechanical planarization control system, the integrated detection system is used for acquiring wafer flatness information; the APC data analysis system is used for acquiring wafer flatness information of the integrated detection system and wafer polishing process parameters of the control system and generating the wafer polishing process parameters; and the control system is used for inputting wafer polishing process parameters and feeding back the wafer polishing process parameters to the chemical mechanical planarization system for polishing the next wafer. The invention also discloses a wafer chemical mechanical planarization control method. The APC data analysis system is introduced into detection of the CMP polishing effect, the measured value can be fed back to the chemical mechanical planarization system in time, the technological parameters of the chemical mechanical planarization system are corrected in time, equivalently, the technological parameters are corrected according to the difference of the real-time state of the chemical mechanical planarization system, and the overall polishing effect is better.

The present invention provides a method for in-situ measurement of film thickness and a chemical mechanical planarization device, the method comprising: on the basis of a reflection spectrum of a wafer film and an equivalent light source spectrum, generating an actually measured spectrum, the equivalent light source spectrum being data of the correspondence relationship between wavelength and light intensity generated by using reflected light passing through a planarization solution and a dielectric layer between the planarization solution and a collimating light source probe; matching the actually measured spectrum with a reference spectrum library; and obtaining a wafer film thickness corresponding to a reference spectrum matching the actually measured spectrum and using said thickness as a measurement result.

The present disclosure relates to a method for manufacturing a pixel that includes depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; performing chemical mechanical planarization up to the insulating layer, a portion of the electrode layer left in place in the opening forming an electrode; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

A chemical mechanical polishing (CMP) slurry can comprise a plurality of particles distributed in a carrier, wherein at least a portion of the particles of the plurality of particles can have a body including a core comprising zirconia and a shell overlying at least a portion of the core, wherein the shell comprises silica; an oxidizing agent; and a carrier. The CMP slurry can comprise at least one of a Hydrogen Peroxide Stability %Reduction of not greater than 50%; and a high copper material removal rate.

A chemical mechanical planarization (CMP) system utilizes a high-pressure rinsing fluid with nanobubbles to assist in conditioning of a CMP pad. The CMP system generates nanobubbles in the rinsing fluid prior to dispensing the rinsing fluid onto the CMP pad or while the rinsing fluid is on the CMP pad. The CMP system includes a pad dresser that dresses or conditions the CMP pad while the rinsing fluid and the nanobubbles are present.

The invention relates to a liquid wall device, chemical mechanical planarization equipment and a method, the chemical mechanical planarization equipment comprises the liquid wall device, and the liquid wall device comprises a spray head which is arranged close to a panel of the chemical mechanical planarization equipment; the pipeline is communicated with the spray head and used for supplying cleaning liquid to the spray head, and the spray head extends from the pipeline to the panel; and the liquid blocking piece comprises a blocking shed arranged below the spray head, and the blocking shed extends from the position close to the panel to the middle of the chemical mechanical planarization equipment. According to the invention, the cleaning liquid is sprayed to the panel of the chemical mechanical planarization equipment through the nozzle, so that the Slurry can be prevented from forming crystals on the panel, and product defects caused by the crystals are avoided. And the cleaning liquid drops far away from the panel are blocked through the liquid blocking piece, so that the cleaning liquid drops are prevented from falling into a Slurry used in the grinding process, and the negative influence on the grinding effect is prevented.

A polishing apparatus, specifically for performing chemical mechanical planarization on an object such as a substrate, which may be a semiconductor wafer. The polishing apparatus may include a rotatable polishing pad having an axial center of rotation and a slurry delivery conduit configured to introduce polishing slurry through said axial center of rotation. The polishing slurry may be configured to be dispensed directly beneath the rotatable polishing pad to enable localized polishing of a surface of a substrate located below or beneath the rotatable polishing pad.

The present invention relates to a gate sidewall structure, a manufacturing method thereof and a DRAM, belonging to the field of semiconductor manufacturing technology, and is used to solve the problems of small spacing between gates and poor device reliability caused by existing processes. The gate sidewall structure includes: a semiconductor substrate; a gate located on the semiconductor substrate; a gate sidewall located on the sidewall of the gate; the outer side surface of the gate sidewall is a curved surface concave toward the gate sidewall. The manufacturing method of the gate sidewall includes: providing a semiconductor substrate; forming a gate material layer on the substrate, etching the gate material layer to form a gate of a transistor; forming a gate sidewall material layer on the semiconductor substrate and the gate; forming an oxide insulating film on the gate sidewall material layer; performing a first chemical mechanical planarization treatment on the oxide insulating film and the gate sidewall; and performing a second chemical mechanical planarization treatment on the oxide insulating film and the gate sidewall. The present invention increases the voltage between gates and improves device reliability.

The invention relates to the technical field of semiconductor manufacturing, and discloses a chemical mechanical planarization method and a chemical mechanical planarization device.The chemical mechanical planarization method comprises the steps that a to-be-planarized structure is provided, the to-be-planarized structure comprises a substrate layer and a sacrificial layer, a groove is formed in the substrate layer, the sacrificial layer is located on the surface of one side of the substrate layer, and the sacrificial layer is located on the surface of the other side of the substrate layer; the sacrificial layer fills the groove; performing a chemical mechanical planarization step on the surface of one side, deviating from the substrate layer, of the sacrificial layer according to the first process parameter; performing a chemical mechanical planarization step on the surface of one side, deviating from the substrate layer, of the sacrificial layer according to a second process parameter; and when the thickness of any area of the sacrificial layer located on the substrate layer is reduced to zero, the polishing head sets the pressure value applied to the corresponding area of the sacrificial layer to be zero. And when the thickness of any area of the sacrificial layer located on the substrate layer is reduced to zero, the polishing head sets the pressure value applied to the corresponding area of the sacrificial layer to be zero, and the situation that the polishing head continues to polish the area is avoided.

Disclosed in the present invention are a low-dielectric-absorption, low-mismatch, precision, linear MIM capacitor and integration technology. The integration technology comprises the integration steps of: 1) forming an active region and an isolation field oxide region; 2) forming a thick gate oxide layer and a thin gate oxide layer; 3) depositing a polysilicon layer and constructing a polysilicon gate of an MOS transistor; 4) completing photolithography and implantation of a source and a drain for a multi-gate oxide high-low voltage BiCMOS / CMOS; 5) improving the flatness of the lower surface region of a metal thin film resistor by means of chemical mechanical planarization; 6) sputtering a high-resistivity microcrystalline titanium thin film on a lower electrode of a metal MIM capacitor by means of a PVD method; 7) depositing a silicon nitride SixNyHz as a dielectric layer of the metal MIM capacitor by means of PECVD; 8) sputtering the high-resistivity microcrystalline titanium thin film on an upper electrode of the metal MIM capacitor by means of a PVD method; and 9) sputtering an aluminum-copper film layer and completing etching processing of a metal connection line. The present invention optimizes the problem of precision matching of metal MIM capacitors, improves the packaging function density and the device density of integrated circuits, and promotes the miniaturization and reduced form of high-performance integrated circuits.

Carriers for polishing workpieces with flats or voids are provided. In one aspect, a substrate carrier head for a chemical mechanical planarization (CMP) system include a carrier body comprising an aperture configured to receive a wafer and a membrane having a first surface configured to contact a surface of the wafer and a second surface opposing the first surface, the membrane having a primary zone and a secondary zone. The substrate carrier head further includes a membrane cavity formed along the second surface and configured to apply pressure to the membrane within the primary zone, and a membrane support plate configured to support the secondary zone of the membrane.

A chemical mechanical planarization (CMP) composition is provided that provides a tunable high Cu removal rate and a low Cu static etch rate for polishing a wide range of bulk or advanced node copper or silica through vias (TSVs). The CMP composition also provides high selectivity of Cu films over other barrier layers such as Ta, TaN, Ti, TiN, and SiN, and dielectric films such as TEOS, low-k, and ultra low-k films. The CMP composition includes an abrasive, an oxidizer, and at least two chelating agents selected from the group consisting of amino acids, amino acid derivatives, and combinations thereof, and the Cu static etch rate reducer includes, but is not limited to, organic alkyl sulfonic acids with linear or branched alkyl chains, and salts of organic alkyl sulfonic acids.

The invention provides a manufacturing method of a capacitor structure. The method comprises the following steps: sequentially forming a first conductive layer, a capacitor dielectric layer and a second conductive layer on a substrate; a protection mask is formed on the second conductive layer before a subsequent processing process in a flash memory device manufacturing process is executed by adding a special photoetching process once. The protective mask shields and protects the capacitor structure in a subsequent processing process, so that the top surface of the capacitor structure is prevented from being affected, and the flatness of the capacitor structure is maintained. According to the method, only one photoetching mask needs to be added, the damage of chemical mechanical planarization and other processes to the flatness of the capacitor structure can be effectively avoided, and therefore the capacitor structure higher in stability and precision is obtained.

A method includes identifying a substrate thickness map of a substrate thinned via one or more chemical mechanical planarization (CMP) operations. The method further includes causing, based on the substrate thickness map, additional thinning of the substrate via etching of the substrate.

A colloidally stable amphiphilic abrasive particle dispersion comprising amphiphilic abrasive particles is provided. The surface of each colloid-stabilized amphiphilic abrasive particle comprises a hydrophilic portion and a hydrophobic portion. Chemical mechanical planarization (CMP) polishing compositions, methods, and systems using the colloid-stabilized amphiphilic abrasive particle dispersions are also provided. The CMP composition provides a high removal rate of tungsten (W), suppresses the removal rate of silicon oxide (TEOS), and thus has excellent W: TEOS selectivity for chemical mechanical planarization of the tungsten surface.

This invention provides a chemical mechanical planarization method and apparatus for semiconductor manufacturing processes to achieve planarization. [Solution] According to one embodiment of the present invention, the technical gist of the present invention is a chemical mechanical planarization method in a semiconductor manufacturing process, which involves applying an electric field to the wafer surface using electrophoretic phenomena during a CMP (Chemical Mechanical Planarization) process to control the distribution of charged particles in a slurry, and a chemical mechanical planarization apparatus for a semiconductor manufacturing process, which includes CMP equipment for performing a CMP process to planarize the wafer surface, and an electric field application control unit for applying an electric field to the wafer surface during the CMP process.

A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

A Chemical Mechanical Planarization (CMP) system, apparatus, and method comprising providing a source of CMP slurry; modifying the source of CMP slurry to form a modified CMP slurry by directing a source of at least one of mechanical or electromagnetic wave energy at the source of CMP slurry; applying a flow of the modified CMP slurry to a wafer polishing apparatus at which a substrate is positioned; and performing a polishing operation on the substrate.

The present invention discloses a wafer backside thinning method based on a BSI process, belonging to the field of semiconductor manufacturing technology, and comprising the following steps: (1) providing a wafer to be thinned; (2) thinning the wafer to a target thickness by adopting a thinning process; (3) forming an oxide layer on the surface of the thinned wafer and performing a chemical mechanical flattening treatment; (4) laying a silicene layer on the flattened wafer thinned surface and then performing an annealing treatment. Based on the existing thinning process method, the present invention performs surface oxidation and flattening treatment on the back side of the wafer thinned to the target thickness, and then lays a silicene layer and performs annealing to improve the flatness of the back side of the wafer after completing the wafer backside thinning process.

The invention provides a manufacturing method of a zero-layer alignment mark suitable for a multi-material active region substrate. The method comprises the following steps: forming a first dielectric layer on a substrate with a zero-layer alignment mark region and a channel region; etching the zero layer alignment mark area, and forming a groove in the substrate; forming a second dielectric layer for blocking epitaxial growth on the inner surface of the groove and the channel region; chemical mechanical planarization is carried out on the second dielectric layer, so that the second dielectric layer is reserved in the groove to form a lining; and removing the first dielectric layer. According to the method, the dielectric layer lining is formed in the zero-layer alignment marked groove in advance, so that the epitaxial material in the subsequent multi-material active region process is effectively prevented from filling the groove, and the marked step morphology is ensured to be kept after being subjected to chemical mechanical planarization. According to the method, the problem that in the prior art, the zero-layer alignment mark is rubbed down, so that the alignment signal disappears is solved, and stable and clear alignment signals can be provided for the subsequent photoetching step.

Present invention provides Chemical Mechanical Planarization (CMP) polishing compositions, methods and systems for polishing diffusion barrier materials (such as ruthenium) for metal interconnects (such as copper) in semiconductor manufacture. The CMP polishing compositions use a family of cyclic chelator comprising at least one N-C-C-N group and at least one cyclic ring. The CMP polishing compositions have demonstrated increased removal rate of diffusion barrier layer metals such as ruthenium.

The invention provides a polishing layer, a polishing pad comprising the polishing layer and a manufacturing method of a semiconductor device, and relates to the technical field of polishing of chemical mechanical planarization treatment. The polishing layer is prepared through reaction of raw materials including an isocyanate prepolymer, a curing agent and hollow microspheres, the isocyanate prepolymer is obtained through reaction of raw materials including aromatic isocyanate and polymeric polyol, NCO serves as an end-capping group, the mass percentage of the overall NCO of the isocyanate prepolymer is 6-12%, the mass percentage of the curing agent is 1-3%, and the mass percentage of the hollow microspheres is 1-3%. The content of free aromatic isocyanate is less than or equal to 0.1%. According to the polishing layer, on the basis that the density of the polishing pad is not changed, abrasion in the polishing process can be reduced, the service life of the polishing pad is prolonged, wide-range adjustment of hardness can be achieved through simple and low-cost process adjustment, and therefore the polishing layer can meet the differential requirements of different semiconductor manufacturing processes.

The invention relates to a CMP machine with improved throughput and processing flexibility. An apparatus for performing chemical mechanical planarization is disclosed. The apparatus includes a support, wherein the axis of rotation extends through the support. The apparatus includes at least one elongate member including a first portion and a second portion opposite the first portion. The first portion is configured to be rotatably connected to the support and to pivot the elongate member in a single direction about an axis of rotation by an angle of rotation of at least about 270 degrees relative to the support. The apparatus includes a carrier head configured to be connected to the second portion and to hold and process the substrate.