81 results about "Chemical-mechanical planarization" patented technology

The invention discloses a wafer chemical-mechanical planarization control system, which is characterized by comprising a chemical-mechanical planarization system, a chemical-mechanical planarization control system, a chemical-mechanical planarization control system, a chemical-mechanical planarization control system and a chemical-mechanical planarization control system, the integrated detection system is used for acquiring wafer flatness information; the APC data analysis system is used for acquiring wafer flatness information of the integrated detection system and wafer polishing process parameters of the control system and generating the wafer polishing process parameters; and the control system is used for inputting wafer polishing process parameters and feeding back the wafer polishing process parameters to the chemical mechanical planarization system for polishing the next wafer. The invention also discloses a wafer chemical mechanical planarization control method. The APC data analysis system is introduced into detection of the CMP polishing effect, the measured value can be fed back to the chemical mechanical planarization system in time, the technological parameters of the chemical mechanical planarization system are corrected in time, equivalently, the technological parameters are corrected according to the difference of the real-time state of the chemical mechanical planarization system, and the overall polishing effect is better.

The present invention provides a method for in-situ measurement of film thickness and a chemical mechanical planarization device, the method comprising: on the basis of a reflection spectrum of a wafer film and an equivalent light source spectrum, generating an actually measured spectrum, the equivalent light source spectrum being data of the correspondence relationship between wavelength and light intensity generated by using reflected light passing through a planarization solution and a dielectric layer between the planarization solution and a collimating light source probe; matching the actually measured spectrum with a reference spectrum library; and obtaining a wafer film thickness corresponding to a reference spectrum matching the actually measured spectrum and using said thickness as a measurement result.

The present disclosure relates to a method for manufacturing a pixel that includes depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; performing chemical mechanical planarization up to the insulating layer, a portion of the electrode layer left in place in the opening forming an electrode; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

A chemical mechanical polishing (CMP) slurry can comprise a plurality of particles distributed in a carrier, wherein at least a portion of the particles of the plurality of particles can have a body including a core comprising zirconia and a shell overlying at least a portion of the core, wherein the shell comprises silica; an oxidizing agent; and a carrier. The CMP slurry can comprise at least one of a Hydrogen Peroxide Stability %Reduction of not greater than 50%; and a high copper material removal rate.

A chemical mechanical planarization (CMP) system utilizes a high-pressure rinsing fluid with nanobubbles to assist in conditioning of a CMP pad. The CMP system generates nanobubbles in the rinsing fluid prior to dispensing the rinsing fluid onto the CMP pad or while the rinsing fluid is on the CMP pad. The CMP system includes a pad dresser that dresses or conditions the CMP pad while the rinsing fluid and the nanobubbles are present.

A polishing apparatus, specifically for performing chemical mechanical planarization on an object such as a substrate, which may be a semiconductor wafer. The polishing apparatus may include a rotatable polishing pad having an axial center of rotation and a slurry delivery conduit configured to introduce polishing slurry through said axial center of rotation. The polishing slurry may be configured to be dispensed directly beneath the rotatable polishing pad to enable localized polishing of a surface of a substrate located below or beneath the rotatable polishing pad.

Disclosed in the present invention are a low-dielectric-absorption, low-mismatch, precision, linear MIM capacitor and integration technology. The integration technology comprises the integration steps of: 1) forming an active region and an isolation field oxide region; 2) forming a thick gate oxide layer and a thin gate oxide layer; 3) depositing a polysilicon layer and constructing a polysilicon gate of an MOS transistor; 4) completing photolithography and implantation of a source and a drain for a multi-gate oxide high-low voltage BiCMOS / CMOS; 5) improving the flatness of the lower surface region of a metal thin film resistor by means of chemical mechanical planarization; 6) sputtering a high-resistivity microcrystalline titanium thin film on a lower electrode of a metal MIM capacitor by means of a PVD method; 7) depositing a silicon nitride SixNyHz as a dielectric layer of the metal MIM capacitor by means of PECVD; 8) sputtering the high-resistivity microcrystalline titanium thin film on an upper electrode of the metal MIM capacitor by means of a PVD method; and 9) sputtering an aluminum-copper film layer and completing etching processing of a metal connection line. The present invention optimizes the problem of precision matching of metal MIM capacitors, improves the packaging function density and the device density of integrated circuits, and promotes the miniaturization and reduced form of high-performance integrated circuits.

Carriers for polishing workpieces with flats or voids are provided. In one aspect, a substrate carrier head for a chemical mechanical planarization (CMP) system include a carrier body comprising an aperture configured to receive a wafer and a membrane having a first surface configured to contact a surface of the wafer and a second surface opposing the first surface, the membrane having a primary zone and a secondary zone. The substrate carrier head further includes a membrane cavity formed along the second surface and configured to apply pressure to the membrane within the primary zone, and a membrane support plate configured to support the secondary zone of the membrane.

A chemical mechanical planarization (CMP) composition is provided that provides a tunable high Cu removal rate and a low Cu static etch rate for polishing a wide range of bulk or advanced node copper or silica through vias (TSVs). The CMP composition also provides high selectivity of Cu films over other barrier layers such as Ta, TaN, Ti, TiN, and SiN, and dielectric films such as TEOS, low-k, and ultra low-k films. The CMP composition includes an abrasive, an oxidizer, and at least two chelating agents selected from the group consisting of amino acids, amino acid derivatives, and combinations thereof, and the Cu static etch rate reducer includes, but is not limited to, organic alkyl sulfonic acids with linear or branched alkyl chains, and salts of organic alkyl sulfonic acids.

The invention provides a manufacturing method of a capacitor structure. The method comprises the following steps: sequentially forming a first conductive layer, a capacitor dielectric layer and a second conductive layer on a substrate; a protection mask is formed on the second conductive layer before a subsequent processing process in a flash memory device manufacturing process is executed by adding a special photoetching process once. The protective mask shields and protects the capacitor structure in a subsequent processing process, so that the top surface of the capacitor structure is prevented from being affected, and the flatness of the capacitor structure is maintained. According to the method, only one photoetching mask needs to be added, the damage of chemical mechanical planarization and other processes to the flatness of the capacitor structure can be effectively avoided, and therefore the capacitor structure higher in stability and precision is obtained.

A method includes identifying a substrate thickness map of a substrate thinned via one or more chemical mechanical planarization (CMP) operations. The method further includes causing, based on the substrate thickness map, additional thinning of the substrate via etching of the substrate.

This invention provides a chemical mechanical planarization method and apparatus for semiconductor manufacturing processes to achieve planarization. [Solution] According to one embodiment of the present invention, the technical gist of the present invention is a chemical mechanical planarization method in a semiconductor manufacturing process, which involves applying an electric field to the wafer surface using electrophoretic phenomena during a CMP (Chemical Mechanical Planarization) process to control the distribution of charged particles in a slurry, and a chemical mechanical planarization apparatus for a semiconductor manufacturing process, which includes CMP equipment for performing a CMP process to planarize the wafer surface, and an electric field application control unit for applying an electric field to the wafer surface during the CMP process.

A method of fabricating a semiconductor device includes receiving a device substrate; forming an interconnect structure on a front side of the device substrate; and etching a recess into a backside of the device substrate until a portion of the interconnect structure is exposed. The recess has a recess depth and an edge of the recess is defined by a sidewall of the device substrate. A conductive bond pad is formed in the recess, and a first plurality of layers cover the conductive bond pad, extend along the sidewall of the device substrate, and cover the backside of the device substrate. The first plurality of layers collectively have a first total thickness that is less than the recess depth. A first chemical mechanical planarization is performed to remove portions of the first plurality of layers so remaining portions of the first plurality of layers cover the conductive bond pad.

A Chemical Mechanical Planarization (CMP) system, apparatus, and method comprising providing a source of CMP slurry; modifying the source of CMP slurry to form a modified CMP slurry by directing a source of at least one of mechanical or electromagnetic wave energy at the source of CMP slurry; applying a flow of the modified CMP slurry to a wafer polishing apparatus at which a substrate is positioned; and performing a polishing operation on the substrate.

The invention provides a manufacturing method of a zero-layer alignment mark suitable for a multi-material active region substrate. The method comprises the following steps: forming a first dielectric layer on a substrate with a zero-layer alignment mark region and a channel region; etching the zero layer alignment mark area, and forming a groove in the substrate; forming a second dielectric layer for blocking epitaxial growth on the inner surface of the groove and the channel region; chemical mechanical planarization is carried out on the second dielectric layer, so that the second dielectric layer is reserved in the groove to form a lining; and removing the first dielectric layer. According to the method, the dielectric layer lining is formed in the zero-layer alignment marked groove in advance, so that the epitaxial material in the subsequent multi-material active region process is effectively prevented from filling the groove, and the marked step morphology is ensured to be kept after being subjected to chemical mechanical planarization. According to the method, the problem that in the prior art, the zero-layer alignment mark is rubbed down, so that the alignment signal disappears is solved, and stable and clear alignment signals can be provided for the subsequent photoetching step.

Present invention provides Chemical Mechanical Planarization (CMP) polishing compositions, methods and systems for polishing diffusion barrier materials (such as ruthenium) for metal interconnects (such as copper) in semiconductor manufacture. The CMP polishing compositions use a family of cyclic chelator comprising at least one N-C-C-N group and at least one cyclic ring. The CMP polishing compositions have demonstrated increased removal rate of diffusion barrier layer metals such as ruthenium.

The invention provides a polishing layer, a polishing pad comprising the polishing layer and a manufacturing method of a semiconductor device, and relates to the technical field of polishing of chemical mechanical planarization treatment. The polishing layer is prepared through reaction of raw materials including an isocyanate prepolymer, a curing agent and hollow microspheres, the isocyanate prepolymer is obtained through reaction of raw materials including aromatic isocyanate and polymeric polyol, NCO serves as an end-capping group, the mass percentage of the overall NCO of the isocyanate prepolymer is 6-12%, the mass percentage of the curing agent is 1-3%, and the mass percentage of the hollow microspheres is 1-3%. The content of free aromatic isocyanate is less than or equal to 0.1%. According to the polishing layer, on the basis that the density of the polishing pad is not changed, abrasion in the polishing process can be reduced, the service life of the polishing pad is prolonged, wide-range adjustment of hardness can be achieved through simple and low-cost process adjustment, and therefore the polishing layer can meet the differential requirements of different semiconductor manufacturing processes.

Some implementations described herein relate to dispensing a slurry onto a polishing pad for a chemical-mechanical planarization (CMP) process. These implementations also involve rotating the polishing pad while the slurry is dispensed onto the polishing pad. Rotation of the polishing pad results in a traversal of the slurry radially outward toward a polishing pad outer edge of the polishing pad. The polishing pad includes a plurality of groove segments and a geometric patterns formed by the plurality of the groove segments impede the flow of the slurry to the polishing pad outer edge.

Improved bonding surfaces for microelectronics are provided. An example method of protecting a dielectric surface for direct bonding during a microelectronics fabrication process includes overfilling cavities and trenches in the dielectric surface with a temporary filler that has an approximately equal chemical and mechanical resistance to a chemical-mechanical planarization (CMP) process as the dielectric bonding surface. The CMP process is applied to the temporary filler to flatten the temporary filler down to the dielectric bonding surface. The temporary filler is then removed with an etchant that is selective to the temporary filler, but nonreactive toward the dielectric surface and toward inner surfaces of the cavities and trenches in the dielectric bonding surface. Edges of the cavities remain sharp, which minimizes oxide artifacts, strengthens the direct bond, and reduces the bonding seam.

Barrier or cladding structures that prevent top vias from chemically reacting to tape residue or other impurities address reliability issues in local silicon interposer interconnection in semiconductor packaging by mitigating metal atom migration and wire growth, thereby enhancing long-term reliability. The via cladding structure incorporates a multi-layered barrier comprising, alone or in any combination, SiOCH, SiOx, SiON, SiNx, CuOx, Ta, Ti, TaN, TiN, Mo, MoN, TaC, TiC, TaCN, or TiCN, enhancing electrical performance and long-term reliability. The method of forming the cladding or barrier structure involves a combination of cladding layer deposition, patterning, wet etch, isotropic dry etch or anisotropic dry etch process, flowable dielectric deposition or spin-coat dielectric, and chemical mechanical planarization (CMP) to ensure robust and reliable connections. The integration of these layers mitigates issues related to metal atom migration and wire growth, providing a solution for the growing demand for high-density, high-performance semiconductor packages.

A polishing pad that includes one or more wear indicators, a chemical mechanical planarization (CMP) apparatus that includes the polishing pad, and associated methods. The polishing pad may include a body configured to engage with a platen of the CMP apparatus. The polishing pad may further include a plurality of grooves formed on a top surface of the body. The plurality of grooves are sized and shaped to facilitate uniform distribution of a slurry across the top surface of the polishing pad during operation. The polishing pad further includes a wear indicator positioned within one of the grooves that includes a top surface having a height that is lower than a height of the groove in the body of the polishing pad. The wear indicator may be configured to allow determination of different levels of wear of the polishing pad.

A method for improving warpage of a chip is disclosed. The method includes providing a substrate having a plurality of metal interconnects formed thereon, forming a dielectric layer on the substrate and the plurality of metal interconnects using a high density plasma chemical vapor deposition process, wherein a surface of the dielectric layer is higher than a top surface of the plurality of metal interconnects, planarizing the dielectric layer using a chemical mechanical planarization process, wherein a surface of the planarized dielectric layer is higher than the top surface of the plurality of metal interconnects, and forming a first high stress tetraethoxysilane layer on the dielectric layer.

The application belongs to the technical field of semiconductors, and discloses a back-illuminated image sensor and a preparation method thereof, the method comprising the following steps: providing a wafer bonding structure; the wafer bonding structure comprising a device wafer; performing co-ion implantation on the back surface of the device wafer, then performing chemical mechanical planarization to thin the device wafer to a set thickness, then forming a substrate oxide layer on the back surface of the device wafer; depositing a high dielectric constant layer on the substrate oxide layer; and performing annealing treatment. The application performs co-ion implantation on the back surface of the device wafer before CMP to change the polishing rate of the back surface, so that the chemical grinding can be more planarized; the H2O2 reacts with damaged Si to generate a sacrificial oxide layer, and the sacrificial oxide layer can be removed by adding HF, so that the EPI damage degree after chemical grinding can be reduced, the SI-H bond generated at the interface can make up for defects while eliminating silicon damage; the application solves the problem of bubbles and improves the terminal performance of products under the premise of ensuring the terminal performance of white spots and dark current.

A roller brush for cleaning a substrate following chemical mechanical planarization (CMP) of the substrate includes a generally cylindrical body having an outer surface; and a plurality of spaced-apart bristles projecting outwardly from and circumferentially around the outer surface of the cylindrical body and separated by a plurality of gaps. Each bristle of the plurality of spaced-apart bristles has a diameter, D, and a height, H, such that the ratio D / H is less than or equal to about 0.3.

A chemical mechanical planarization composition for polishing molybdenum, comprising an aqueous liquid carrier, abrasive particles dispersed in the liquid carrier, an amine compound having an acid group selected from the group consisting of carboxylic acid, phosphoric acid, and sulfonic acid, and an oxidizing agent selected from the group consisting of hydrogen peroxide, ferric nitrate, potassium iodate, and mixtures thereof. A method for chemical mechanical polishing a substrate containing a molybdenum layer includes contacting the substrate with the polishing composition, moving the polishing composition relative to the substrate, and polishing the substrate to remove a portion of the molybdenum layer from the substrate.

Shallow Trench Isolation (STI) chemical mechanical planarization (CMP) polishing compositions, methods and systems of use therefore are provided. The CMP polishing composition comprises abrasives of ceria coated inorganic oxide particles, such as ceria-coated silica; and dual chemical additives for providing the tunable oxide film removal rates and tunable SiN film removal rates and low oxide trench dishing and high oxide: SiN selectivity. Dual chemical additives comprise at least one silicone-and-fluorine containing compound; and at least one of non-ionic organic molecule having more than one hydroxyl functional group.

The present disclosure relates to a method for manufacturing a pixel that includes depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; performing chemical mechanical planarization up to the insulating layer, a portion of the electrode layer left in place in the opening forming an electrode; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.

The invention relates to chemical mechanical planarization equipment and a method for replacing polishing pads, the chemical mechanical planarization equipment is used for executing a wafer polishing process, and the method comprises the following steps: removing a first polishing pad on a polishing disc; at least one sensor located on the grinding disc detects removal of the first grinding pad and sends a signal to a host; after receiving the signal, the host activates the alarm to give an alarm; if yes, life parameters in the host are reset, an alarm elimination instruction is sent to the alarm, and the alarm stops giving an alarm; wherein the service life parameter is one of reference parameters of the grinding process controlled by the host, and the alarm stops alarming only after the service life parameter is reset; after the first polishing pad is removed, a second polishing pad is mounted on the polishing disc. The device can give an alarm after detecting that the grinding pad is taken down to remind to reset the service life parameter of the grinding pad.