Method for manufacturing a
semiconductor component, comprising: Forming an insulating layer (24) over a fin structure (26), wherein a first section (28) of the fin structure (26) is exposed by the insulating layer (24) and a second section of the fin structure (26) is embedded in the insulating layer (24); Formation of a
dielectric layer (32) over side walls of the first section (26) of the fin structure (26); Removing the first section (28) of the fin structure (26) and part of the second section of the fin structure (26) in a source / drain area, thereby forming a trench (42), and Forming an epitaxial source / drain structure in the trench (42) using a first process or a second process, wherein the first process comprises an improved epitaxial growth process which has an improved growth rate for a preferred crystallographic
facet, and the second process involves using a modified
etching process to reduce the width of the epitaxial source / drain structure; wherein the
semiconductor component comprises an NMOS and / or a PMOS component; wherein, in the case of an NMOS component, the first process is carried out using a CVD process at a high temperature within a range of about 650 to 700 °C and a pressure within a range of about 27 to 47 kPa and / or the modified
etching process comprises a CVD
etching process carried out using a mixture of GeH4 and HCl with a
mixing ratio of GeH4 to HCl within a range of about 0.5 to 1.2 and at a high temperature within a range of about 650 to 750 °C and a pressure within a range of about 0.7 to 13 kPa or using a mixture of SiH4 and HCl with a
mixing ratio of SiH4 to HCl within a range of about 0.2 to 0.25 and at a high temperature within a range of about 650 to 750 °C and a pressure within a range of about 0.7 to 13 kPa; and / or wherein, in the case of a PMOS component, the first process is carried out using a CVD process at a high temperature within a range of 600 to 650 °C and a pressure within a range of approximately 0.7 to 7 kPa and / or the modified etching process comprises a CVD etching process using HCl with a flow rate within a range of approximately 50 to 120 sccm, a temperature within a range of 600 to 650 °C and a pressure within a range of approximately 0.7 to 7 kPa.