33669 results about "Device material" patented technology

The invention relates to the technical field of intelligent control of test equipment, and discloses a semiconductor device test equipment control system and method based on industrial data processing, and the method comprises the steps: collecting multi-source heterogeneous data of semiconductor device test equipment, and carrying out the preprocessing; constructing a structural causal model, and performing root cause identification through anti-fact reasoning by using the structural causal model; constructing an abnormal test fingerprint and a knowledge base; generating an intervention scheme, evaluating the generated intervention scheme, and selecting an optimal intervention scheme; processing the detected anomaly, and generating and implementing a preventive control strategy based on historical anomaly data and a causal analysis result; according to the invention, by introducing innovative technologies such as causal inference, anti-factual inference, abnormal test fingerprint identification and Monte Carlo tree search, intelligent control of semiconductor test equipment is realized.

The invention relates to the technical field of semiconductor device testing, in particular to a SiC MOSFET power cycle testing method which comprises the following steps: S1, building a composite environment testing platform, configuring dynamic testing parameters, automatically calculating a physical boundary and collecting sensor data in real time; s2, establishing a finite element simulation model based on the physical boundary and sensor data, and outputting optimized dynamic test parameters and a simulated stress distribution diagram; s3, synchronously applying composite stress according to the dynamic test parameters and the stress distribution diagram, and collecting multi-dimensional test data in real time; when the system is used, through dynamic boundary calculation and real-time data acquisition, the intelligent degree and reliability of the test are improved, the test period is shortened, the failure prediction accuracy is improved, the system is suitable for reliability evaluation of SiC MOSFET devices in the fields of new energy, aerospace and the like, a large number of physical tests are avoided through virtual simulation, and the reliability of the SiC MOSFET devices is improved. And reduction of device loss and resource waste is facilitated.

The invention provides a third-generation semiconductor device multi-physical field coupling effect dynamic monitoring method and system, and relates to the technical field of semiconductors, and the method comprises the steps: collecting the data of a temperature field, an electric field, a magnetic field and a stress field through a complementary sensor array, constructing a feature tensor, inputting the feature tensor into a pre-trained graph neural network, and extracting a coupling effect dynamic evolution rule; on-line analysis and prediction are carried out by using an adaptive time window and a recurrent neural network, a multi-field coupling correlation degree evaluation model is established, an early warning level is determined according to the deviation between the coupling correlation degree and an early warning threshold value, and device risk evaluation and maintenance suggestions are generated, so that early warning of the failure risk of the semiconductor device is realized.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

An example embodiment of the present invention provides a semiconductor device including: an encoder configured to receive a plurality of bit data by dividing the plurality of bit data into first group data and second group data, the plurality of bit data being divided into 2-bit units, to delay the second group data for a first period, and to output the first group data and the delayed second group data; and an output driver configured to output the first group data and the delayed second group data together to an external semiconductor device.

The invention discloses a self-adaptive switching system and method for power supply and distribution, and the system comprises a data collection module, an analysis module, a modeling module, a decision module, an execution module and an early warning module, and the data collection module generates a real-time monitoring signal; the analysis module performs dynamic weighted evaluation according to the real-time monitoring signal and generates an evaluation signal; the modeling module constructs a virtual model of the power supply system and generates an analog signal; the decision signal generates a control signal containing a path selection instruction; the execution module controls the semiconductor device to switch the physical connection state of the power supply according to the control signal and generates a switch feedback signal; and the early warning module forms an equipment health assessment result according to the switch feedback signal and an abnormal arc signal when the execution module switches the connection state and transmits the result to the decision module. The self-adaptive switching system for power supply and distribution can solve the problem that a traditional power supply and distribution switching system depends on a single threshold to judge the state of a power supply and cannot comprehensively evaluate the quality of electric energy.

A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source / drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source / drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source / drain feature; and a power rail disposed under and electrically connected to the first via.

A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source / drain (S / D) epitaxy and a bottom FET with bottom S / D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S / D epitaxy and cuts through the bottom S / D epitaxy with isolation between the backside contact and the bottom S / D epitaxy.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

A semiconductor device includes a plurality of gate separated by an interlayer dielectric (ILD), a backside contact. The backside contact is extended below the plurality of gates and a dielectric layer, and from a first gate to a second gate of the plurality of gates, and a placeholder. The placeholder is extended below the plurality of gates and between the second gate and a third gate of the plurality of gates. The backside contact and the placeholder are not directly electrically connected.

The invention relates to the technical field of semiconductor parallel testing, and provides a semiconductor device parallel testing method and system based on a multi-channel IC testing machine. The method comprises the following steps: acquiring a parallel test task set, and extracting key test characteristics of each task; calculating test conflicts among the tasks, and generating a task conflict matrix; outputting a channel distance matrix according to the test machine channel position; defining a conflict scheduling objective function, jointly solving a distance matrix and a conflict matrix, and outputting a task channel mapping relation; and loading the task set according to the mapping relation to execute the test. The technical problems of parallel test conflicts and unreasonable test resource allocation caused by difference of voltage, current, frequency or drive circuit characteristics of different test tasks are solved, and under the premise of guaranteeing the test accuracy and the system stability, through collaborative optimization mapping of the conflict matrix and the distance matrix, the test efficiency is improved. And the resource allocation of the multi-channel IC test machine is optimized, the interference conflict between tasks is reduced, and the parallel test efficiency is improved.

The invention provides a training method and device for a semiconductor device performance prediction model and related equipment, and the method comprises the steps: determining key parameters and performance parameters of a semiconductor device, the key parameters comprise key size parameters and / or process parameters, and the performance parameters comprise electrical characteristic parameters of the semiconductor device; based on the multiple groups of key parameter values and the corresponding performance parameter values, establishing a sample set; the key parameter values are disturbed, and the correlation degree of the key parameters and the performance parameters is determined; wherein after the key parameter value is disturbed, the change condition of the corresponding performance parameter value is used for representing the correlation degree of the key parameter and the performance parameter; initializing the weight of a preset neural network model based on the performance prediction target and the correlation degree of the key parameter and the performance parameter; and inputting at least part of samples in the sample set into a weight-initialized preset neural network model for training to obtain a semiconductor device performance prediction model.

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

The invention relates to the technical field of semiconductors, in particular to a device integrated with a deep trench isolation structure and a preparation method of the device. The preparation method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a gate material layer stacked on the surface of the substrate and a mask layer stacked on the gate material layer, and a functional element of the semiconductor device is formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates through the mask layer and the gate material layer and goes deep into the substrate; the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure comprises a filling structure, the filling structure is not higher than the surface of the substrate, and the material of the filling structure is a conductive non-metal material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. According to the invention, the preparation process of the deep trench isolation structure can be integrated into the standard process for preparing the gate structure of devices such as a BCD, the integration process of deep trench isolation is simplified, and the preparation cost is reduced.

The invention discloses a semiconductor device based on two-dimensional semi-metal interface optimized contact and a preparation method thereof, which are applied to devices including a two-dimensional semiconductor-based metal-semi contact structure, such as thin film transistors, Schottky junction diodes / transistors and the like. According to the invention, the two-dimensional semi-metal interface layer is introduced between the metal electrode (source and drain electrodes) and the two-dimensional material (conductive channel) through PVD and CVD processes, so that pollution and defects caused by additional transfer steps are avoided, preparation of the interface layer with large area, high uniformity and controllable thickness can be realized, and industrial requirements are met. According to the semiconductor device provided by the invention, the two-dimensional semimetal is introduced as the interface layer, so that the contact resistance between the source and drain electrodes and the conductive channel is obviously optimized, Fermi level pinning is eliminated, and the adjustable Schottky barrier height is realized; and a brand new solution is provided for development and industrial application of a metal-semiconductor contact structure device of a high-performance two-dimensional semiconductor.

The invention belongs to the technical field of semiconductor device packaging, and discloses a power semiconductor module three-dimensional stacking vertical commutation low-inductance packaging structure. The two vertical commutation structures are stacked and integrated on the same substrate; different from traditional two-dimensional packaging in which all elements are laid on a two-dimensional plane, three-dimensional stacked packaging suitable for power devices is proposed for the first time, and power loops are stacked and integrated; the magnetic fluxes of the stacked power loops are cancelled, so that ultra-low inductance (pH level) integration is realized; under the condition that the areas of the substrates are the same, the capacity of the module is doubled; meanwhile, dynamic current sharing design is considered, and one driving chip simultaneously drives eight GaN chips to realize parallel dynamic current sharing for the first time; the method is suitable for various topological structures including half-bridge structures, full-bridge structures, three-level ANPC structures and the like; the method is suitable for various packaging schemes, including PCB on DBC packaging, DBC substrate welding / sintering packaging and embedded packaging. Taking the packaging of the half-bridge module double-sided parallel PCB on DBC as an example, low-inductance, low-thermal-resistance and high-power-density integration is realized.

A method includes forming a dielectric layer over a source / drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source / drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.

The invention discloses an electromagnetic field simulation grid adaptive generation method based on a neural network. The method comprises the following steps: performing mesh generation on a semiconductor device simulation model to obtain original generation data, and constructing node features; an undirected graph is constructed, graph nodes of the undirected graph adopt node features of grid points, and connecting edges adopt Euclidean distances between the grid points and adjacent grid points; inputting the undirected graph into a double-branch neural network, and outputting a predicted node position; and correcting each node of the original subdivision data by using the predicted node position obtained by the double-branch neural network to form new subdivision data for electromagnetic field simulation. According to the method, physical field information can be fused to efficiently adjust the node density, and the geometric boundary and topological structure characteristics of the device can be strictly kept.

The invention discloses a solar cell performance prediction method and device based on a physical information fusion model, and relates to the technical field of computer data processing and semiconductor characterization. According to the technical scheme provided by the invention, the deep neural network architecture is adopted to perform feature extraction and fusion on the multi-dimensional spectral information, the prediction precision is improved by more than 35%, and the reliability is improved by more than 40%, so that the prediction performance is remarkably improved; an innovative physical information fusion loss function is adopted for training the model and comprises a data-driven prediction loss item and a constraint loss item based on a semiconductor device physical rule, and a prediction task and a physical principle are deeply fused, so that the prediction model can understand a physical causal relationship between spectral characteristics and device performance, and the prediction efficiency is improved. According to the method, more accurate performance prediction and better physical interpretability are realized, multiple physical constraints are adopted to standardize the prediction result, so that the model prediction result conforms to the physical principle of the semiconductor device, and the physical rationality and engineering application value of the prediction result are improved.

The invention provides an LED packaging device and a preparation method and application thereof, and relates to the technical field of semiconductor devices.The preparation method comprises the steps that packaging silica gel and fluorescent powder are mixed according to a preset proportion, and then a film with the preset thickness is prepared through a film scraping machine; curing the membrane at a first preset temperature for a first preset time, and completing primary curing to obtain a semi-cured fluorescent sheet; transferring the semi-cured fluorescent sheet to the flip LED chip which is subjected to die bonding in the bracket, and carrying out vacuum pressure sinking, so that the semi-cured fluorescent sheet is completely attached to the surface and the side surface of the flip LED chip; curing the semi-cured fluorescent sheet subjected to vacuum pressure sinking at a second preset temperature for a second preset time, and completing secondary curing to obtain a cured finished product; according to the LED packaging device and the manufacturing method thereof, the technical problems that in the prior art, the stability of the dispensing glue amount of the LED packaging device is poor, fluorescent powder is not evenly distributed, and consequently the brightness and the concentration degree are reduced can be solved.

A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface therebetween. A bottom shielding structure of a second conductivity type is provided under the bottom surface of the gate trench. First and second support shielding structures of the second conductivity type extend into the drift region on opposing sides of the gate trench and are spaced apart from the sidewalls thereof. A material composition, distance of extension into the drift region relative to a surface of the semiconductor layer structure, and / or dopant concentration of the bottom shielding structure may be different from that of the first and second support shielding structures. Related devices and fabrication methods are also discussed.

A substrate 10 has an integrated circuit formed therein and has a pad electrode PD formed on an upper surface thereof and electrically connected to the integrated circuit. An insulating film IF2 is formed on the upper surface of the substrate 10, and an opening OP is formed in the insulating film IF2. A redistribution wiring PW1 is formed in the opening OP and on the insulating film IF2 and is electrically connected to the pad electrode PD. An external connection terminal ET1 electrically connected to the redistribution wiring RW1 is formed on the redistribution wiring RW1. Also, a redistribution wiring RW2 is formed on the insulating film IF2 and is electrically isolated from the redistribution wiring RW1, the pad electrode PD, and the integrated circuit. A plurality of external connection terminals ET2 electrically connected to the redistribution wiring RW2 are formed on the redistribution wiring RW2. The redistribution wiring RW2 and the external connection terminal ET2 constitute a measuring circuit (20) for measuring a resistance value.

A described example includes: a leadframe having a high voltage section and a low voltage section spaced from and electrically isolated from the high voltage section, and a heat slug mounted to the high voltage section. The high voltage section includes an input portion connected to the heat slug at an interior end by a mount portion, and further includes an interior lead portion that is connected to the mount portion by a flexible connect portion. An insulating material mounted to the heat slug provides a die mount area for a semiconductor die having a Hall element that is positioned so that the Hall element is proximate to the heat slug. Mold compound covers the semiconductor die, portions of the leadframe, and portions of the heat slug while a board side surface of the heat slug is exposed forming a thermal pad for a semiconductor device package.

The invention provides a TEM sample and a preparation method and application thereof.According to the preparation method of the TEM sample, on the premise that the hole structure of a semiconductor device is not affected, part of residual polymer accumulated and blocked in a hole opening in the semiconductor device is removed through reactive ion etching, so that the hole opening is expanded and not blocked any more; a protective colloid can enter a pore structure for filling and precursor material plating of atomic layer deposition is facilitated, the definition of the side wall of the pore is enhanced, and the quality and the final observation effect of the TEM sample are effectively improved; the equipment and technology adopted by the preparation method of the TEM sample provided by the invention are low in investment, and the operation process is simpler and faster than that of a Fab etching process; meanwhile, batch laboratory-scale sample treatment can also be realized; in addition, compared with a wet chemical corrosion cleaning technology for removing residual polymers, the problems of chemical reagent residues, chemical reactant pollution and the like at the bottom of the deep hole structure are avoided.

The invention provides a semiconductor equipment task scheduling control method and system, equipment and a medium, and the method comprises the steps: collecting multi-factor operation data and operation task data of an operation arm, splitting a task into a plurality of sub-tasks based on the motion type of the operation arm, and carrying out the task scheduling of the operation arm based on a task unique identifier, a sub-task identifier and an operation arm identifier; associating the multi-factor operation data with the operation task data, and constructing a mapping structure; constructing a node set based on the mapping structure, screening the node set to form a candidate node pair set, executing conflict detection according to a conflict detection strategy for each node pair in the candidate node pair set, generating a conflict edge set, and generating a path conflict graph based on the node set and the conflict edge set, the conflict detection strategy comprises station conflict detection, time conflict detection and space conflict detection; and dynamically adjusting the tasks in the candidate sub-task set in real time based on the path conflict graph and the conflict resolution strategy.

A semiconductor device has a first interconnect structure, second interconnect structure, and a semiconductor die disposed between the first interconnect structure and second interconnect structure. The semiconductor die can have a photonic area. An embedded interconnect structure is disposed between the first interconnect structure and second interconnect structure. The embedded interconnect structure has a height sufficient to span a gap between the first interconnect structure and second interconnect structure. The embedded interconnect structure can be a plurality of conductive posts, and a second encapsulant deposited around the conductive posts. The embedded interconnect structure can be a plurality of e-bar structures, and a second encapsulant deposited around the e-bar structures. The embedded interconnect structure can also be a plurality of vertical loop wires, and a second encapsulant deposited around the vertical loop wires. A first encapsulant is deposited around the semiconductor die and embedded interconnect structure.

Provided are a semiconductor device for changing a link speed and a link width of a peripheral component interconnect express (PCIe) link and an operating method thereof. The semiconductor device includes the PCIe link including a plurality of lanes, and a controller configured to transceive a data link layer packet (DLLP) including a number of times of transition and a maximum number of times of transition from an L0 state to an L0p state through the PCIe link, based on a first bit error rate (BER) of a data packet received through the PCIe link and a first criterion value in the L0 state, and determine whether to perform at least one of a link speed changing operation performed in a recovery state, or a link width changing operation performed in the L0p state, based on the number of times of transition and the maximum number of times of transition.

A semiconductor device may include: a first conductive line including an opening passing through the first conductive line; a second conductive line disposed over the first conductive line and spaced apart from the first conductive line; a first electrode layer buried in the opening; a selector layer disposed in the opening and surrounding side surfaces of the first electrode layer; and a variable resistance layer disposed over the selector layer and the first electrode layer.