37577 results about "Device material" patented technology

The invention relates to the technical field of intelligent control of test equipment, and discloses a semiconductor device test equipment control system and method based on industrial data processing, and the method comprises the steps: collecting multi-source heterogeneous data of semiconductor device test equipment, and carrying out the preprocessing; constructing a structural causal model, and performing root cause identification through anti-fact reasoning by using the structural causal model; constructing an abnormal test fingerprint and a knowledge base; generating an intervention scheme, evaluating the generated intervention scheme, and selecting an optimal intervention scheme; processing the detected anomaly, and generating and implementing a preventive control strategy based on historical anomaly data and a causal analysis result; according to the invention, by introducing innovative technologies such as causal inference, anti-factual inference, abnormal test fingerprint identification and Monte Carlo tree search, intelligent control of semiconductor test equipment is realized.

The present application provides a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a first die; a first redistribution structure positioned on the first die; a second die positioned on the first redistribution structure and comprising a first cache unit; and a third die positioned on the first redistribution structure, separated from the second die, and comprising a second cache unit. The first redistribution structure comprises: a plurality of conductive layers electrically coupled the first die and the first cache unit of the second die and electrically coupled the first die and the second cache unit of the third die, respectively and correspondingly; and a bridge layer electrically isolated from the plurality of conductive layers, electrically connected the second die and the third die. The first cache unit of the second die and the second cache unit of the third die are topographically aligned with the first die. The first die is configured as a cache memory, and the second die and the third die are configured as logic dies.

The invention relates to the technical field of semiconductor device testing, in particular to a SiC MOSFET power cycle testing method which comprises the following steps: S1, building a composite environment testing platform, configuring dynamic testing parameters, automatically calculating a physical boundary and collecting sensor data in real time; s2, establishing a finite element simulation model based on the physical boundary and sensor data, and outputting optimized dynamic test parameters and a simulated stress distribution diagram; s3, synchronously applying composite stress according to the dynamic test parameters and the stress distribution diagram, and collecting multi-dimensional test data in real time; when the system is used, through dynamic boundary calculation and real-time data acquisition, the intelligent degree and reliability of the test are improved, the test period is shortened, the failure prediction accuracy is improved, the system is suitable for reliability evaluation of SiC MOSFET devices in the fields of new energy, aerospace and the like, a large number of physical tests are avoided through virtual simulation, and the reliability of the SiC MOSFET devices is improved. And reduction of device loss and resource waste is facilitated.

The invention provides a third-generation semiconductor device multi-physical field coupling effect dynamic monitoring method and system, and relates to the technical field of semiconductors, and the method comprises the steps: collecting the data of a temperature field, an electric field, a magnetic field and a stress field through a complementary sensor array, constructing a feature tensor, inputting the feature tensor into a pre-trained graph neural network, and extracting a coupling effect dynamic evolution rule; on-line analysis and prediction are carried out by using an adaptive time window and a recurrent neural network, a multi-field coupling correlation degree evaluation model is established, an early warning level is determined according to the deviation between the coupling correlation degree and an early warning threshold value, and device risk evaluation and maintenance suggestions are generated, so that early warning of the failure risk of the semiconductor device is realized.

Semiconductor devices and systems with optical and electrical interposers, and methods of forming the same, are disclosed herein. In one example, a semiconductor device includes a glass substrate and a bridge die embedded in the glass substrate, where the glass substrate includes one or more optical waveguides and the bridge die includes an interconnect to electrically couple multiple integrated circuit dies.

An electronic hardware wallet for conducting cryptocurrency transactions, blockchain transactions, or other secure communications is embodied on a monolithic integrated circuit (IC) die supported on a single substrate. The monolithic semiconductor device can include a non-volatile data store for storing application software executable by the multi-core processor, and the secure element can include a secure data store for storing secret data (e.g., a private key) for use in a secure electronic transaction. In some embodiments, the secure element can include hardware logic embodying a cryptocurrency algorithm associated with executing the secure electronic transaction and can have a limited and selective communication bus between the secure element and the multi-core processor. The electronic hardware wallet can communicatively couple with one or more other devices to facilitate a multi-party computation (MPC) algorithm for authenticating the cryptocurrency algorithm and validating the secure electronic transaction.

An example embodiment of the present invention provides a semiconductor device including: an encoder configured to receive a plurality of bit data by dividing the plurality of bit data into first group data and second group data, the plurality of bit data being divided into 2-bit units, to delay the second group data for a first period, and to output the first group data and the delayed second group data; and an output driver configured to output the first group data and the delayed second group data together to an external semiconductor device.

The invention discloses a self-adaptive switching system and method for power supply and distribution, and the system comprises a data collection module, an analysis module, a modeling module, a decision module, an execution module and an early warning module, and the data collection module generates a real-time monitoring signal; the analysis module performs dynamic weighted evaluation according to the real-time monitoring signal and generates an evaluation signal; the modeling module constructs a virtual model of the power supply system and generates an analog signal; the decision signal generates a control signal containing a path selection instruction; the execution module controls the semiconductor device to switch the physical connection state of the power supply according to the control signal and generates a switch feedback signal; and the early warning module forms an equipment health assessment result according to the switch feedback signal and an abnormal arc signal when the execution module switches the connection state and transmits the result to the decision module. The self-adaptive switching system for power supply and distribution can solve the problem that a traditional power supply and distribution switching system depends on a single threshold to judge the state of a power supply and cannot comprehensively evaluate the quality of electric energy.

A semiconductor device includes semiconductor elements and conductors. The conductors include a first upper conductor connected to an upper electrode of the first semiconductor element through a first upper solder, a first lower conductor connected to a lower electrode of the first semiconductor element through a first lower solder, a second upper conductor connected to an upper electrode of the second semiconductor element through a second upper solder, a second lower conductor connected to a lower electrode of the second semiconductor element through a second lower solder, and a joint conductor connecting the first upper conductor and the second lower conductor through a relay solder. Each solder contains Cu and Sn. Each solder connection target has an Ni layer. A grain size of at least one of the first upper solder, second upper solder, or relay solder is smaller than a grain size of the first and second lower solders.

A semiconductor structure includes one or more channel layers; a gate structure engaging the one or more channel layers; a first source / drain feature connected to a first side of the one or more channel layers and adjacent to the gate structure; a first dielectric cap disposed over the first source / drain feature, wherein a bottom surface of the first dielectric cap is below a top surface of the gate structure; a first via disposed under and electrically connected to the first source / drain feature; and a power rail disposed under and electrically connected to the first via.

The invention discloses a manufacturing method of a groove, a semiconductor device and a manufacturing method of the semiconductor device, and relates to the technical field of semiconductors, and the manufacturing method comprises the steps: providing a substrate, forming a first mask layer on the substrate, and etching the first mask layer by taking a photomask as a mask, so that the first mask layer covers the substrate of a first groove region, forming a second mask layer on the substrate, etching the second mask layer to enable the second mask layer to expose the first mask layer and the substrate in the second groove region, etching the substrate in the second groove region by taking the first mask layer and the second mask layer as masks to form a relatively shallow second groove, and etching the first mask layer to form a relatively shallow second groove; according to the method, the substrate of the first trench region and the substrate of the second trench region are exposed by the second mask layer, and the substrate of the first trench region and the substrate of the second trench region are etched by taking the second mask layer as a mask to form a deeper second trench and a shallower first trench, so that a shallow trench and a deep trench can be manufactured by adopting one photomask, and the manufacturing cost can be further reduced.

A semiconductor device is provided. The semiconductor device includes a back-end-of-line (BEOL) layer, a backside power distribution network (BSPDN), a stacked field effect transistor (stacked FET) and a backside contact. The stacked FET is vertically interposed between the BEOL layer and the BSPDN and includes a top FET with top source / drain (S / D) epitaxy and a bottom FET with bottom S / D epitaxy. The stacked FET is characterized as having at least partial vertical alignment of the top FET and the bottom FET. A backside contact electrically connects the BSPDN and the top S / D epitaxy and cuts through the bottom S / D epitaxy with isolation between the backside contact and the bottom S / D epitaxy.

The invention discloses a gas distribution device and semiconductor equipment, and the gas distribution device comprises a cover body which is provided with a gas inlet part; the spraying piece is movably arranged on the cover body, and a diffusion cavity communicated with the air inlet part is formed between the spraying piece and the cover body; the lifting isolation device comprises a partition plate part and a lifting part, the lifting part is movably arranged on the partition plate part in a sleeving mode, the top of the lifting part is attached to the cover body so that interaction force can be generated between the lifting part and the partition plate part as well as between the lifting part and the cover body, and the partition plate part is arranged on the spraying part so that the diffusion cavity can be defined into different air chambers through the partition plate part and the lifting part; the driving device is arranged at the bottom of the spraying part and extends out of the cover body, and the driving device is controlled to drive the spraying part and the partition plate part to move away from or towards the cover body, so that the top of the lifting part moves towards or away from the cover body, and the volume of the area defined by the lifting isolation device is adjusted. The semiconductor equipment comprises a gas distribution device and a base which is arranged opposite to the gas distribution device and is used for bearing a substrate. According to the invention, the airflow adjustment flexibility can be improved, and the equipment compatibility is improved.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a semiconductor device with an integrated heat dissipation function for a power MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The single MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer, the profile of the cross section of the grid electrode is in an H shape, and the grid electrode comprises two longitudinal parts and a transverse part used for bridging the two longitudinal parts. According to the invention, the H-shaped gate structure is in bridge connection with the double longitudinal grooves through the transverse part, so that the channel width is increased, and the on-resistance is reduced; a current path is further optimized by combining a metal deposition layer and a heavily doped N + layer in the bottom doping layer; and the metal layer is connected in parallel to conduct electricity, so that the resistance is reduced, and the heavily doped N + layer inhibits the JFET effect, so that the resistance is reduced by more than 10%.

The invention discloses a self-adaptive digital twin simulation device and method for semiconductor equipment. The device comprises a data acquisition module, a simulation model construction and operation module and a parameter updating module which are connected through signals. The data acquisition module is used for acquiring production information and process parameter information of a semiconductor product and acquiring actual processing data in real time; the simulation model construction and operation module constructs a process equipment energy consumption simulation model according to a preset process equipment configuration unit, fuses production information and process parameter information of a semiconductor product, operates the process equipment energy consumption simulation model, and gives energy consumption simulation data in real time; and the parameter updating module is used for updating the process parameter information in the process equipment energy consumption simulation model. A real-time data feedback mechanism is introduced by setting a parameter updating module, process parameter information is dynamically updated, and the accuracy and the real-time performance of the process equipment energy consumption simulation model are improved.

The invention relates to the technical field of semiconductor devices, in particular to an infrared photoelectric detector based on a super lens and a manufacturing method of the infrared photoelectric detector. The infrared photoelectric detector based on the super lens comprises a tube socket, a metal tube cap and a detector chip, the metal tube cap and the tube socket are fixedly connected and form a totally-enclosed packaging structure, the detector chip is packaged between the tube socket and the metal tube cap, a chip electrode of the detector chip is welded with a pin of the tube socket, the super lens is arranged at the top of the metal tube cap, and the super lens is arranged on the top of the metal tube cap. The side wall is a metal tube shell, and the super lens comprises a super lens substrate and super lens units periodically arranged above the super lens substrate. According to the infrared photoelectric detector based on the super lens, the super lens units periodically arranged on the super lens can be utilized, the transmittance of incident light can be improved, the interference effect of reflected light can be restrained, and then the detection rate of the infrared photoelectric detector is improved.

A semiconductor device includes a plurality of gate separated by an interlayer dielectric (ILD), a backside contact. The backside contact is extended below the plurality of gates and a dielectric layer, and from a first gate to a second gate of the plurality of gates, and a placeholder. The placeholder is extended below the plurality of gates and between the second gate and a third gate of the plurality of gates. The backside contact and the placeholder are not directly electrically connected.

The invention relates to the technical field of semiconductor parallel testing, and provides a semiconductor device parallel testing method and system based on a multi-channel IC testing machine. The method comprises the following steps: acquiring a parallel test task set, and extracting key test characteristics of each task; calculating test conflicts among the tasks, and generating a task conflict matrix; outputting a channel distance matrix according to the test machine channel position; defining a conflict scheduling objective function, jointly solving a distance matrix and a conflict matrix, and outputting a task channel mapping relation; and loading the task set according to the mapping relation to execute the test. The technical problems of parallel test conflicts and unreasonable test resource allocation caused by difference of voltage, current, frequency or drive circuit characteristics of different test tasks are solved, and under the premise of guaranteeing the test accuracy and the system stability, through collaborative optimization mapping of the conflict matrix and the distance matrix, the test efficiency is improved. And the resource allocation of the multi-channel IC test machine is optimized, the interference conflict between tasks is reduced, and the parallel test efficiency is improved.

The invention provides a training method and device for a semiconductor device performance prediction model and related equipment, and the method comprises the steps: determining key parameters and performance parameters of a semiconductor device, the key parameters comprise key size parameters and / or process parameters, and the performance parameters comprise electrical characteristic parameters of the semiconductor device; based on the multiple groups of key parameter values and the corresponding performance parameter values, establishing a sample set; the key parameter values are disturbed, and the correlation degree of the key parameters and the performance parameters is determined; wherein after the key parameter value is disturbed, the change condition of the corresponding performance parameter value is used for representing the correlation degree of the key parameter and the performance parameter; initializing the weight of a preset neural network model based on the performance prediction target and the correlation degree of the key parameter and the performance parameter; and inputting at least part of samples in the sample set into a weight-initialized preset neural network model for training to obtain a semiconductor device performance prediction model.

Some implementations described herein provide techniques and apparatuses provide a semiconductor device including a photonics device having a backside transmissive region and methods of manufacturing. The semiconductor device includes a first semiconductor device stacked over a second semiconductor device, where the first semiconductor device includes a photodiode structure and the second semiconductor device includes the backside transmissive region. The backside transmissive region, which is below the photodiode structure of the first semiconductor device, includes a trench structure having highly reflective structures and / or properties to maintain an optical power of light waves propagating through the backside transmissive region. An absence of structures within the trench structure lessens a likelihood of interferences which may cause a transmission loss (e.g., a reflection loss, an absorption loss, a scattering loss, and / or a mode mismatch loss) relative to another transmissive region that is adjacent to the photodiode structure.

A manufacturing method of a semiconductor structure and the semiconductor structure, the manufacturing method of the semiconductor structure comprising: providing a substrate comprising a first region and a second region; forming a laminated structure formed by alternately stacking a plurality of first material layers and a plurality of second material layers on the first region; first etching is executed, a groove is formed in one end of the laminated structure, and the second area is exposed out of the bottom of the groove; executing second etching, removing part of the plurality of second material layers through the grooves and keeping the plurality of first material layers arranged at intervals; wherein before the second etching is executed, a protection layer is formed on the surface of the second area, and the protection layer at least extends towards the surface of the first area. According to the method, the semiconductor device with relatively high reliability can be obtained.

A semiconductor device includes a top transistor, a bottom transistor, an isolation box between the top transistor and the bottom transistor, a first gate dielectric, and a second gate dielectric. First portions of the first gate dielectric cover a top surface and top-half of sidewalls of the isolation box, and first portions of the second gate dielectric cover a bottom surface and bottom-half of the sidewalls of the isolation box.

The invention relates to the technical field of semiconductors, in particular to a device integrated with a deep trench isolation structure and a preparation method of the device. The preparation method comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a gate material layer stacked on the surface of the substrate and a mask layer stacked on the gate material layer, and a functional element of the semiconductor device is formed in the substrate; forming a deep trench in the semiconductor structure, wherein the deep trench penetrates through the mask layer and the gate material layer and goes deep into the substrate; the deep trench is filled to form a deep trench isolation structure, the deep trench isolation structure comprises a filling structure, the filling structure is not higher than the surface of the substrate, and the material of the filling structure is a conductive non-metal material; patterning and etching the gate material layer to form a gate structure; and removing the mask layer. According to the invention, the preparation process of the deep trench isolation structure can be integrated into the standard process for preparing the gate structure of devices such as a BCD, the integration process of deep trench isolation is simplified, and the preparation cost is reduced.

The invention discloses a semiconductor device based on two-dimensional semi-metal interface optimized contact and a preparation method thereof, which are applied to devices including a two-dimensional semiconductor-based metal-semi contact structure, such as thin film transistors, Schottky junction diodes / transistors and the like. According to the invention, the two-dimensional semi-metal interface layer is introduced between the metal electrode (source and drain electrodes) and the two-dimensional material (conductive channel) through PVD and CVD processes, so that pollution and defects caused by additional transfer steps are avoided, preparation of the interface layer with large area, high uniformity and controllable thickness can be realized, and industrial requirements are met. According to the semiconductor device provided by the invention, the two-dimensional semimetal is introduced as the interface layer, so that the contact resistance between the source and drain electrodes and the conductive channel is obviously optimized, Fermi level pinning is eliminated, and the adjustable Schottky barrier height is realized; and a brand new solution is provided for development and industrial application of a metal-semiconductor contact structure device of a high-performance two-dimensional semiconductor.

The invention provides a solar cell and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The solar cell comprises a silicon substrate, a semiconductor layer and a transparent conductive layer, the semiconductor layer is formed on the silicon substrate, and the semiconductor layer is of a porous structure; and the transparent conductive layer is positioned on the surface, far away from the silicon substrate, of the semiconductor layer and is in contact with the porous structure. The semiconductor layer has the porous structure, so that the contact area between the semiconductor layer and the transparent conductive layer can be increased, the current transmission characteristic is improved, the energy consumption in the current collection process is reduced, and the cell efficiency is improved.

The invention belongs to the technical field of semiconductor device packaging, and discloses a power semiconductor module three-dimensional stacking vertical commutation low-inductance packaging structure. The two vertical commutation structures are stacked and integrated on the same substrate; different from traditional two-dimensional packaging in which all elements are laid on a two-dimensional plane, three-dimensional stacked packaging suitable for power devices is proposed for the first time, and power loops are stacked and integrated; the magnetic fluxes of the stacked power loops are cancelled, so that ultra-low inductance (pH level) integration is realized; under the condition that the areas of the substrates are the same, the capacity of the module is doubled; meanwhile, dynamic current sharing design is considered, and one driving chip simultaneously drives eight GaN chips to realize parallel dynamic current sharing for the first time; the method is suitable for various topological structures including half-bridge structures, full-bridge structures, three-level ANPC structures and the like; the method is suitable for various packaging schemes, including PCB on DBC packaging, DBC substrate welding / sintering packaging and embedded packaging. Taking the packaging of the half-bridge module double-sided parallel PCB on DBC as an example, low-inductance, low-thermal-resistance and high-power-density integration is realized.

The invention provides a semiconductor device with a PN junction and a preparation method thereof, and belongs to the technical field of semiconductor devices. The semiconductor device comprises a silicon substrate, the surface of one side of the silicon substrate in the thickness direction is provided with an emitter region covering an emitter and an isolation region formed by removing the emitter, a PN junction is formed between the emitter and the silicon substrate, the isolation region is arranged at the edge of the silicon substrate, and at least one side wall of the silicon substrate in the length direction is provided with a cutting surface. An isolation region is arranged at least close to the edge of the cutting surface in the silicon substrate, the surface height of the isolation region is lower than that of the emitter region, the isolation region and the emitter region are connected through a buffer region of a slope structure, and passivation layers cover the surfaces of the emitter, the isolation region and the buffer region. According to the invention, the structure of the isolation region is optimized, a transmission channel of carriers from the emitter region to the cutting surface is effectively cut off, and uniform coverage of the passivation layer is ensured, so that the performance of the device is optimized.

The invention provides a solar cell and a manufacturing method thereof, and belongs to the technical field of semiconductor devices. The solar cell comprises a silicon substrate and a semiconductor layer, the silicon substrate comprises a first surface and a second surface which are opposite, the semiconductor layer is located on the first surface, the first semiconductor layer comprises a second structural region and a first structural region, and the crystallization degree of the first structural region is larger than that of the second structural region; wherein the second structural region is closer to the first surface than the first structural region, and the first semiconductor layer comprises at least one of amorphous silicon, nanocrystalline silicon or microcrystalline silicon. The semiconductor layer has a crystallization structure, and the contact resistance between the semiconductor layer and the conductive material layer can be reduced, so that the current transmission characteristic is improved, the energy consumption in the current collection process is reduced, and the cell efficiency is improved.

A method includes forming a dielectric layer over a source / drain region. An opening is formed in the dielectric layer. The opening exposes a portion of the source / drain region. A conductive liner is formed on sidewalls and a bottom of the opening. A surface modification process is performed on an exposed surface of the conductive liner. The surface modification process forms a surface coating layer over the conductive liner. The surface coating layer is removed to expose the conductive liner. The conductive liner is removed from the sidewalls of the opening. The opening is filled with a conductive material in a bottom-up manner. The conductive material is in physical contact with a remaining portion of the conductive liner and the dielectric layer.

The present application discloses a semiconductor device and a method for fabricating the semiconductor device. The semiconductor device includes a substrate; a capping mask layer positioned on the substrate; a first gate insulating layer positioned along the capping mask layer, inwardly positioned in the substrate, and including a U-shaped cross-sectional profile; a first work function layer positioned on the first gate insulating layer; a first conductive layer positioned on the first work function layer; and a first capping layer positioned on the first conductive layer. The first capping layer includes germanium oxide. A top surface of the first capping layer and a top surface of the capping mask layer are substantially coplanar.