731 results about "Gate voltage" patented technology

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

A high-linearity grid voltage bootstrap circuit relates to the technical field of analog-to-digital conversion and comprises a first charge pump boosting unit, a second charge pump boosting unit and a grid voltage bootstrap unit, working states of a sampling switch are divided into a sampling state and a holding state, an input voltage VIN is boosted to a VG through the grid voltage bootstrap unit in a sampling stage, and the sampling switch is switched on; and the holding stage sampling switch is cut off, and charges are injected to the upper polar plates of the capacitors C3 and C4 of the gate voltage bootstrap unit through the first charge pump boosting unit and the second charge pump boosting unit respectively. According to the invention, the problem that the actual gate-source voltage is reduced due to the grid parasitic capacitance of the sampling switch is solved, and the layout area occupation is greatly reduced while the bootstrap voltage is improved; the proportion of the capacitor C3 and the capacitor C4 can be flexibly set to obtain the required bootstrap voltage; and the problem that the on-resistance of the sampling switch is increased due to the reduction of the gate-source voltage can be solved, and the linearity of the sampling switch is improved.

A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

This disclosure provides a charge pump circuit. The charge pump circuit according to this disclosure includes one or more cascaded boost units and output units having the same structure. Each boost unit has a dual-branch structure with top and bottom symmetry and connected to two sets of four-phase clock signals with opposite clock phases. By adjusting the phase relationship of the four-phase clocks, the rise time of the gate voltage of the transfer transistor can be delayed by advancing the falling edge of the driving clock of the secondary capacitor and delaying its rising edge. This ensures that the transfer transistor is in the off state at the moment of high-low phase switching, thereby avoiding the problem of reduced charge transfer efficiency caused by reverse charge flow between the input and output nodes of the boost unit.

The invention discloses an LDO (Low Dropout Regulator) circuit based on a level conversion and pre-adjustment module. The LDO circuit comprises a reference source, an error amplifier, a pre-adjustment module, a level conversion module, a power switch tube P1, a power circuit tube N1 and resistance feedback networks R1 and R2. The pre-adjustment module carries out voltage reduction processing on an input high-voltage power supply, and the level conversion module generates bias voltage according to an enable signal and the high-voltage power supply, controls a power switch and a switch in the operational amplifier, and ensures that the circuit is resistant to high voltage and extremely low in drain. The error amplifier adjusts the grid voltage of the power circuit according to the feedback and reference voltage difference value, and controls the current to stably output the voltage. And the resistance feedback network realizes closed-loop regulation of the output voltage. Under the condition that the LDO is enabled to be closed, the power tube can be ensured to be completely closed no matter the LDO is under the working voltage of 3V or 5V, so that the electric leakage condition of the LDO is greatly improved, and the LDO has the characteristic of low electric leakage.

The invention belongs to the field of power device driving, particularly relates to the technical field of crosstalk suppression, and more particularly relates to a crosstalk suppression driving circuit. Through cooperative work of the driving module, the detection module, the buffering module and the clamping module, crosstalk is effectively suppressed while the switching speed is ensured. The driving module ensures normal switching action of the power device; the detection module converts the drain voltage change rate into a detection signal in real time, and recognizes the crosstalk risk in advance; the buffer module suppresses forward crosstalk by absorbing grid forward voltage spikes; the clamping module immediately conducts a low-impedance path from the grid electrode to the negative power supply when the detection signal exceeds a threshold value, and negative crosstalk is quickly eliminated. According to the design, the suppression circuit is only activated when the voltage change rate exceeds the standard, switching delay caused by a traditional fixed buffer circuit is avoided, accurate and rapid crosstalk suppression can be achieved, and finally the suppression effect and the system reliability are remarkably improved while the high-speed switching performance is maintained.

Disclosed is a 3-terminal neuromorphic synaptic device including a substrate, a source electrode and a drain electrode provided on the substrate to be spaced apart from each other, a channel area provided on the substrate to be electrically connected to the source electrode and the drain electrode, between the source electrode and the drain electrode, an ion transport layer provided on the channel area, a gate electrode provided on the ion transport layer, and a voltage application part that applies a gate voltage to the gate electrode. The gate electrode is formed of at least one of an oxide-based material including mobile ions, a chalcogenide-based material including the mobile ions, and a nitride-based material including the mobile ions.

The invention relates to a high-side power NMOS (N-channel Metal Oxide Semiconductor) gate drive circuit in synchronous rectification buck. The high-side power NMOS gate drive circuit comprises a high-voltage storage circuit, a gate charge discharge circuit, a gate voltage control capacitor C2, a level shift circuit and a logic control circuit. The high-voltage storage circuit stores an input voltage VIN on a capacitor C1 and is used for shortening the conduction delay of a high-side power tube MLD1; when the low-side power tube MLD2 is conducted, the gate charge leakage circuit MN1 realizes complete turn-off of the tube MLD1, and prevents the high-side power tube MLD1 and the low-side power tube MLD2 from being conducted at the same time; the grid voltage controls the capacitor C2 to turn on and turn off the MN1 tube under the floating potential. The logic control circuit controls the conduction of the MLD1 and the MLD2 through a first signal SWH and a second signal SWL of the PWM generator, so that the conduction delay is further shortened; the level shift circuit converts a low level into a high level based on VIN so as to prevent the MOS tube from being broken down.

The invention discloses a modeling method of a simulation model, a storage medium and a terminal. The method comprises the following steps: acquiring an initial simulation model of a semiconductor device to be modeled; according to the initial simulation model, fitting a drain current-grid voltage characteristic curve of a sub-threshold region of the semiconductor device to be modeled; judging whether the to-be-modeled semiconductor device has subsurface leakage current in a subthreshold region of the drain current-grid voltage characteristic curve or not; if the secondary surface leakage current exists, establishing a sub-circuit model representing the secondary surface leakage current; integrating the sub-circuit model and the initial simulation model; and according to the integrated initial simulation model, fitting the drain current-grid voltage characteristic curve of the sub-threshold region until the fitting curve of the drain current-grid voltage characteristic curve converges, and obtaining a simulation model of the semiconductor device to be modeled. According to the modeling method, the secondary surface leakage current can be accurately modeled, and the simulation precision and accuracy of an integrated circuit simulation model are improved.

The invention relates to the technical field of analog and digital-analog hybrid integrated circuits, and discloses a bootstrap sampling switch circuit with a pre-charging function and an analog-to-digital converter. The circuit comprises a sampling switch module and a time sequence control module. The sampling switch module sequentially works at a holding phase, a pre-charging phase and a tracking phase under the control of a multi-phase clock signal generated by the time sequence control module, the pre-charging phase is added before the tracking phase, the grid voltage of a sampling switch is pre-boosted, and the pre-charging time is dynamically controlled by using an adjustable clock circuit, so that the pre-charging time of the sampling switch is dynamically controlled. Therefore, the charge sharing effect caused by the gate parasitic capacitance is effectively suppressed. The analog-to-digital converter comprises the sampling switch circuit. The linearity and the conduction characteristic of the sampling switch are remarkably improved, and the sampling switch has excellent time sequence configurability and is suitable for a high-speed and high-precision analog-to-digital conversion system.

A memory apparatus includes drain-side select gate transistors for coupling to a drain-side of memory holes of memory cells and configured to retain a drain-side transistor threshold voltage. The memory apparatus also includes source-side select gate transistors for coupling to a source-side of each of the memory holes and configured to retain a source-side transistor threshold voltage. A control means pre-reads the drain-side transistor threshold voltage of the drain-side select gate transistors and the source-side transistor threshold voltage of source-side select gate transistors of the memory holes having the memory cells being erased in an erase operation. The control means adjusts at least one of a drain-side select gate voltage applied to the drain-side select gate transistors and a source-side select gate voltage applied to the source-side select gate transistors based on at least one of the pre-read of the drain-side transistor threshold voltage and the source-side transistor threshold voltage.

In one or more examples, a display apparatus may include a display panel on which sub-pixels are arranged, each of the sub-pixels including an organic light-emitting diode and a driving transistor for driving the organic light-emitting diode, data lines disposed on the display panel and connected to the sub-pixels, gate lines disposed on the display panel and connected to the sub-pixels, sensing lines disposed on the display panel and connected to the sub-pixels, a data driving circuit configured to supply data voltages to the data lines, a gate driving circuit configured to supply gate voltages to the gate lines, a sensing circuit connected to the sensing lines to sense sensing voltages of the sub-pixels, and a controller configured to determine whether at least one of the driving transistor and the organic light-emitting diode is defective based on a sensing voltage sensed by the sensing circuit.

A masking circuit includes a ninth transistor including a control electrode connected to a second masking control node, a first electrode receiving a first clock signal, and a second electrode, a tenth transistor including a control electrode receiving a carry signal, a first electrode receiving a high gate voltage, and a second electrode connected to a first node, an eleventh transistor including a control electrode receiving a second enable signal, a first electrode connected to the first node, and a second electrode connected to the second masking control node, a twelfth transistor including a control electrode receiving a first enable signal, a first electrode connected to the second masking control node, and a second electrode connected to a second node, and a thirteenth transistor including a control electrode receiving the carry signal, a first electrode connected to the second node, and a second electrode receiving a low gate voltage.

An inverter driving apparatus is capable of resolving current imbalance of power modules having different threshold voltages for an inverter including a plurality of power modules connected in parallel. The inverter driving apparatus includes a gate driver configured to output a gate voltage to the plurality of power modules and monitor threshold voltages of the plurality of power modules, and a controller configured to output a PWM (Pulse Width Modulation) signal to the gate driver in response to a command input from the outside and output a voltage control signal to the gate driver, based on the threshold voltages. The gate driver may be configured to output the gate voltage, based on a feedback gate voltage that includes feedback regarding the gate voltage, the PWM signal, and the voltage control signal.

The invention belongs to the technical field of gate voltage bootstrapped switches, and discloses a high-performance gate voltage bootstrapped switch for a Sigma-Delta ADC, a PMOS switch circuit is introduced into an NMOS type gate voltage bootstrapped switch circuit to form a complementary switch, and the complementary switch is used for counteracting an output error caused by a clock feed-through effect of an NMOS switch and the PMOS switch; virtual tubes are added to the input and output ends of the NMOS switch and the PMOS switch by using an inverter chain and are used for absorbing channel charges of the switch tubes; the substrate potential of the NMOS switch and the substrate potential of the PMOS switch are connected into the switching circuit, so that the substrate potential of the switching tube is switched between GND and input voltage Vin, and on the premise that sampling / maintaining precision is guaranteed, interference of clock feed-through and charge injection in the switching tube on output signals is restrained, and the linearity of the grid voltage bootstrapped switch is improved.

This invention provides a radio frequency (RF) switch circuit and module. The RF switch circuit includes a first resistor and stacked switching units. Each stacked switching unit comprises multiple stages of stacked field-effect transistor (FET) circuits connected in series. Each stage of the stacked FET circuit includes a FET, a second resistor, and a bootstrap unit, which includes one or two bootstrap circuits. The bootstrap unit in each stage of the stacked FET circuit is used to raise the gate voltage of the corresponding FET during electrostatic discharge (ESD) to assist in turning on the FET and allowing the ESD current to be discharged through the path formed by the FET. This invention can prevent gate oxide breakdown or thermal damage caused by localized overheating of the FET acting as a switch during an ESD event in the RF switch circuit, thereby improving the stability of the RF switch circuit.

The present disclosure provides a fast voltage regulation control circuit of an LDO, and relates to the technical field of integrated circuits, the LDO comprising an input voltage terminal, a power tube, an LDO self-control circuit and an output voltage terminal, the power tube being coupled between the input voltage terminal and the output voltage terminal; the fast voltage regulation control circuit is coupled with the control electrode of the power tube to control the LDO to switch between a fast voltage regulation mode and a self-voltage regulation mode; when the LDO enters the self-voltage regulation mode, the gate voltage applied to the control electrode of the power tube comprises a first gate voltage applied to the control electrode by the LDO self-control circuit; when the LDO enters the fast voltage regulation mode, the gate voltage applied to the control electrode of the power tube comprises the first gate voltage applied to the control electrode by the LDO self-control circuit and a second gate voltage applied to the control electrode by the fast voltage regulation control circuit, so that the gate voltage of the control electrode of the power tube is equal to the sum of the first gate voltage and the second gate voltage, and fast voltage regulation of the LDO output is realized in the fast voltage regulation scenario.

Semiconductor device (100), comprising: a semiconductor substrate (10); a transistor section (70) and a diode section (80) arranged on the semiconductor substrate (10), wherein the transistor section (70) includes a gate trench section (40) arranged extending in a direction of extension which differs in plan view from the direction of arrangement; several terminal pads arranged above a top surface (21) of the semiconductor substrate (10) and arranged in an arrangement direction between a region in which the transistor section (70) or the diode section (80) is arranged and a first end face on the top surface (21) of the semiconductor substrate (10); and a gate runner section that transmits a gate voltage to the transistor section (70), wherein: The Gate Runner section contains: a first gate runner (50) which, in plan view, is arranged extending between the first end face of the semiconductor substrate (10) and at least one of the terminal surfaces; and a second gate runner (51) which, in plan view, is arranged between at least two of the several terminal surfaces and the transistor section (70), the transistor section (70) is also arranged in at least one of those intermediate terminal area regions (130) which are inserted between two terminal areas in plan view, the gate trench section (40), which is arranged in at least one intermediate connection area (130), is connected to the first gate runner (50), and the gate trench section (40), which is arranged so that it faces the second gate runner (51) in the direction of extension, is connected to the second gate runner (51).

A common-source cascode switching system and its operation method, as well as a half-bridge circuit, are disclosed. The common-source cascode switching system includes a JFET and a MOSFET coupled in series between the drain and source terminals, and a driving circuit. The driving circuit includes: a JFET driver that receives an input signal and outputs a JFET drive signal to a capacitor coupled in series with the gate of the JFET; a switch coupled between the gate and source terminals of the JFET and configured to respond to the input signal; and a comparator for comparing the JFET gate voltage with a threshold. The driving circuit also includes a MOSFET driver circuit to drive the MOSFET in a MOSFET on state during an input signal on state, and to drive the MOSFET in either a MOSFET off state or a MOSFET on state during an input signal off state in response to a comparison signal from the comparator.

An integrated circuit (100A) includes an H-bridge circuit (102) having a first output node (OUT1) for coupling to the high-side terminal of an inductor (103) and a second output node (OUT2) for coupling to the low-side terminal of the inductor. A current-sensing FET (SNS-DRV) is coupled between a current source (110) and a lower supply voltage to provide a reference current (Itrip), including a peak current limit at the sensing node. A current-sensing comparator (104) has a first input coupled to the sensing node, a second input coupled to the second output node, and an output (113) coupled to send an output signal to a driver control circuit. A FET linearity detection circuit (112) is coupled to receive the gate voltage (LS2) of an active low-side power FET (Mls2) and has an output (CMP EN) coupled to enable the current-sensing comparator when the active low-side power FET operates in the linear region.

The application discloses a preparation method of FE-DSOI wafers and FE-DSOI devices, and the method comprises the following steps: providing a plurality of original wafers; preparing a bottom wafer by using the original wafers; depositing ferroelectric material on the surface of the bottom wafer to obtain a bottom wafer containing ferroelectric material; performing thermal oxidation treatment on the original wafers to obtain a top wafer; and performing bonding and layer transfer treatment on the top wafer and the bottom wafer containing ferroelectric material, so as to obtain FE-DSOI wafers containing ferroelectric material and double buried oxide silicon. By using the application, the technical problems that the conventional DSOI does not have back gate regulation capability and cannot inhibit threshold voltage drift when no back gate voltage is continuously applied in the prior art can be solved.

This invention discloses a method and device structure for improving the electrical transport properties of etched graphene quantum dots, belonging to the field of low-temperature transport testing technology. The method includes the following steps: fabricating etched graphene quantum dot devices; performing preliminary electrical transport characterization by cooling; and undergoing several cycles of "sample electrode grounding protection – heating to above 200K or room temperature – cooling again – electrical transport characterization" to improve the electrical transport properties of the device, enabling subsequent observation and manipulation of the quantum dot's fine charge stability map. The optimized method of this invention, through several heating and cooling thermal cycles, successfully adjusts the coulomb blocking region of the graphene quantum dots from hundreds of volts towards zero, facilitating the application of a gate voltage. Furthermore, the charge stability map of the two quantum dots is significantly optimized and improved, greatly increasing the yield of etched graphene quantum dot devices. In addition, the optimized method of this invention is simple to operate and has significant effects, making it suitable for widespread application.

A method includes performing, by one or more controllers, operations including: receiving a pulse to control an operation of a power switch including a gate terminal; generating, based on the received pulse, a first signal to the gate terminal to increase a gate voltage level of the power switch at a first rate from an off-state gate voltage level to a first on-state gate voltage level in a first time period; and generating, based on the received pulse, a second signal to the gate terminal to increase the gate voltage level of the power switch at a second rate, less than the first rate, to a second on-state gate voltage level in a second time period subsequent to the first time period.

A display device includes a display panel including a pixel, a gate driver which provides a plurality of gate signals to the pixel, a data driver which provides a data voltage to the pixel in an address scan period and does not provide the data voltage to the pixel in a self-scan period, and a power management circuit which provides high gate voltages of the gate signals to the gate driver. A level of a high gate voltage which is one of the high gate voltages in the self-scan period may be different from a level of the high gate voltage in the address scan period.

A system for viral monitoring in effluent includes at least one graphene-based field-effect transistor and circuitry, wherein the circuitry is configured to repeatedly monitor and determine presence of SARS-CoV-2 (COVID virus) in the effluent. The circuitry is configured to apply a gate voltage and measure a conductance across each of the at least one graphene-based field-effect transistor, compare the measured conductance across each of the at least one graphene-based field-effect transistor to a threshold conductance, and determine whether levels of the COVID virus exceed a predetermined threshold in the effluent. If levels of the COVID virus exceed the predetermined threshold in the effluent, the circuitry is configured to remove at least a portion of the bound COVID virus from the proteins of the at least one graphene-based field-effect transistor.

The invention provides a mobility separation method and device for a core-shell structure junctionless transistor, and the method comprises the steps: obtaining a first relation curve of drain current-gate voltage and a second relation curve of gate channel capacitance-gate voltage, determining first gate voltage when a core layer in the core-shell structure junctionless transistor is in a flat band based on the second relation curve, and separating the mobility of the core-shell structure junctionless transistor from the first gate voltage. In the first relation curve, determining the drain current corresponding to the grid voltage as the first grid voltage as the first current in the core layer, and according to the first relation curve and the first current, determining the second current in the shell layer of the junction-free transistor with the core-shell structure. And according to the second current, the transconductance of the second current to the gate voltage, the gate voltage and the first gate voltage, determining the first mobility of the shell layer in the core-shell structure junctionless transistor. In short, the current in the single channel is separated from the total current, and then the mobility corresponding to the channel is determined based on the current in the single channel, so that accurate characterization of the mobility of each channel is realized.

The application provides a GaN amplitude-phase control multifunctional chip and a phased array system, and belongs to the technical field of microelectronics. The GaN amplitude-phase control multifunctional chip comprises an input port, an output port, a distributed current multiplexing amplifier, a phase shifter, a first DC blocking capacitor and a second DC blocking capacitor; the distributed current multiplexing amplifier comprises a first switch tube, a second switch tube, a first gate voltage supply circuit, a DC self-bias circuit, a negative feedback circuit, a first choke filter circuit, a second gate voltage supply circuit, a second choke filter circuit and a voltage source. The application is based on the above-mentioned components and the connection relationship between the components, so that the push stage amplifier in the GaN amplitude-phase control multifunctional chip adopts a distributed current multiplexing structure, thereby reducing the power consumption of the push stage amplifier, improving the efficiency of the GaN amplitude-phase control multifunctional chip, and enabling the GaN amplitude-phase control multifunctional chip to realize high efficiency under the condition of small size and high power.

The invention belongs to the technical field of micro-nano semiconductor electronic devices, and discloses a reconfigurable field effect transistor based on different-surface contact electrodes and a preparation method of the reconfigurable field effect transistor. The transistor comprises a SiO2 / Si substrate, an hBN passivation layer, a source / drain Au electrode, a MoTe2 channel, an hBN dielectric layer, a graphene gate and a top gate Au electrode from bottom to top, the source electrode, the drain electrode and the channel form different-surface contact, and an air cavity is formed between the channel and the dielectric layer. The air cavity causes the top gate electric field to generate asymmetric regulation and control on the channel, so that one end of the channel is kept in an eigenstate, and the other end of the channel is regulated and controlled by the gate voltage to form an n-type or p-type region, thereby forming an ni or pi homojunction in the single channel, and realizing reconfigurable carrier transport polarity. The invention further provides a preparation method based on dry transfer, the process is simple, and the preparation method is suitable for a reconfigurable logic circuit and a nano electronic system.

The invention relates to a driving circuit and method with wide-range adjustment and high turn-on rate, and relates to the technical field of power semiconductor device driving. The circuit comprises an energy storage capacitor, first to fourth MOS transistors, first to third DC power supplies, a charging resistor and a first diode. Wherein the energy storage capacitor is connected to the third MOS tube through the charging resistor to form an adjustable charging loop with the second direct-current power supply; meanwhile, a low-impedance discharging path connected with the charging resistor in parallel is formed through the first diode and the second MOS tube; the first direct-current power supply provides steady-state grid voltage, and the third direct-current power supply and the fourth MOS tube form a turn-off loop. The invention has the following beneficial effects: the turn-on rate can be continuously set in a wide range by adjusting the voltage of the second direct-current power supply; and the low-impedance discharge path can provide extremely high transient driving current to realize high-speed turn-on.

The application provides a neuron-like transistor device, which comprises a substrate, a buried oxygen layer and a channel layer which are sequentially stacked on the substrate, a gate oxide layer and a gate electrode on the channel layer, and a source electrode and a drain electrode which are respectively located on both sides of the channel layer. The gate electrode is used for applying a front gate voltage as an input signal, the drain electrode is used for applying a constant input current, the voltage of the drain electrode is used as an output signal, and the input signal is changed in a step-by-step manner from small to large. The neuron nonlinear activation of a single device is realized, and it is possible to build a complete and programmable artificial neuron by using a single or few transistors. The neuron-like transistor device has a simple structure, and a manufacturing process which is suitable for a CMOS manufacturing process. The measurement method of the neuron-like transistor device is simple, and an electrode does not need to be additionally introduced, so that the simulation of the neuron characteristics can be realized without additional device design, the integration density of the transistors in a chip is improved, and the neuron-like transistor device is suitable for the integration of a large-scale circuit.