1757 results about "Gate voltage" patented technology

The invention discloses a self-adaptive nanosecond driving protection method for a high-voltage IGBT power module. The method comprises the steps that data such as high-voltage side voltage, collector current, grid voltage and junction temperature are collected and preprocessed, and standardized feature vectors are obtained; extracting statistical features, frequency domain features and trend features to obtain a comprehensive feature vector; density clustering is carried out based on historical fault data, and an extreme value model is established by using generalized Pareto distribution to generate an optimized threshold value; constructing a time sequence feature matrix, predicting a fault probability by adopting a time sequence convolutional network and a long-short term memory network, and generating a protection strategy parameter; and generating an optimal driving waveform and a control signal, and updating parameters according to an actual response effect. According to the invention, predictive protection and nanosecond-level precise control of faults are realized, and the reliability and performance of the high-voltage IGBT module are remarkably improved.

The invention provides a power management chip high-low side driving signal time sequence optimization method and system. The method comprises the following steps: acquiring temperature data of a power management chip under a switch switching transient working condition through an infrared thermal imaging technology, and synchronously acquiring three-dimensional temperature field distribution of junction temperatures on the surface and inside a packaging layer; based on the space continuity of a temperature field, extracting the temperature change characteristics of a power device area, converting the temperature gradient into Seebeck voltage by using a thermoelectric material embedded in a hot spot area, and constructing a dynamic thermoelectric feedback network; according to Seebeck voltage data, a coupling relation between hot carrier concentration and driving signal phase deviation is established, and disturbance of hot carrier mobility change on MOSFET switching delay is quantified; the rising / falling edge slope of the grid voltage is adjusted based on the coupling relation, the phase deviation caused by the hot carrier effect is eliminated through dynamic compensation, and the switching performance is optimized. The dynamic response precision of the power management chip is improved.

The invention provides a single molecule detection device and method based on an electrochemical gating technology in a quantum tunneling region, and relates to a detection technology for regulating molecular energy level alignment and regulating molecular conductance through gate voltage, a functionalized tunneling electrode is prepared at the tip of a nano pipettor and is placed in a solution containing single molecules, and the electrochemical gating technology in the quantum tunneling region is used for detecting the single molecules in the nano pipettor. The gate potential and the bias voltage are dynamically adjusted, tunneling current signals flowing through the single molecule are recorded and analyzed in real time, the structure, the charge state and the energy state of the single molecule can be actively regulated and controlled, and dynamic detection of the single molecule is achieved according to the conductivity change spectrum of the single molecule under different potential conditions. And the single molecule detection precision based on the tunneling electrode is obviously improved.

According to the SiC MOSFET global short circuit and overcurrent protection circuit and the control method thereof provided by the invention, when a short circuit fault occurs in the SiC MOSFET, the drain current ID is more than several times of the rated current of the SiC MOSFET. When a short circuit occurs, a transistor QDZ of the short circuit detection circuit is switched on by node voltage Vr of the resistance-capacitance filter circuit, a fault signal VFAULT is converted into a low level, grid voltage VGS output by the grid control unit is gradually converted into zero voltage from negative driving voltage VEE, and soft turn-off is performed on the SiC MOSFET; when an over-current fault occurs in the SiC MOSFET, drain current ID is higher than rated current, node voltage Vo of the resistance-capacitance filter circuit lasts for a long time, the maximum value of capacitor voltage Vch of the over-current detection circuit is higher than reference voltage Vref2, a fault signal VFAULT is converted into low level, grid voltage VGS output by the grid control unit is gradually converted into zero voltage from negative driving voltage VEE, and soft turn-off is performed on the SiC MOSFET. According to the invention, high-speed short circuit and over-current fault protection of the SiC MOSFET in all inductance regions of a commutation loop can be realized.

The utility model relates to the technical field of power semiconductor devices, and discloses a super-junction VDMOS device resistant to static breakdown, which comprises a drain electrode and a grid electrode, an N + substrate is deposited on the upper surface of the drain electrode, a buffer layer is arranged above the N + substrate, a first N-epitaxial layer grows on the upper surface of the buffer layer, and a second N-epitaxial layer grows on the lower surface of the buffer layer. A first N-epitaxial layer is grown on the substrate, a P-region is formed in the first N-epitaxial layer through ion implantation diffusion, a second N-epitaxial layer grows on the first N-epitaxial layer, highly-doped P columns are arranged on the two sides in the second N-epitaxial layer, a heavily-doped region hole potential barrier region is arranged on one side of each P column, and a lightly-doped region hole potential well region is arranged on the lower side of one side of each P column. According to the VDMOS device, the thickness of the gate dielectric layer is increased, the total thickness of the gate dielectric layer is 100 nm, the single-particle shrinkage-through effect of the VDMOS device can be effectively improved, the gate dielectric layer is composed of 20 nm silicon dioxide and 80 nm trisilicon nitride, the single-particle shrinkage-through resistance characteristic of the device is further improved, and under the same gate voltage, gate-source electric leakage is reduced.

The invention relates to the technical field of power electronic device diagnosis, and discloses a reverse conducting IGBT intelligent power module fault automatic diagnosis method and system. The method comprises the following steps: acquiring multi-source monitoring data including a grid voltage waveform, a collector current waveform and a shell temperature change curve when the power module operates; then establishing a dynamic feature extraction model, performing time domain and frequency domain conjoint analysis on the multi-source monitoring data, and generating a feature parameter set; then constructing a fault feature space, and mapping the feature parameter set to a high-dimensional space to form a feature vector distribution diagram; carrying out regional division on the feature vector distribution map by adopting a self-adaptive clustering algorithm, and identifying an abnormal feature aggregation region; and finally, comparing the abnormal feature gathering area with a preset fault feature library through a mode matching engine, and outputting a fault type identification result. According to the method, multi-source data can be integrated to realize dynamic feature extraction and adaptive fault identification, and the real-time performance and accuracy of fault diagnosis are improved.

The present disclosure provides a pixel driving circuit and a display panel, including a driving transistor connected in series with a light emitting element between a first power supply line and a second power supply line; a data transistor electrically connected to a gate of the driving transistor; a boost module configured to be loaded with a boost input signal, where an output terminal of the boost module is electrically connected to the gate of the driving transistor to enable the voltage of the gate of the driving transistor to boost from the first voltage to the second voltage, and the first capacitor and the second capacitor are connected in series between the first wiring and the gate of the driving transistor.

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

The invention discloses a power device driver and a parameter correction method thereof, which are applied to the technical field of power device driving, and are characterized in that a data acquisition module acquires grid voltage and peak current of an IGBT (Insulated Gate Bipolar Translator) in the working process of the IGBT to obtain sampling data; the digital isolation chip realizes electrical isolation among the data acquisition module, the MCU and the grid voltage regulation module; the MCU calibrates the real-time junction temperature data based on the sampling data by using a preset junction temperature calibration formula and outputs calibrated junction temperature data; the gate driving chip outputs a gate voltage capable of driving the IGBT according to the control signal; the second-order short-circuit protection module sends an abnormal signal to the MCU when the IGBT is short-circuited, so that the MCU sends a grid voltage regulation trigger signal to the grid voltage regulation module; the grid voltage adjusting module responds to the grid voltage adjusting trigger signal and controls itself to reduce the grid voltage. Based on the power device driver and the parameter correction method thereof provided by the invention, the junction temperature monitoring precision and reliability are improved.

The invention relates to the technical field of electronic circuits, in particular to a threshold voltage control system and control equipment of a field effect transistor. Comprising a main feedback loop used for obtaining an actual value of a threshold voltage of a field effect transistor, comparing the actual value of the threshold voltage with a set value to obtain a deviation signal, and sending the deviation signal to a control module; the auxiliary feedback loop is used for collecting the current change rate of the field effect transistor and sending the current change rate to the control module; the control module is used for generating a control signal according to the deviation signal and the current change rate and adjusting the grid voltage of the field effect transistor according to the control signal so as to control the threshold voltage of the field effect transistor. According to the invention, the main feedback loop and the auxiliary feedback loop cooperatively collect the voltage deviation signal and the current change rate of the field effect transistor so as to dynamically adjust the grid voltage of the field effect transistor, thereby improving the control precision.

The invention discloses an AC voltage stabilizer dynamic regulation system based on an intelligent algorithm, and relates to the technical field of AC voltage stabilizers, and the system comprises a data collection module which is used for collecting a gate voltage waveform of an IGBT of an AC voltage stabilizer and an AC voltage instantaneous value of a power grid input end of the AC voltage stabilizer; the data processing module is used for determining a first Shannon entropy value of a rising edge and a second Shannon entropy value of a falling edge of the gate voltage according to the gate voltage waveform; determining an entropy change difference quantity between the rising edge and the falling edge according to the first Shannon entropy value and the second Shannon entropy value; determining a power grid input fluctuation quantity according to the AC voltage instantaneous value; if the power grid input fluctuation quantity is smaller than a fluctuation threshold value and the entropy change difference quantity is larger than a first preset difference threshold value, generating an inversion signal compensation waveform according to the gate voltage waveform; and injecting the inverted signal compensation waveform into a PWM modulator of the AC voltage stabilizer. According to the invention, the accuracy of identifying the real disturbance caused by the external power grid of the AC voltage stabilizer is improved.

A high-linearity grid voltage bootstrap circuit relates to the technical field of analog-to-digital conversion and comprises a first charge pump boosting unit, a second charge pump boosting unit and a grid voltage bootstrap unit, working states of a sampling switch are divided into a sampling state and a holding state, an input voltage VIN is boosted to a VG through the grid voltage bootstrap unit in a sampling stage, and the sampling switch is switched on; and the holding stage sampling switch is cut off, and charges are injected to the upper polar plates of the capacitors C3 and C4 of the gate voltage bootstrap unit through the first charge pump boosting unit and the second charge pump boosting unit respectively. According to the invention, the problem that the actual gate-source voltage is reduced due to the grid parasitic capacitance of the sampling switch is solved, and the layout area occupation is greatly reduced while the bootstrap voltage is improved; the proportion of the capacitor C3 and the capacitor C4 can be flexibly set to obtain the required bootstrap voltage; and the problem that the on-resistance of the sampling switch is increased due to the reduction of the gate-source voltage can be solved, and the linearity of the sampling switch is improved.

A gate driver includes first to nth stages. A kth stage among the first to nth stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

A buffer circuit configured to generate an output voltage according to an input voltage includes: an input stage configured to provide first and second differential currents to a load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage; a load stage configured to apply gate voltages to first and second output transistors of an output stage based on the first through fourth differential currents; the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage.

The invention relates to a class-C voltage-controlled oscillator with negative-pressure substrate bias and a use method thereof. Aiming at the problem that a traditional C-type voltage-controlled oscillator is difficult to start, the C-type voltage-controlled oscillator provided by the scheme adopts different circuits to simultaneously control the grid voltage and the substrate voltage of the cross-coupled pair transistors, so that the transistors are effectively prevented from entering a linear region, and the C-type voltage-controlled oscillator is quickly started and stably works in a C-type oscillation mode. The circuit structure of the scheme comprises an NMOS (N-channel Metal Oxide Semiconductor) cross coupling circuit, a PMOS (P-channel Metal Oxide Semiconductor) cross coupling circuit, an LC resonant cavity circuit, an amplitude detection circuit, a Schmidt signal processing circuit and a negative voltage charge pump circuit. Wherein the Schmidt signal processing circuit and the negative voltage charge pump circuit rapidly process an initial oscillation signal and provide negative voltage required by the system, and a substrate of the NMOS cross coupling tube is biased. According to the scheme, the design structure is simple, the tuning range is wide, and a new thought is provided for research and design of quick start of the C-type voltage-controlled oscillator.

A display device includes a display panel including an active pixel and a reference pixel, a reference pixel measurer which applies a reference data voltage and a gate voltage to the reference pixel, calculates a first threshold voltage and a second threshold voltage based on a driving current of the reference pixel and calculates a difference between the first threshold voltage and the second threshold voltage, and a driving controller which controls the reference pixel measurer and outputs a data signal based on the difference.

A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

The invention relates to the technical field of MOS transistors, and discloses a low-power-consumption operation control method, device and equipment of an MOS transistor and a storage medium, and the method comprises the steps: collecting the working state feature data of the MOS transistor; performing change trend analysis on the working state characteristic data to obtain a current power consumption state and a power consumption fluctuation range; executing optimal threshold voltage adjustment parameter calculation based on the current power consumption state and the power consumption fluctuation range to obtain a target threshold voltage value; executing body bias control and grid voltage compensation according to the target threshold voltage value to obtain a body bias voltage control signal and a grid voltage control signal; and the power supply voltage and the working frequency of the MOS transistor are dynamically adjusted according to the body bias voltage and the grid voltage control signal, a voltage frequency working point is obtained, the sudden load change is rapidly responded, meanwhile, all control parameters are accurately adjusted, and the global optimal operation state of the MOS transistor is achieved.

An on-period of a second gate electrode is shorter than an on-period of a first gate electrode in a period from when the first gate electrode is turned on until the first gate electrode is turned off. An on-period of a third gate electrode is shorter than the on-period of the second gate electrode in the period from when the first gate electrode is turned on until the first gate electrode is turned off. A timing at which a third gate voltage of the third gate electrode reaches a third threshold voltage and a start timing of a third Miller period of the third gate voltage are within a first Miller period of a first gate voltage of the first gate electrode and within a second Miller period of a second gate voltage of the second gate electrode.

The application relates to a high-order curvature compensation band gap reference circuit, which comprises a first-order band gap reference circuit, a high-temperature region curvature compensation circuit and a starting circuit. The first-order band gap reference voltage is realized by the following technologies: the voltage generated by the current of PMOS tube M4 on resistors R3-R4 and the voltage generated by the current of PMOS tube M6 on resistor R4 both have positive temperature coefficients, the voltage generated by the current of PMOS tube M5 on resistors R3-R4 and the voltage generated by the current of PMOS tube M7 on resistor R4 both have negative temperature coefficients; the working area of NMOS tube M13 gradually changes from the deep triode region, the triode region to the saturation region with the increase of temperature by controlling the working of NMOS tube M13 by the technology that the gate voltage of NMOS tube M12 increases with the increase of temperature, so that the current of PMOS tube M14 is high-order nonlinear with temperature, and the first-order band gap reference voltage is temperature compensated, thereby obtaining the high-order temperature compensation band gap voltage.

A gate driver includes first to nth stages. A kth stage among the first to nth stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k-1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

A three terminal neuromorphic synaptic device and a method for manufacturing the same are provided. The three terminal neuromorphic synaptic device includes a substrate, source / drain electrodes provided on the substrate, a channel region electrically connected between the source electrode and the drain electrode, an ion transfer layer provided on the channel region, a gate electrode provided on the ion transfer layer, and a voltage application unit to apply a gate voltage to the gate electrode. The ion transfer layer includes an electrolyte material to transfer an active ion of the gate electrode between the gate electrode and the channel region, in response to the gate voltage applied to the gate electrode. The voltage application unit adjusts a resistance and a conductance of the channel region by changing an amount of active ions accumulated in the channel region, depending on the number of times that the gate voltage is applied.

The invention provides a numerical control delayer, a four-digit numerical control delayer and a manufacturing method of a chip of the four-digit numerical control delayer. The delayer comprises a first single-pole double-throw switch, a second single-pole double-throw switch, a delay unit and a reference unit, the first single-pole double-throw switch comprises two stages of triodes S1 and S2 which are connected in parallel; the second single-pole double-throw switch comprises a triode S3 and a triode S4 which are connected in parallel; one end of the delay unit is connected with the drain electrode of S1, and the other end is connected with the drain electrode of S3; one end of the reference unit is connected with the drain of S2, and the other end is connected with the drain of S4; drain electrodes of the S1 and the S2 are connected with a radio frequency signal input port; drain electrodes of the S3 and the S4 are connected with a radio frequency signal output port; source electrodes of the S1, the S2, the S3 and the S4 are all in direct current grounding, grid electrodes of the S1, the S2, the S3 and the S4 are all connected with a voltage control unit, and on and off of each triode are controlled by controlling grid electrode voltage, so that the delayer is switched between a reference state and a delay state. According to the invention, the insertion loss of the delayer in the millimeter wave frequency band can be reduced.

The utility model relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a SiC VDMOSFET (Vertical Double-diffused Metal Oxide Semiconductor Field Effect Transistor) structure for improving dynamic characteristics, which comprises a SiC VDMOSFET structure formed by mutually connecting a plurality of VDMOS cells in parallel, each VDMOS cell comprises a drain electrode, a metal source electrode, a grid electrode and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, an N well layer, a P well layer and a depletion layer; wherein the N well layer is isolated from the diffusion layer by the P well layer, and the N well layer is in ohmic short circuit with the metal source electrode. According to the utility model, the charge conduction performance of the depletion layer is changed by doping phosphorus elements with different concentrations in the depletion layer region, the depletion layer has a better charge attraction effect in a conduction state, and the JFET region is reduced to the third region of the depletion layer along with the increase of the grid voltage, so that the conductivity of a charge channel is multiplied, and the conductivity of the charge channel is improved. Therefore, bidirectional optimization of switching loss and switching EMI noise can be realized, and the purpose of improving the dynamic characteristics of the device is achieved.

The invention discloses a photoelectric synapse device based on a floating gate structure and a preparation method. The photoelectric synapse device comprises a substrate; the Ta2NiSe5 nanosheet is prepared on the substrate, and the Ta2NiSe5 nanosheet is prepared on the substrate; the h-BN nanosheet is prepared on the substrate, and the h-BN nanosheet partially covers the Ta2NiSe5 nanosheet; the ReS2 nanosheet is prepared on the h-BN nanosheet; the control electrode is prepared on the part, not covered by the h-BN nanosheet, of the Ta2NiSe5 nanosheet, the source electrode and the drain electrode are prepared on the h-BN nanosheet, the ReS2 nanosheet is partially covered with the source electrode, the ReS2 nanosheet is partially covered with the drain electrode, and the part, covered with the ReS2 nanosheet, of the source electrode does not coincide with the part, covered with the ReS2 nanosheet, of the drain electrode. According to the photoelectric synapse device based on the floating gate structure, the number of carriers of the Ta2NiSe5 nanosheet layer and the number of carriers of the ReS2 nanosheet layer can be adjusted through a low gate voltage signal and a low-power optical signal so as to adjust the storage state, and the power consumption of the device is reduced on the premise that the data processing efficiency is guaranteed.

This disclosure provides a charge pump circuit. The charge pump circuit according to this disclosure includes one or more cascaded boost units and output units having the same structure. Each boost unit has a dual-branch structure with top and bottom symmetry and connected to two sets of four-phase clock signals with opposite clock phases. By adjusting the phase relationship of the four-phase clocks, the rise time of the gate voltage of the transfer transistor can be delayed by advancing the falling edge of the driving clock of the secondary capacitor and delaying its rising edge. This ensures that the transfer transistor is in the off state at the moment of high-low phase switching, thereby avoiding the problem of reduced charge transfer efficiency caused by reverse charge flow between the input and output nodes of the boost unit.

Load disconnect techniques for boost converters. In an example, a power converter includes a driver circuit, a control circuit, and a comparator circuit. During normal boost operation (VIN<VOUT), the comparator circuit disables the control circuit and enables the driver circuit, which in turn fully turns on a high-side switching element during high-side on-phase. In contrast, during start-up operation or an output short-to-ground condition (VIN≥VOUT), the comparator circuit disables the driver circuit and enables the control circuit, which in turn controls the gate voltage of the high-side switching element, so the current through the switching element is regulated, and the switching node voltage is regulated to about a threshold voltage higher than VIN. In this manner, the comparator circuit controls the driver circuit and the control circuit, which in turn allow the boost converter to operate in a normal fashion even when VIN is higher than VOUT.

A driver includes a plurality of stages. At least one stage includes: an input circuit configured to transfer an input signal to a Q node in response to a first clock signal, where the Q node includes a first Q node and a second Q node; a QB node controlling circuit configured to control a voltage of a QB node based on a voltage of the first Q node and a QB control signal; an output circuit configured to output an output signal, which has a high gate voltage, based on a voltage of the second Q node, and configured to output the output signal, which has a low gate voltage, based on the voltage of the QB node; and a QB node discharging circuit configured to discharge the QB node when the high gate voltage and the low gate voltage are deactivated.

The invention relates to the technical field of battery pack linkage, and discloses a multi-string battery pack voltage collection and protection linkage method and device and computer equipment, and the method comprises the steps: carrying out the data collection of each series unit in a multi-string battery pack, and obtaining basic monitoring data; performing junction temperature calculation on power loss and thermal resistance characteristics of the MOSFET devices in each series unit to obtain real-time junction temperature data; carrying out oscillation frequency detection on the grid voltage change of the MOSFET device in each series unit to obtain grid oscillation frequency data, and carrying out thermal resistance oscillation coupling detection to obtain a dynamic protection threshold parameter; performing temperature compensation and cross interference elimination on the voltage acquisition channel of each series unit to obtain target voltage data; according to the anti-oscillation locking protection method, the problem that the MOSFET fails due to overheating is effectively prevented, the coordinated protection among the series units is ensured, and the influence of single-point failure on the whole battery pack is avoided.

The invention discloses a driving circuit, a driving chip and a display device. The driving circuit comprises a current source which comprises a source branch and a plurality of mirror image branches, each mirror image branch comprises a first driving transistor, at least part of the first driving transistors are gated to provide driving current for a load in the output stage of the driving circuit, and a plurality of gate end charging and discharging units are arranged on the source branch and the mirror image branches. Each gate end charging and discharging unit is used for providing gate end charging current or gate end discharging current for the first driving transistor in the corresponding mirror image branch; and the bias unit is used for providing adjustable bias current for the plurality of gate end charging and discharging units so as to adjust the gate voltage rising / falling slope of the first driving transistors in the plurality of mirror image branches. The grid voltage rising / falling slope of the grid end of the first driving transistor in each mirror image branch is adjusted through the adjustable current source and the grid end charging and discharging unit, so that the change rate of the driving current is adjusted, and electromagnetic interference caused by rapid change of the driving current can be avoided.