2484 results about "Gate voltage" patented technology

The invention discloses a self-adaptive nanosecond driving protection method for a high-voltage IGBT power module. The method comprises the steps that data such as high-voltage side voltage, collector current, grid voltage and junction temperature are collected and preprocessed, and standardized feature vectors are obtained; extracting statistical features, frequency domain features and trend features to obtain a comprehensive feature vector; density clustering is carried out based on historical fault data, and an extreme value model is established by using generalized Pareto distribution to generate an optimized threshold value; constructing a time sequence feature matrix, predicting a fault probability by adopting a time sequence convolutional network and a long-short term memory network, and generating a protection strategy parameter; and generating an optimal driving waveform and a control signal, and updating parameters according to an actual response effect. According to the invention, predictive protection and nanosecond-level precise control of faults are realized, and the reliability and performance of the high-voltage IGBT module are remarkably improved.

The invention provides a power management chip high-low side driving signal time sequence optimization method and system. The method comprises the following steps: acquiring temperature data of a power management chip under a switch switching transient working condition through an infrared thermal imaging technology, and synchronously acquiring three-dimensional temperature field distribution of junction temperatures on the surface and inside a packaging layer; based on the space continuity of a temperature field, extracting the temperature change characteristics of a power device area, converting the temperature gradient into Seebeck voltage by using a thermoelectric material embedded in a hot spot area, and constructing a dynamic thermoelectric feedback network; according to Seebeck voltage data, a coupling relation between hot carrier concentration and driving signal phase deviation is established, and disturbance of hot carrier mobility change on MOSFET switching delay is quantified; the rising / falling edge slope of the grid voltage is adjusted based on the coupling relation, the phase deviation caused by the hot carrier effect is eliminated through dynamic compensation, and the switching performance is optimized. The dynamic response precision of the power management chip is improved.

The invention discloses a SiC MOSFET gate oxide layer degradation monitoring method based on turn-off oscillation, and the method comprises the steps: measuring the drain-source current change rate diDS / dt when a SiC MOSFET is turned off through the source stray inductance voltage vcir, and carrying out the measurement of the gate oxide layer degradation of the SiC MOSFET based on the offset of the negative temperature sensitivity of the threshold voltage VTH in the diDS / dt and the positive temperature sensitivity of the electron mobility mu. Zero temperature sensitivity of a source stray inductance voltage negative peak value vcircmin is realized by adjusting a driving resistor RG and a negative voltage VEE during turn-off, and the gate oxide layer degradation degree of the SiC MOSFET is monitored under a selected monitoring driving resistor RGM and a turn-off gate voltage VEEM. The monitoring method is high in universality and has a good monitoring effect on degradation of gate oxide layers of SiC MOSFETs of different models; the temperature influence is extremely small, so that the device can work in an environment with large temperature fluctuation; a pin of a monitored device does not need to be used as a measurement interface, so that the system invasiveness is small; the parameter measurement methods are many and mature; and the method has great online application potential.

The present invention relates to organic thin film sensors and the preparation and use thereof in sensing applications, and in particular in glucose sensing. The sensor is characterised by a layered structure comprising a porous wicking layer whose surface is configured to receive a liquid sample. An enzyme is disposed on or within the porous layer for facilitating the generation of a charge carrier from an analyte. A polymer layer in contact with the porous layer is connected to an ohmic conductor for applying a gate voltage to the polymer layer, the polymer layer being conductive to the charge carrier; and an organic semiconducting layer is connected to a source electrode and a drain electrode.

The invention provides a single molecule detection device and method based on an electrochemical gating technology in a quantum tunneling region, and relates to a detection technology for regulating molecular energy level alignment and regulating molecular conductance through gate voltage, a functionalized tunneling electrode is prepared at the tip of a nano pipettor and is placed in a solution containing single molecules, and the electrochemical gating technology in the quantum tunneling region is used for detecting the single molecules in the nano pipettor. The gate potential and the bias voltage are dynamically adjusted, tunneling current signals flowing through the single molecule are recorded and analyzed in real time, the structure, the charge state and the energy state of the single molecule can be actively regulated and controlled, and dynamic detection of the single molecule is achieved according to the conductivity change spectrum of the single molecule under different potential conditions. And the single molecule detection precision based on the tunneling electrode is obviously improved.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with low threshold voltage, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, an N well layer, a P well layer and a heavily doped P layer are formed in the semiconductor epitaxial layer through ion implantation, the grid electrode comprises a triangular grid electrode and a rectangular grid electrode, the grid oxide layer covering the surface of the triangular grid electrode is in contact with the N substrate layer, and the N drift layer is divided into a left part and a right part by the grid oxide layer. According to the invention, the grid electrode is designed to further comprise the triangular grid electrode, the electric field effect of the grid electrode between the tip part of the triangular grid electrode and the drain electrode is better, but the grid oxide layer wrapped by the triangular grid electrode at the tip part is thicker, so that charges flowing out of the drain electrode gather towards the inside of the heavily doped N layer more quickly along the grid oxide layer; at the moment, more charge flow can be provided in a smaller grid voltage environment.

The invention discloses an in-memory computing array and an operation method thereof, and belongs to the technical field of semiconductors and CMOS hybrid integrated circuits. A 2T1R in-memory computing array based on subthreshold current is designed, each unit in the array is composed of a memristor, a gate tube T1 and a reading tube T2, write-in and erase operations are similar to a 1T1R array architecture, but read-out is carried out through the transistor T2 working in a subthreshold region, the reading current generated by the reading tube is small, and the read-in and erase operations can be carried out through the memristor, the gate tube T1 and the reading tube T2. And the parallelism degree of in-memory calculation is increased, and ultrahigh parallel calculation of 100-1000 orders of magnitude can be realized. And meanwhile, the reading current of the reading tube T2 is in exponential correlation with the gate voltage, so that a larger switching current ratio can be obtained, and a reading window of the in-memory calculation unit is amplified. Compared with a 1T1R array architecture, more complex in-memory calculation operation can be realized, and an operation strategy can be flexibly selected, so that more efficient multiply-accumulate operation is realized.

According to the SiC MOSFET global short circuit and overcurrent protection circuit and the control method thereof provided by the invention, when a short circuit fault occurs in the SiC MOSFET, the drain current ID is more than several times of the rated current of the SiC MOSFET. When a short circuit occurs, a transistor QDZ of the short circuit detection circuit is switched on by node voltage Vr of the resistance-capacitance filter circuit, a fault signal VFAULT is converted into a low level, grid voltage VGS output by the grid control unit is gradually converted into zero voltage from negative driving voltage VEE, and soft turn-off is performed on the SiC MOSFET; when an over-current fault occurs in the SiC MOSFET, drain current ID is higher than rated current, node voltage Vo of the resistance-capacitance filter circuit lasts for a long time, the maximum value of capacitor voltage Vch of the over-current detection circuit is higher than reference voltage Vref2, a fault signal VFAULT is converted into low level, grid voltage VGS output by the grid control unit is gradually converted into zero voltage from negative driving voltage VEE, and soft turn-off is performed on the SiC MOSFET. According to the invention, high-speed short circuit and over-current fault protection of the SiC MOSFET in all inductance regions of a commutation loop can be realized.

The invention discloses an accelerated degradation model of a SiC MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) under alternating gate drive, which takes gate negative bias voltage, junction temperature, multiple stresses of gate voltage rise time and switching times as inputs and threshold voltage variation as outputs, solves the problem of inaccurate threshold voltage drift prediction of the SiC MOSFET under alternating-current BTI (Bias Temperature Instability), and improves the prediction accuracy of the SiC MOSFET under alternating-current BTI. The method can be used for describing the SiC MOSFET threshold voltage degradation rule in the alternating gate drive mode. According to the invention, the change rule of key performance parameters in the long-term use process of the SiC MOSFET device can be reflected, and the method has important significance for accurately evaluating and optimizing and improving the use reliability of the device.

The embodiment of the invention provides an IGBT second-class short circuit process transient voltage and current evaluation method and device, and the method comprises the steps: responding to the second-class short circuit of an IGBT chip until the short circuit current reaches a peak value, and building a relation model between the collector current and the commutation loop voltage according to circuit parameters; establishing a relation model of collector current and grid voltage by utilizing physical characteristics of a chip device; establishing a relation model between the collector-emitter voltage and the chip collector-emitter voltage according to the capacitance effect; according to the relation model of the collector current and the commutation loop voltage, the relation model of the collector current and the grid voltage and the relation model of the collector and emitter voltage and the chip collector and emitter voltage, the collector and emitter voltage and the collector and emitter voltage of the IGBT chip are determined; according to the IGBT state detection method and device, the IGBT second-class short circuit transient voltage and current are analyzed by obtaining the circuit parameters, and the accuracy and reliability of IGBT state detection are improved.

The utility model relates to the technical field of power semiconductor devices, and discloses a super-junction VDMOS device resistant to static breakdown, which comprises a drain electrode and a grid electrode, an N + substrate is deposited on the upper surface of the drain electrode, a buffer layer is arranged above the N + substrate, a first N-epitaxial layer grows on the upper surface of the buffer layer, and a second N-epitaxial layer grows on the lower surface of the buffer layer. A first N-epitaxial layer is grown on the substrate, a P-region is formed in the first N-epitaxial layer through ion implantation diffusion, a second N-epitaxial layer grows on the first N-epitaxial layer, highly-doped P columns are arranged on the two sides in the second N-epitaxial layer, a heavily-doped region hole potential barrier region is arranged on one side of each P column, and a lightly-doped region hole potential well region is arranged on the lower side of one side of each P column. According to the VDMOS device, the thickness of the gate dielectric layer is increased, the total thickness of the gate dielectric layer is 100 nm, the single-particle shrinkage-through effect of the VDMOS device can be effectively improved, the gate dielectric layer is composed of 20 nm silicon dioxide and 80 nm trisilicon nitride, the single-particle shrinkage-through resistance characteristic of the device is further improved, and under the same gate voltage, gate-source electric leakage is reduced.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a shallow-channel super-junction MOS device and a preparation process thereof, the shallow-channel super-junction MOS device comprises a drain electrode, a source electrode, a semiconductor epitaxial layer, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and the semiconductor epitaxial layer comprises an N substrate layer and a drift layer; a P well layer, a P-layer II and an N well layer are formed in the drift layer through ion implantation; the cross section of the grid electrode is T-shaped; a first P-layer is formed in the N well layer through ion implantation, and a narrow heavily doped N layer is formed in the drift layer and located between two adjacent second P-layers through ion implantation. After the gate voltage is accessed, a charge channel is formed in the P-layer 2, so that the N-well layer and the drift layer can form a path, and the existence of the P-layer 1 can inhibit the collection of charges flowing in the N-well layer to the gate region, so that the number of parasitic charges can be greatly reduced, and the response speed of the MOS semiconductor device is improved.

The invention relates to the technical field of power electronic device diagnosis, and discloses a reverse conducting IGBT intelligent power module fault automatic diagnosis method and system. The method comprises the following steps: acquiring multi-source monitoring data including a grid voltage waveform, a collector current waveform and a shell temperature change curve when the power module operates; then establishing a dynamic feature extraction model, performing time domain and frequency domain conjoint analysis on the multi-source monitoring data, and generating a feature parameter set; then constructing a fault feature space, and mapping the feature parameter set to a high-dimensional space to form a feature vector distribution diagram; carrying out regional division on the feature vector distribution map by adopting a self-adaptive clustering algorithm, and identifying an abnormal feature aggregation region; and finally, comparing the abnormal feature gathering area with a preset fault feature library through a mode matching engine, and outputting a fault type identification result. According to the method, multi-source data can be integrated to realize dynamic feature extraction and adaptive fault identification, and the real-time performance and accuracy of fault diagnosis are improved.

The invention provides a power conversion device and a control method thereof, and a switch driving chip, and relates to the technical field of switch control, the power conversion device comprises a controller, a first switch tube and a second switch tube, the controller provides a first driving current for a grid electrode of the first switch tube when a turn-off moment of the first switch tube arrives, and the controller provides a second driving current for a grid electrode of the second switch tube when the turn-off moment of the second switch tube arrives; when the voltage difference of the first switch tube is greater than or equal to a first threshold value, a second driving current is provided for the grid of the first switch tube so as to control the voltage of the grid of the first switch tube to rise; and when the voltage difference of the first switching tube is greater than or equal to a second threshold value, or the time duration for providing the second driving current is greater than or equal to a time threshold value, providing a third driving current for the grid electrode of the first switching tube to control the voltage of the grid electrode of the first switching tube to drop to turn off. According to the invention, the generation of voltage stress and EMI can be reduced, the turn-off speed of the first switching tube is improved, the turn-off loss is reduced, and the applicability is high.

The invention provides a method for testing a power device and a test circuit for realizing the test method, and the method comprises the steps: applying a negative grid voltage to a grid of a to-be-tested device, and applying a test voltage to a source and a drain of the to-be-tested device, so as to carry out the body diode bipolar degradation test of the to-be-tested device; after the body diode bipolar degradation test is performed on the device to be tested, applying a grid pre-bias voltage to the grid of the device to be tested so as to eliminate the threshold drift of the device to be tested; and after the threshold drift of the to-be-tested device is eliminated, applying double-pulse voltage to the source electrode and the drain electrode of the to-be-tested device so as to perform double-pulse test on the to-be-tested device. According to the method, the problem that the threshold voltage drift of the silicon carbide device is not fully considered in the prior art is solved by applying the grid pre-bias voltage, the double-pulse test is directly carried out after the bipolar degradation experiment of the body diode is finished, the influence of inconsistent retest time on the test result is avoided, and meanwhile, the test efficiency is remarkably improved.

The invention discloses a rapid discharge circuit suitable for a high-voltage LDO and a discharge method thereof, the rapid discharge circuit comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4, an NMOS tube M5, an NMOS tube M6, an NMOS tube M7, a current source I0 and a Zener diode Z2, the source electrodes of the PMOS tubes M1, M2 and M3 are connected with an input power supply Vin, the PMOS tubes M1, M2 and M3 form a current mirror, the drain electrode of the NMOS tube M4 and the NMOS tube M6 form a current mirror, an input signal EN controls the NMOS tube M7, and the Zener diode Z2 limits the grid voltage of the NMOS tube M5. According to the high-voltage LDO, the function of rapidly discharging the output signal Vout in the turn-off state of the high-voltage LDO can be achieved through a small turn-off current and a simple circuit structure.

The invention discloses a quasi one-dimensional (TaSe4) 2I and two-dimensional MoTe2 mixed-dimensional heterojunction phototransistor detector and a preparation method thereof, the detector sequentially comprises a Si substrate, a SiO2 gate dielectric layer, a quasi one-dimensional (TaSe4) 2I and two-dimensional MoTe2 nano film from bottom to top, the quasi one-dimensional (TaSe4) 2I and MoTe2 nano film are respectively provided with a metal electrode, and a heterostructure of the (TaSe4) 2I, the MoTe2 and the metal electrodes is formed. The preparation method comprises the following steps: (1) transferring the (TaSe4) 2I nanowire to the Si substrate; (2) transferring the MoTe2 nano film to one side of the (TaSe4) 2I nanowire; (3) preparing a pattern of a bottom electrode; (4) positioning, exposing and developing the pattern of the bottom electrode to expose the electrode part needing to be evaporated; and (5) preparing a metal electrode. According to the invention, the composite effect of a (TaSe4) 2I / MoTe2 heterojunction is utilized, and dark current is inhibited through a vertical structure; moTe2 is utilized to increase light absorption, and meanwhile, grid voltage is applied, so that light current is improved, and high responsivity and external quantum efficiency are obtained.

An object is to provide a technique that suppresses heat generation in a first semiconductor switching element and a second semiconductor switching element. A semiconductor device includes a gate drive circuit that drives each of the first semiconductor switching element and the second semiconductor switching element based on an input signal. When a first gate voltage applied to the first gate to turn On the first semiconductor switching element is lower than a first threshold, the gate drive circuit turns Off the first semiconductor switching element after turns Off the second semiconductor switching element regardless of the input signal.

The present disclosure provides a pixel driving circuit and a display panel, including a driving transistor connected in series with a light emitting element between a first power supply line and a second power supply line; a data transistor electrically connected to a gate of the driving transistor; a boost module configured to be loaded with a boost input signal, where an output terminal of the boost module is electrically connected to the gate of the driving transistor to enable the voltage of the gate of the driving transistor to boost from the first voltage to the second voltage, and the first capacitor and the second capacitor are connected in series between the first wiring and the gate of the driving transistor.

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

A power converter incorporating a synchronous rectifier implements adaptive gate voltage regulation for fast turn-off of the synchronous rectifier. In some embodiments, the adaptive gate voltage regulation circuit and method monitors the slope of the synchronous rectifier current during the on period of the synchronous rectifier. In response to detecting the synchronous rectifier current decreasing rapidly, a larger gate discharge current is applied to quickly discharge the synchronous rectifier gate voltage. In response to detecting the synchronous rectifier current decreasing more moderately, a smaller gate discharge current is applied to discharge the synchronous rectifier gate voltage in a moderate manner. When the synchronous rectifier can be turned off quickly, large reverse current and large drain voltage spike at the synchronous rectifier is avoided. The adaptive gate voltage regulation circuit and method is particularly useful when the power converter is operated in the discontinuous conduction mode.

A power supply having ORing MOSFETs mounts a voltage regulating unit between a main power module and an auxiliary power module of a secondary side of the power supply. The voltage regulating unit regulates a control voltage received by a driving unit, such that a voltage difference between a gate voltage and a source voltage of one of the ORing MOSFETs can be less than a rated voltage threshold for avoiding damaging the one ORing MOSFET.

The invention discloses a power device driver and a parameter correction method thereof, which are applied to the technical field of power device driving, and are characterized in that a data acquisition module acquires grid voltage and peak current of an IGBT (Insulated Gate Bipolar Translator) in the working process of the IGBT to obtain sampling data; the digital isolation chip realizes electrical isolation among the data acquisition module, the MCU and the grid voltage regulation module; the MCU calibrates the real-time junction temperature data based on the sampling data by using a preset junction temperature calibration formula and outputs calibrated junction temperature data; the gate driving chip outputs a gate voltage capable of driving the IGBT according to the control signal; the second-order short-circuit protection module sends an abnormal signal to the MCU when the IGBT is short-circuited, so that the MCU sends a grid voltage regulation trigger signal to the grid voltage regulation module; the grid voltage adjusting module responds to the grid voltage adjusting trigger signal and controls itself to reduce the grid voltage. Based on the power device driver and the parameter correction method thereof provided by the invention, the junction temperature monitoring precision and reliability are improved.

The invention relates to the technical field of electronic circuits, in particular to a threshold voltage control system and control equipment of a field effect transistor. Comprising a main feedback loop used for obtaining an actual value of a threshold voltage of a field effect transistor, comparing the actual value of the threshold voltage with a set value to obtain a deviation signal, and sending the deviation signal to a control module; the auxiliary feedback loop is used for collecting the current change rate of the field effect transistor and sending the current change rate to the control module; the control module is used for generating a control signal according to the deviation signal and the current change rate and adjusting the grid voltage of the field effect transistor according to the control signal so as to control the threshold voltage of the field effect transistor. According to the invention, the main feedback loop and the auxiliary feedback loop cooperatively collect the voltage deviation signal and the current change rate of the field effect transistor so as to dynamically adjust the grid voltage of the field effect transistor, thereby improving the control precision.

The invention discloses an AC voltage stabilizer dynamic regulation system based on an intelligent algorithm, and relates to the technical field of AC voltage stabilizers, and the system comprises a data collection module which is used for collecting a gate voltage waveform of an IGBT of an AC voltage stabilizer and an AC voltage instantaneous value of a power grid input end of the AC voltage stabilizer; the data processing module is used for determining a first Shannon entropy value of a rising edge and a second Shannon entropy value of a falling edge of the gate voltage according to the gate voltage waveform; determining an entropy change difference quantity between the rising edge and the falling edge according to the first Shannon entropy value and the second Shannon entropy value; determining a power grid input fluctuation quantity according to the AC voltage instantaneous value; if the power grid input fluctuation quantity is smaller than a fluctuation threshold value and the entropy change difference quantity is larger than a first preset difference threshold value, generating an inversion signal compensation waveform according to the gate voltage waveform; and injecting the inverted signal compensation waveform into a PWM modulator of the AC voltage stabilizer. According to the invention, the accuracy of identifying the real disturbance caused by the external power grid of the AC voltage stabilizer is improved.

A high-linearity grid voltage bootstrap circuit relates to the technical field of analog-to-digital conversion and comprises a first charge pump boosting unit, a second charge pump boosting unit and a grid voltage bootstrap unit, working states of a sampling switch are divided into a sampling state and a holding state, an input voltage VIN is boosted to a VG through the grid voltage bootstrap unit in a sampling stage, and the sampling switch is switched on; and the holding stage sampling switch is cut off, and charges are injected to the upper polar plates of the capacitors C3 and C4 of the gate voltage bootstrap unit through the first charge pump boosting unit and the second charge pump boosting unit respectively. According to the invention, the problem that the actual gate-source voltage is reduced due to the grid parasitic capacitance of the sampling switch is solved, and the layout area occupation is greatly reduced while the bootstrap voltage is improved; the proportion of the capacitor C3 and the capacitor C4 can be flexibly set to obtain the required bootstrap voltage; and the problem that the on-resistance of the sampling switch is increased due to the reduction of the gate-source voltage can be solved, and the linearity of the sampling switch is improved.

A gate driver includes first to nth stages. A kth stage among the first to nth stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

A buffer circuit configured to generate an output voltage according to an input voltage includes: an input stage configured to provide first and second differential currents to a load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage; a load stage configured to apply gate voltages to first and second output transistors of an output stage based on the first through fourth differential currents; the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage.

A semiconductor device includes an output element, a temperature detection circuit, a current limiting circuit, and an overcurrent detection circuit. The output element is a power semiconductor element that drives a load, and is turned on by applying a predetermined turn-on voltage to a gate of the output element in a normal state. The temperature detection circuit detects the temperature of the output element as a detected temperature, during the operation of the output element. The overcurrent detection circuit detects an overcurrent state of the output element. When the overcurrent state is detected and the detected temperature exceeds a set temperature, the current limiting circuit sets a gate voltage of the output element to a set voltage lower than the predetermined turn-on voltage. In addition, the current limiting circuit increases the set voltage in stages as the temperature decreases.