1240 results about "Gate voltage" patented technology

The invention provides a power management chip high-low side driving signal time sequence optimization method and system. The method comprises the following steps: acquiring temperature data of a power management chip under a switch switching transient working condition through an infrared thermal imaging technology, and synchronously acquiring three-dimensional temperature field distribution of junction temperatures on the surface and inside a packaging layer; based on the space continuity of a temperature field, extracting the temperature change characteristics of a power device area, converting the temperature gradient into Seebeck voltage by using a thermoelectric material embedded in a hot spot area, and constructing a dynamic thermoelectric feedback network; according to Seebeck voltage data, a coupling relation between hot carrier concentration and driving signal phase deviation is established, and disturbance of hot carrier mobility change on MOSFET switching delay is quantified; the rising / falling edge slope of the grid voltage is adjusted based on the coupling relation, the phase deviation caused by the hot carrier effect is eliminated through dynamic compensation, and the switching performance is optimized. The dynamic response precision of the power management chip is improved.

The invention relates to the technical field of power electronic device diagnosis, and discloses a reverse conducting IGBT intelligent power module fault automatic diagnosis method and system. The method comprises the following steps: acquiring multi-source monitoring data including a grid voltage waveform, a collector current waveform and a shell temperature change curve when the power module operates; then establishing a dynamic feature extraction model, performing time domain and frequency domain conjoint analysis on the multi-source monitoring data, and generating a feature parameter set; then constructing a fault feature space, and mapping the feature parameter set to a high-dimensional space to form a feature vector distribution diagram; carrying out regional division on the feature vector distribution map by adopting a self-adaptive clustering algorithm, and identifying an abnormal feature aggregation region; and finally, comparing the abnormal feature gathering area with a preset fault feature library through a mode matching engine, and outputting a fault type identification result. According to the method, multi-source data can be integrated to realize dynamic feature extraction and adaptive fault identification, and the real-time performance and accuracy of fault diagnosis are improved.

The present disclosure provides a gate driving circuit and a display panel. by the control of one of the fourth node, the output end of the second output module, and the first node of the shift register of the next stage, the voltage regulating module may utilize a low voltage signal to stabilize or reduce the gate voltage of the second transistor, so that the second transistor is stable or preferably in the cut-off state to reduce the leakage current. In this way, voltage level of the second gate driving signal can be maintained at a high voltage level or a pulse amplitude.

The invention discloses an AC voltage stabilizer dynamic regulation system based on an intelligent algorithm, and relates to the technical field of AC voltage stabilizers, and the system comprises a data collection module which is used for collecting a gate voltage waveform of an IGBT of an AC voltage stabilizer and an AC voltage instantaneous value of a power grid input end of the AC voltage stabilizer; the data processing module is used for determining a first Shannon entropy value of a rising edge and a second Shannon entropy value of a falling edge of the gate voltage according to the gate voltage waveform; determining an entropy change difference quantity between the rising edge and the falling edge according to the first Shannon entropy value and the second Shannon entropy value; determining a power grid input fluctuation quantity according to the AC voltage instantaneous value; if the power grid input fluctuation quantity is smaller than a fluctuation threshold value and the entropy change difference quantity is larger than a first preset difference threshold value, generating an inversion signal compensation waveform according to the gate voltage waveform; and injecting the inverted signal compensation waveform into a PWM modulator of the AC voltage stabilizer. According to the invention, the accuracy of identifying the real disturbance caused by the external power grid of the AC voltage stabilizer is improved.

A high-linearity grid voltage bootstrap circuit relates to the technical field of analog-to-digital conversion and comprises a first charge pump boosting unit, a second charge pump boosting unit and a grid voltage bootstrap unit, working states of a sampling switch are divided into a sampling state and a holding state, an input voltage VIN is boosted to a VG through the grid voltage bootstrap unit in a sampling stage, and the sampling switch is switched on; and the holding stage sampling switch is cut off, and charges are injected to the upper polar plates of the capacitors C3 and C4 of the gate voltage bootstrap unit through the first charge pump boosting unit and the second charge pump boosting unit respectively. According to the invention, the problem that the actual gate-source voltage is reduced due to the grid parasitic capacitance of the sampling switch is solved, and the layout area occupation is greatly reduced while the bootstrap voltage is improved; the proportion of the capacitor C3 and the capacitor C4 can be flexibly set to obtain the required bootstrap voltage; and the problem that the on-resistance of the sampling switch is increased due to the reduction of the gate-source voltage can be solved, and the linearity of the sampling switch is improved.

A gate driver includes first to nth stages. A kth stage among the first to nth stages includes a first transistor including a second terminal electrically connected to a first control node, a fifth transistor including a gate electrically connected to an inverting control node, a sixth transistor including a gate electrically connected to a second control node, a fourth transistor including a gate which receives a low gate voltage, a first terminal electrically connected to a first control node, a second terminal electrically connected to a second control node, and a back gate, and a seventh transistor including a gate which receives a voltage of the inverting control node of a k+1th stage, a first terminal which receives a voltage of the first control node or the second control node of a k−1th stage, and a second terminal electrically connected to the back gate of the fourth transistor.

A buffer circuit configured to generate an output voltage according to an input voltage includes: an input stage configured to provide first and second differential currents to a load stage or receive third and fourth differential currents from the load stage based on a difference between the input voltage and the output voltage; a load stage configured to apply gate voltages to first and second output transistors of an output stage based on the first through fourth differential currents; the output stage configured to regulate the output voltage based on the gate voltages applied to the first and the second output transistors; and a slew rate compensator configured to regulate the gate voltages of the first and second output transistors by providing a source current to the load stage or receiving a sink current from the load stage.

A method of driving a transistor between switching states includes controlling a transition of a gate voltage at a gate terminal of a transistor during each of a plurality of turn-off switching events to turn off the transistor, wherein the transistor is configured to be turned off according to a desaturation time during each of the plurality of turn-off switching events; measuring a transistor parameter indicative of a voltage slew rate of the transistor for a first turn-off switching event during which the transistor is transitioned from an on state to an off state; and regulating a duration of the desaturation time for a next turn-off switching event based on the measured transistor parameter.

The invention relates to the technical field of MOS transistors, and discloses a low-power-consumption operation control method, device and equipment of an MOS transistor and a storage medium, and the method comprises the steps: collecting the working state feature data of the MOS transistor; performing change trend analysis on the working state characteristic data to obtain a current power consumption state and a power consumption fluctuation range; executing optimal threshold voltage adjustment parameter calculation based on the current power consumption state and the power consumption fluctuation range to obtain a target threshold voltage value; executing body bias control and grid voltage compensation according to the target threshold voltage value to obtain a body bias voltage control signal and a grid voltage control signal; and the power supply voltage and the working frequency of the MOS transistor are dynamically adjusted according to the body bias voltage and the grid voltage control signal, a voltage frequency working point is obtained, the sudden load change is rapidly responded, meanwhile, all control parameters are accurately adjusted, and the global optimal operation state of the MOS transistor is achieved.

The application relates to a high-order curvature compensation band gap reference circuit, which comprises a first-order band gap reference circuit, a high-temperature region curvature compensation circuit and a starting circuit. The first-order band gap reference voltage is realized by the following technologies: the voltage generated by the current of PMOS tube M4 on resistors R3-R4 and the voltage generated by the current of PMOS tube M6 on resistor R4 both have positive temperature coefficients, the voltage generated by the current of PMOS tube M5 on resistors R3-R4 and the voltage generated by the current of PMOS tube M7 on resistor R4 both have negative temperature coefficients; the working area of NMOS tube M13 gradually changes from the deep triode region, the triode region to the saturation region with the increase of temperature by controlling the working of NMOS tube M13 by the technology that the gate voltage of NMOS tube M12 increases with the increase of temperature, so that the current of PMOS tube M14 is high-order nonlinear with temperature, and the first-order band gap reference voltage is temperature compensated, thereby obtaining the high-order temperature compensation band gap voltage.

This disclosure provides a charge pump circuit. The charge pump circuit according to this disclosure includes one or more cascaded boost units and output units having the same structure. Each boost unit has a dual-branch structure with top and bottom symmetry and connected to two sets of four-phase clock signals with opposite clock phases. By adjusting the phase relationship of the four-phase clocks, the rise time of the gate voltage of the transfer transistor can be delayed by advancing the falling edge of the driving clock of the secondary capacitor and delaying its rising edge. This ensures that the transfer transistor is in the off state at the moment of high-low phase switching, thereby avoiding the problem of reduced charge transfer efficiency caused by reverse charge flow between the input and output nodes of the boost unit.

The invention discloses a grid voltage bootstrapped switch circuit with compensation and an ADC, and belongs to the technical field of integrated circuits. The circuit comprises a compensation charge pump circuit and a grid voltage bootstrapped switch circuit. A charge pump branch power supply end in the grid voltage bootstrap switch circuit is connected to an output compensation voltage end of the compensation charge pump circuit; when the input clock signal CLK1 is low and the input clock signal CLK2 is high in level, the power supply end of the charge pump branch is switched off, and the capacitor in the charge pump circuit is compensated for charging; when the level of the CLK1 is high and the level of the CLK2 is low, the power supply end of the charge pump branch is switched on, a bootstrap capacitor in the grid voltage bootstrap switch circuit is charged, and the Vboost provides compensation voltage. The compensation charge pump circuit provides higher power supply voltage for the grid voltage bootstrap switch, grid voltage drop of the sampling switch tube caused by parasitic capacitance at the positive end of the bootstrap capacitor can be compensated back, input parasitic capacitance is reduced, on-resistance of the sampling switch tube is reduced, and sampling linearity is improved.

A gate driver includes a plurality of stages. Each of the stages comprises a control circuit configured to receive an input signal in response to a first clock signal and control a voltage of a control node and a voltage of an inverted control node based on the input signal, a carry output circuit configured to output a high gate voltage or a second clock signal as a carry signal in response to the voltage of the control node and the voltage of the inverted control node, and a gate output circuit configured to output the high gate voltage or a gate clock signal as a gate signal in response to the voltage of the control node and the voltage of the inverted control node.

The invention relates to the technical field of electronic circuits, in particular to a field effect transistor dynamic threshold voltage measuring method and system. The method comprises the following steps: generating a high-speed pulse signal with preset rise time through a pulse signal generator; applying the high-speed pulse signal to the grid electrode of the field-effect tube to be tested, and collecting the voltage waveform of the grid electrode of the field-effect tube through an oscilloscope, and recording the voltage waveform as a grid electrode voltage waveform; the current probe monitors the current response of the drain electrode of the field effect transistor in real time, the current response is recorded as drain electrode current response, and the sampling rate of the drain electrode current response is synchronous with the sampling rate of the grid voltage waveform. According to the invention, the channel establishment delay is quantified in situ on the electrical characteristic, so that the threshold voltage is redefined by the potential at the completion moment of the channel formation, and the concealment of the transient characteristic caused by direct current slow scanning is eliminated.

An emission driver includes a plurality of stages. Each stage includes an input block that transfers an input signal to a control node, a control block that controls an inverted control node and applies a third low gate voltage to the inverted control node in response to a voltage of the control node, an emission signal output block that outputs a high gate voltage as an emission signal in response to the voltage of the control node and outputs a first low gate voltage as the emission signal in response to a voltage of the inverted control node, and a carry signal output block that outputs the high gate voltage as a carry signal in response to the voltage of the control node and outputs a second low gate voltage different from the first low gate voltage as the carry signal in response to the voltage of the inverted control node. The third low gate voltage is different from the first low gate voltage and the second low gate voltage.

The invention discloses an LDO (Low Dropout Regulator) circuit based on a level conversion and pre-adjustment module. The LDO circuit comprises a reference source, an error amplifier, a pre-adjustment module, a level conversion module, a power switch tube P1, a power circuit tube N1 and resistance feedback networks R1 and R2. The pre-adjustment module carries out voltage reduction processing on an input high-voltage power supply, and the level conversion module generates bias voltage according to an enable signal and the high-voltage power supply, controls a power switch and a switch in the operational amplifier, and ensures that the circuit is resistant to high voltage and extremely low in drain. The error amplifier adjusts the grid voltage of the power circuit according to the feedback and reference voltage difference value, and controls the current to stably output the voltage. And the resistance feedback network realizes closed-loop regulation of the output voltage. Under the condition that the LDO is enabled to be closed, the power tube can be ensured to be completely closed no matter the LDO is under the working voltage of 3V or 5V, so that the electric leakage condition of the LDO is greatly improved, and the LDO has the characteristic of low electric leakage.

The invention belongs to the field of power device driving, particularly relates to the technical field of crosstalk suppression, and more particularly relates to a crosstalk suppression driving circuit. Through cooperative work of the driving module, the detection module, the buffering module and the clamping module, crosstalk is effectively suppressed while the switching speed is ensured. The driving module ensures normal switching action of the power device; the detection module converts the drain voltage change rate into a detection signal in real time, and recognizes the crosstalk risk in advance; the buffer module suppresses forward crosstalk by absorbing grid forward voltage spikes; the clamping module immediately conducts a low-impedance path from the grid electrode to the negative power supply when the detection signal exceeds a threshold value, and negative crosstalk is quickly eliminated. According to the design, the suppression circuit is only activated when the voltage change rate exceeds the standard, switching delay caused by a traditional fixed buffer circuit is avoided, accurate and rapid crosstalk suppression can be achieved, and finally the suppression effect and the system reliability are remarkably improved while the high-speed switching performance is maintained.

Disclosed is a 3-terminal neuromorphic synaptic device including a substrate, a source electrode and a drain electrode provided on the substrate to be spaced apart from each other, a channel area provided on the substrate to be electrically connected to the source electrode and the drain electrode, between the source electrode and the drain electrode, an ion transport layer provided on the channel area, a gate electrode provided on the ion transport layer, and a voltage application part that applies a gate voltage to the gate electrode. The gate electrode is formed of at least one of an oxide-based material including mobile ions, a chalcogenide-based material including the mobile ions, and a nitride-based material including the mobile ions.

There is provided a gate drive circuit that controls a gate voltage applied to a gate terminal of a switching element and drives the switching element. The gate drive circuit includes an overcurrent detection circuit that detects an overcurrent state based on a value of a current flowing through the switching element. A monitor voltage of a power supply line that is connected to the switching element and supplies power to the switching element is input to the overcurrent detection circuit, and the overcurrent detection circuit detects an overvoltage state when the monitor voltage is equal to or greater than a predetermined threshold value.

A regulator for a load voltage includes a pass transistor for a load current, a gate voltage sensor coupled to a gate of the pass transistor, and a feed-forward supply noise cancellation circuit configured to amplify a gain of a supply noise cancelling signal at increments of the gate voltage.

The invention provides a current test discharge method and system based on active discharge and segmented control, and the method comprises the steps: monitoring the voltage of an energy storage capacitor after the current test of a chip is completed; when the voltage is greater than a first threshold value, entering a constant-current discharge mode, and in the constant-current discharge mode, adjusting the grid voltage of the MOS tube according to the voltage value, and maintaining the discharge current to be a set value constantly; the voltage of the energy storage capacitor continues to be monitored, when the voltage is smaller than a first threshold value and larger than a second threshold value, an exponential decay mode is switched, and in the exponential decay mode, the voltage of the grid electrode of the MOS tube continues to be adjusted; when the voltage is smaller than the second threshold value, the MOS tube is closed, and the discharging process is completed. The technical problems of non-uniform energy release, large transient impact, long discharge time and the like existing in a traditional discharge mode are effectively solved through precise control of two stages of constant current discharge and exponential decay.

The invention belongs to the technical field of motors, and discloses anti-electromagnetic interference magnetic suspension controller equipment and a filtering method. The method comprises the following steps: preparing a quantum confinement magnetic permeability unit, acquiring magnetic flux and temperature data in a magnetic core in real time through an embedded sensor array, and building a corresponding magnetic permeability regulation and control model; the output of the magnetic conductivity regulation and control model is obtained, and real-time inductance is obtained through analysis; on the basis of the real-time inductance, in combination with a preset target inductance, compensating the real-time inductance through a grid voltage regulation and inductance compensation cooperation strategy; according to the compensated real-time inductance, a PID controller is adopted for filtering; under the strong magnetic field and high temperature coupling environment, the nonlinear decrease amplitude of the magnetic conductivity can be effectively reduced, the drift amount of the inductance value, the cut-off frequency offset of the filter and the current ripple can be reduced, the rotor suspension precision can be improved, and the filtering stability and the control reliability of a magnetic suspension system under the extreme environment can be remarkably improved.

Systems and methods for modulating conductance of a plurality of unit cells are described. A controller can determine a plurality of conductance values for a plurality of unit cells arranged in a crossbar arrangement. The plurality of unit cells can include non-volatile memory devices. The plurality of conductance values can be less than maximum conductance values of the plurality of unit cells. The controller can determine a read gate voltage for driving a plurality of access transistors to read from connected to the plurality of unit cells under a read operation. The controller can map a plurality of weights to the plurality of conductance values and to the read gate voltage.

The invention relates to a high-side power NMOS (N-channel Metal Oxide Semiconductor) gate drive circuit in synchronous rectification buck. The high-side power NMOS gate drive circuit comprises a high-voltage storage circuit, a gate charge discharge circuit, a gate voltage control capacitor C2, a level shift circuit and a logic control circuit. The high-voltage storage circuit stores an input voltage VIN on a capacitor C1 and is used for shortening the conduction delay of a high-side power tube MLD1; when the low-side power tube MLD2 is conducted, the gate charge leakage circuit MN1 realizes complete turn-off of the tube MLD1, and prevents the high-side power tube MLD1 and the low-side power tube MLD2 from being conducted at the same time; the grid voltage controls the capacitor C2 to turn on and turn off the MN1 tube under the floating potential. The logic control circuit controls the conduction of the MLD1 and the MLD2 through a first signal SWH and a second signal SWL of the PWM generator, so that the conduction delay is further shortened; the level shift circuit converts a low level into a high level based on VIN so as to prevent the MOS tube from being broken down.

The invention discloses a modeling method of a simulation model, a storage medium and a terminal. The method comprises the following steps: acquiring an initial simulation model of a semiconductor device to be modeled; according to the initial simulation model, fitting a drain current-grid voltage characteristic curve of a sub-threshold region of the semiconductor device to be modeled; judging whether the to-be-modeled semiconductor device has subsurface leakage current in a subthreshold region of the drain current-grid voltage characteristic curve or not; if the secondary surface leakage current exists, establishing a sub-circuit model representing the secondary surface leakage current; integrating the sub-circuit model and the initial simulation model; and according to the integrated initial simulation model, fitting the drain current-grid voltage characteristic curve of the sub-threshold region until the fitting curve of the drain current-grid voltage characteristic curve converges, and obtaining a simulation model of the semiconductor device to be modeled. According to the modeling method, the secondary surface leakage current can be accurately modeled, and the simulation precision and accuracy of an integrated circuit simulation model are improved.

A system for prognosis and control of a power module includes a gate driver circuit and a controller circuit. The gate driver circuit drives a target gate node of a target power transistor in response to a pulse width modulation signal, measures a target gate voltage, switches a desaturation signal in response to the target power transistor switching between an off state and an on state, measures a target transistor voltage, and measures a target transistor current. The controller circuit modulates the pulse width modulation signal to increase the target gate voltage, determines a target threshold voltage as the target gate voltage in response to the desaturation signal switching states, determines a target on-resistance based on the target transistor voltage and the target transistor current, and controls the target power transistor based on the target threshold voltage and the target on-resistance.

The invention relates to the technical field of analog and digital-analog hybrid integrated circuits, and discloses a bootstrap sampling switch circuit with a pre-charging function and an analog-to-digital converter. The circuit comprises a sampling switch module and a time sequence control module. The sampling switch module sequentially works at a holding phase, a pre-charging phase and a tracking phase under the control of a multi-phase clock signal generated by the time sequence control module, the pre-charging phase is added before the tracking phase, the grid voltage of a sampling switch is pre-boosted, and the pre-charging time is dynamically controlled by using an adjustable clock circuit, so that the pre-charging time of the sampling switch is dynamically controlled. Therefore, the charge sharing effect caused by the gate parasitic capacitance is effectively suppressed. The analog-to-digital converter comprises the sampling switch circuit. The linearity and the conduction characteristic of the sampling switch are remarkably improved, and the sampling switch has excellent time sequence configurability and is suitable for a high-speed and high-precision analog-to-digital conversion system.

The invention relates to a feedback-based self-adaptive grid voltage regulation synchronous rectification method and a chip, which are executed in a synchronous rectification chip of a power supply circuit. A voltage signal VKA between the drain electrode and the source electrode of the synchronous rectification MOS tube is detected, a feedback signal V 'KA is formed through adaptive filtering, and the driving module dynamically adjusts the grid voltage Vgs according to the V' KA. When the V 'KA is lower than a conduction detection threshold VON, the MOS tube is completely conducted; when the V 'KA rises to be close to a pre-turn-off trigger threshold value VREADY-OFF, the Vgs is dynamically reduced to increase the on resistance, so that the MOS tube is kept in an incomplete conduction state; in the state, the V 'KA is continuously monitored, when the V' KA is lower than the VON again, complete conduction is recovered, only when the V 'KA continuously rises and reaches a turn-off threshold VOFF, the MOS tube is completely turned off, and if the above conditions are not met, the MOS tube is maintained in an incomplete conduction state. According to the adaptive closed-loop adjustment method, the conduction loss and the grid driving loss can be effectively reduced, and the power supply conversion efficiency and the system reliability are improved.

A gate driver on array (GOA) circuit includes a first GOA unit. The first GOA circuit includes a first pull-up control module that includes a first transistor, having a gate receiving a control signal, a source receiving a starting signal, and a drain electrically connected to a first node. When the first transistor is turned off, a voltage level of the gate of the first transistor is lower than a voltage level of the source; the source of the first transistor is an end for signal inputting; and the drain of the first transistor is an end for signal outputting.

Provided in the present invention are a current mirror circuit, a multi-channel LED drive circuit and a drive system. The current mirror circuit comprises a first mirroring transistor, which generates a first bias voltage on the basis of a reference current; an independent control module, which is connected between a gate of the first mirroring transistor and a gate of a second mirroring transistor and, on the basis of an enable signal, turns on or off the second mirroring transistor, wherein during turning on, after the gate voltage of the second mirroring transistor is pulled to being consistent with the first bias voltage, a path between the gate of the first mirroring transistor and the gate of the second mirroring transistor is turned on, and during turning off, after the path between the gate of the first mirroring transistor and the gate of the second mirroring transistor is cut off, the second mirroring transistor is turned off; and a second mirroring transistor, which is controlled by an output signal of the independent control module and performs mirroring amplification on the reference current, so as to obtain an output current. Without the need to use multiple mirror current sources or provide an operational amplifier circuit as a buffer, the present invention allows for low crosstalk between control operations of multiple LED constant-current drive circuits.