A pixel
driving circuit and a driving method thereof, a display panel and a
display device, the pixel
driving circuit being used for driving a light emitting unit (
OLED), the pixel
driving circuit comprising: a driving circuit (1), a compensation circuit (2), a
control circuit (3), and a data writing circuit (4), the driving circuit (1) being connected with a first node (N1), a second node (N2), and a third node (N3), and being used for inputting a
driving current to the third node (N3) through the second node (N2) according to a
voltage signal of the first node (N1); the compensation circuit (2) being connected with the first node (N1), the third node (N3), and a gate driving
signal end (Gate), and being used for connecting the first node (N1) and the third node (N3) in response to a
signal of the gate driving signal end (Gate); the
control circuit (3) being connected with the second node (N2), a first power supply end (VDD), the third node (N3), a first
electrode of the light emitting unit (
OLED), and a first enable signal end (EM1), and being used for connecting the first power supply end (VDD) and the second node (N2) in response to a signal of the first enable signal end (EM1), and being used for connecting the third node (N3) and the first
electrode of the light emitting unit (
OLED) in response to the signal of the first enable signal end (EM1); and the data writing circuit (4) being connected with the second node (N2), a
data signal end (Da), and a second enable signal end (EM2), and being used for transmitting a signal of the
data signal end (Da) to the second node (N2) in response to a signal of the second enable signal end (EM2). In at least part of a period in which the gate driving signal end (Gate) outputs an invalid level, the first enable signal end (EM1) alternately outputs a valid level and an invalid level, the second enable signal end (EM2) alternately outputs the valid level and the invalid level, and a valid level period of the second enable signal end (EM2) is located in an invalid level period of the first enable signal end (EM1), and a valid level period of the first enable signal end (EM1) is located in an invalid level period of the second enable signal end (EM2).