The present application provides a junctionless
transistor, comprising a substrate (100), and a
buried oxide layer (110), a core layer (150), and a shell layer (160) sequentially stacked on the substrate (100). The
doping concentration of the shell layer (160) is less than the
doping concentration of the core layer (150), a gate (170) is provided on the shell layer (160), and the dimension of the shell layer (160) in a first direction parallel to the surface of the substrate (100) is greater than the dimension of the gate (170) in the first direction. Compared with a
scenario where the dimension of the shell layer (160) in the first direction is equal to the dimension of the gate (170) in the first direction, in the present application, the dimension of the shell layer (160) in the first direction is increased, so that charge carriers in a channel are less influenced by source-drain electric fields and are controlled almost exclusively by a gate
electric field. During device operation, due to the low
doping concentration or absence of doping in the shell layer (160), the
charge carrier mobility is high, and therefore, the device can have a lower off-state current and a higher on-state current, thereby improving the device performance.