350 results about "Charge carrier" patented technology

An example polishing system, such as an electrochemical mechanical polishing (ECMP) system, includes a polishing pad assembly having a polishing pad. The example polishing system includes a bias source. The example polishing system includes a workpiece carrier operable to bring the semiconductor workpiece into contact with the polishing pad. In some implementations, the polishing pad assembly is operable to provide an electrically conductive path for one or more charge carriers to the bias source.

Performance evaluation and structural optimization methods for a high-power semiconductor laser chip, and a performance evaluation system for a high-power semiconductor laser chip. The performance evaluation method for a high-power semiconductor laser chip comprises: providing a window on an N-side electrode of a chip to be tested (step 1); keeping the chip in an operating state (step 2); allowing a quantum well active region of the chip to generate spontaneous emission, so that the spontaneous emission is imaged outside the chip (step 3); acquiring, by means of a spectrograph, a spectrum of the spontaneous emission outside the chip and obtaining a two-dimensional distribution of a quantum well temperature of the chip in the operating state; and acquiring, by means of a CCD camera, an image of the spontaneous emission imaging outside the chip and obtaining a two-dimensional distribution of charge carriers in the quantum well of the chip in the operating state (step 4). According to the performance evaluation and structural optimization methods for a high-power semiconductor laser chip, the distributions of the temperature and the charge carrier concentration in the quantum well of the chip to be tested in the operating state in which the resolution is freely adjusted can be obtained. Operations of the methods are convenient, and implementation is simple and easy, thereby efficiently improving the accuracy of an evaluation result.

A structure includes a semiconductor substrate. The structure further includes a first oxide structure disposed above the semiconductor substrate and a second oxide structure disposed above the first oxide structure and configured to form a conductive path at an interface between the first oxide structure and the second oxide structure. The structure additionally includes a conducting structure extending from the interface through the second oxide structure. The conducting structure is configured such that in response to a voltage being applied to the conducting structure, a charge carrier is generated below the second oxide structure along the conductive path.

Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.

A moisture electric generating device comprising: a first electrode and a second electrode; and disposed between the first electrode and the second electrode and a functional layer which releases electrical charge carriers; the functional layer includes at least two sub layers; a first sub layer acting as a moisture reservoir to a second sublayer, to provide moisture to the second sublayer; the second sub layer which produces electrical charge carriers as a function of moisture available from the first sub layer.

A self-orienting perforating gun includes an outer housing having a throughbore, a charge carrier positioned in the throughbore of the outer housing, a hub secured directly or indirectly to the outer housing, a bearing secured to each carrier end of the charge carrier wherein the bearing overlies the hub to provide a rotatable relationship between the hub and the charge carrier about a rotational axis within the outer housing, and an eccentric weight coupled to the charge carrier applying an off-axis orienting force to the charge carrier for urging the charge carrier to rotate about the rotational axis toward a predefined orientation relative to the direction of gravity.

The invention relates to a laser arrangement comprising at least two edge-emitting laser ridges, each with an integrated active zone and an output coupling plane. The at least two edge-emitting laser ridges are spatially separated from one another and share a common, and in particular a single-piece, semiconductor layer sequence with a contact region. Each ridge has a contact terminal, particularly on a surface, for supplying charge carriers to the active zone. A support substrate with at least one contact region is electrically coupled and mechanically connected to the contact region of the common semiconductor layer sequence. Furthermore, a heating element is provided, which is applied to a surface consisting of one of the common semiconductor layer sequences and the support substrate, and comprises two contact terminals and a meandering conductor between the two contact terminals.

In embodiments a component includes a semiconductor layer sequence having a p-side semiconductor layer, an n-side semiconductor layer and an active zone located therebetween, wherein the active zone has a multiple quantum well structure including a plurality of quantum barrier layers and quantum well layers, the quantum barrier layers and the quantum well layers being arranged alternately along a vertical direction, wherein the active zone has at least one recess having facets extending obliquely to a main surface of the active zone, the recess being opened towards the p-side semiconductor layer, wherein, at least within the recess, the quantum barrier layers are n-doped and have a non-constant doping profile so that the component is configured to increase transport negatively charged charge carriers, from the n-side semiconductor layer towards the p-side semiconductor layer, based on the non-constant doping profile, and wherein, from the n-side semiconductor layer towards the p-side semiconductor layer, dopant concentrations of the quantum barrier layers gradually increase.

The invention discloses an organic composite electrode material, a preparation method thereof and a photo-assisted charging ammonium ion battery. The organic composite electrode material is obtained by compounding 2, 6-di [1-(pyrene-3, 4, 9, 10-tetraformyl diimine)] anthraquinone and reduced graphene oxide, and the organic composite electrode material is prepared by compounding the 2, 6-di [1-(pyrene-3, 4, 9, 10-tetraformyl diimine)] anthraquinone and the reduced graphene oxide. According to the invention, the photo-assisted charging strategy and the aqueous ion battery are combined, the ammonium ions are used as the charge carrier of the aqueous photo-assisted charging battery for the first time by virtue of the rapid dynamic characteristic of the ammonium ions in the aqueous electrolyte, and the advantages of rapid ion transmission of the ammonium ions in the electrolyte are utilized; the problem that the photoelectric reaction rate and the electrochemical oxidation reduction rate in the aqueous photo-assisted rechargeable battery are not matched is solved, collaborative optimization of the photoelectric reaction rate and the electrochemical reaction rate is achieved, the charging and discharging efficiency and the energy utilization rate of the battery are remarkably improved, and a new thought is provided for the next generation of photo-storage integrated battery technology.

The invention provides a high-gain 4H-SiC ultraviolet position sensitive detector and a preparation method thereof, and relates to the technical field of semiconductor photoelectric detection. A high-gain 4H-SiC ultraviolet position sensitive detector is realized through a first n-type 4H-SiC layer, a p-type 4H-SiC layer and a second n-type 4H-SiC layer, namely, an n +-p-n-structure, and a wide bandgap semiconductor material 4H-SiC is used as a device main body for migration of carriers irradiated by light. The material has the outstanding characteristics of large forbidden band width, high critical displacement energy, high thermal conductivity coefficient, good chemical stability and the like. According to the device structure, by introducing an internal gain mechanism, the photoelectric conversion efficiency and the position resolution ratio under the weak light condition are remarkably improved, and the limitations that an existing silicon-based PSD is large in background noise, and performance attenuation or damage is prone to occurring under the extreme environments of high temperature, intense radiation and the like are effectively overcome.

The present application provides a junctionless transistor, comprising a substrate (100), and a buried oxide layer (110), a core layer (150), and a shell layer (160) sequentially stacked on the substrate (100). The doping concentration of the shell layer (160) is less than the doping concentration of the core layer (150), a gate (170) is provided on the shell layer (160), and the dimension of the shell layer (160) in a first direction parallel to the surface of the substrate (100) is greater than the dimension of the gate (170) in the first direction. Compared with a scenario where the dimension of the shell layer (160) in the first direction is equal to the dimension of the gate (170) in the first direction, in the present application, the dimension of the shell layer (160) in the first direction is increased, so that charge carriers in a channel are less influenced by source-drain electric fields and are controlled almost exclusively by a gate electric field. During device operation, due to the low doping concentration or absence of doping in the shell layer (160), the charge carrier mobility is high, and therefore, the device can have a lower off-state current and a higher on-state current, thereby improving the device performance.

A perforating gun is disclosed with shaped charges at a preferential orientation. An example includes a gun body and a charge carrier disposed within the gun body. The charge carrier defines a longitudinal carrier axis and has a plurality of axially-spaced charge mounting locations. A plurality of charges are each pivotally mounted to the charge carrier at one of the respective charge mounting locations about a charge pivot axis transverse to the longitudinal carrier axis. The charges may preferentially align in response to gravity so their orientation remains constant throughout a range of inclination of the wellbore.

A method for manufacturing a semiconductor structure includes: depositing atomic layers of tin monoxide along a vertical direction; patterning the atomic layers of tin monoxide into a channel unit; forming a first conducting oxide unit that is connected to the channel unit; forming a second conducting oxide unit that is connected to the channel unit and that is spaced apart from the first conducting oxide unit so as to permit charge carriers to be transmitted between the first conducting oxide unit and the second conducting oxide unit through the patterned atomic layers in the channel unit along the vertical direction; forming a gate dielectric over the channel unit, the first and second conducting oxide units; forming a metal gate over the gate dielectric; recessing the metal gate to expose the gate dielectric; and partially removing the gate dielectric to expose at least the first conducting oxide unit.

A kind of lead-free perovskite hemispherical photodetector, preparation method and its application in single-pixel lensless color imaging belong to the field of image processing technology.The detector is composed of chromium electrode layer, electron transport layer, perovskite layer, hole transport layer and metal electrode layer from inside to outside on the spherical surface of hemispherical transparent substrate.The perovskite obtained by the application has strong lead-free and excellent stability, outstanding charge carrier transport capacity, high collection efficiency and strong weak light sensing ability.The application uses perovskite for color imaging, directly converts optical signal into electrical signal, has high sensitivity, shows excellent performance with linear dynamic response range of 146dB, and has the advantages of uniform response capacity and uniform thickness.The halide perovskite used by the application has low cost, short preparation time, does not contain toxic element lead, improves the application range of perovskite detector, and reduces the manufacturing cost and time cost of perovskite detector.

This disclosure provides a stress-improving light-emitting diode and its fabrication method, belonging to the field of semiconductor technology. The fabrication method includes: sequentially forming a buffer layer and a filler layer on a substrate; alternately performing multiple cooling growth stages and multiple heating growth stages to form a first insertion layer on the filler layer, wherein, during the cooling growth stage, a first sub-layer is formed at a first temperature, which is lower than the growth temperature of the filler layer; during the heating growth stage, a second sub-layer is formed at a second temperature, which is higher than the first temperature; and sequentially forming a first semiconductor layer, a light-emitting layer, and a second semiconductor layer on the first insertion layer, where the second temperature is lower than the growth temperature of the first semiconductor layer. This disclosure can improve the radiative recombination efficiency of charge carriers and improve the luminous efficiency of the LED.

The invention belongs to the technical field of detector preparation, and particularly discloses a preparation method of a B-site cation doped perovskite X-ray detector and a product. Comprising the following steps: respectively preparing a bottom-layer precursor solution SL with low doping concentration of B-site cations and a top-layer precursor solution SH with high doping concentration of B-site cations; firstly blade-coating the bottom-layer precursor solution SL on a base, then blade-coating the top-layer precursor solution SH on the surface of the base in a laminated manner to form a wet mold with a B-site cation longitudinal concentration gradient, and introducing a 2D organic cation solution into the surface of the wet mold to perform an in-situ reaction so as to construct a 2D / 3D perovskite heterostructure; and carrying out segmented annealing crystallization on the wet mold constructed with the 2D / 3D perovskite heterostructure to obtain a compact gradient doped perovskite thick film, and then preparing a metal electrode on the surface of the gradient doped perovskite thick film. According to the invention, doped ions adjust an energy band structure, the effective quality of carriers is reduced, and the mobility is improved, so that the photo-generated current response and the signal-to-noise ratio are improved.

An electrical device comprising a capacitor for high voltage applications and a method for manufacturing the same are provided. The invention relates to an electrical device (100) comprising a capacitor for high voltage applications and a method for manufacturing the same. In particular, the proposed electrical device (100) comprises a capacitor comprising: - a bottom electrode (110) comprising a semiconductor substrate (111), - a dielectric (120) extending conformally on the bottom electrode (110), - a top electrode (130) on the dielectric (120), wherein the substrate (111) comprises: - a first region (113) of a first doping type extending upwardly from a bottom surface (111-BS) of the substrate to a top surface (111-TS) of the substrate, - a second region (114) of a second doping type having opposite charge carriers compared to the first doping type and extending downwardly from the top surface (111-TS) of the substrate to a given depth (111-D).

This invention discloses an MSM interdigitated wideband ultraviolet photodetector and its fabrication method, belonging to the field of semiconductor technology. The detector includes: a substrate; an AlN nucleation layer on the substrate surface; a heterostructure on the surface of the AlN nucleation layer away from the substrate, wherein the heterostructure includes GaN, GaON, and Ga2O3 layers stacked sequentially from bottom to top; and interdigitated electrodes on the surface of the Ga2O3 layer away from the substrate. This invention introduces a GaON layer between the Ga2O3 and GaN heterojunctions. This GaON layer acts as a lattice buffer layer, effectively releasing the lattice mismatch stress between Ga2O3 and GaN, significantly improving the interface quality of the heterojunction, and enhancing the separation and collection efficiency of charge carriers, thus significantly improving the overall performance of the MSM interdigitated ultraviolet photodetector.

This invention relates to the field of solid-state battery technology, and particularly to a composite solid-state electrolyte material, its preparation method, and its application. The composite solid-state electrolyte material contains a crystalline phase substance with the general chemical formula: B%A a RE b X 1 c D g +C%A d M e X 2 f D h Where A represents charge carriers; RE represents rare earth elements; M represents metallic elements; X represents... 1 X 2 D is a halide anion; A is an anion doping element or group; a RE b X 1 c D g and A d M e X 2 f D h It is a crystalline phase substance; B% is A a RE b X 1 c D g The mass fraction of the composite solid electrolyte material; C% is A d M e X 2 f D h The mass fraction of the composite solid electrolyte material is defined as follows: 0 ≤ a ≤ 3, 0 < b ≤ 1, 0.5 < c ≤ 12, 0 < d ≤ 5, 0 < e ≤ 2, 1 < f ≤ 20, 0 ≤ g ≤ 4, 0 ≤ h ≤ 5; 85 < B + C < 98, 10% < B% ≤ 85%; 10% < C% ≤ 85%, 0.2 ≤ C / B ≤ 10. The composite solid electrolyte material of this invention includes crystalline and amorphous phase components, giving it high ionic conductivity. The use of moisture-resistant non-metallic halide components instead of traditional halides and oxyhalides in the raw materials also provides it with good air stability.

The present invention effectively reduces the reverse recovery loss of a diode region in an RC-IGBT. A semiconductor device 1 comprises an IGBT region 31 and a diode region 32 on a single chip. A trench 6 (first trench) of the IGBT region 31 and a trench 6 (second trench) of the diode region 32 are both wide trenches. The diode region 32 comprises: a first semiconductor layer 20 of a second conductivity type, provided on the top side of the drift layer 2 of a first conductivity type; and a second semiconductor layer 23 of the first conductivity type and a charge carrier discharge layer 26 of the second conductivity type, provided on the back side of the drift layer 2 of the first conductivity type. The second semiconductor layer 23 and the charge carrier discharge layer 26 are arranged alternately.

Optoelectronic semiconductor body (1) comprising a sequence of semiconductor layers (2) with an active region (20) intended for generating radiation, a first barrier region (21) and a second barrier region (22), wherein - the active area (20) is located between the first barrier area (21) and the second barrier area (22); - in the first barrier area (21) at least one load carrier barrier layer (3) is arranged which is tension-stressed; - the active area on a material system Al x In y Ga 1-x-y P is based on 0 ≤ x ≤ 1, 0 ≤ y ≤ 1 and x + y ≤ 1; - the charge carrier barrier layer has an Al content x of 0.52 ≤ x ≤ 0.7; - the first barrier area (21) has at least one further load carrier barrier layer (35) which is tension-stressed; - the first charge carrier barrier layer (3) and the further charge carrier barrier layer (35) are spaced apart by 50 nm and 200 nm inclusive, respectively, wherein the entire semiconductor material between the charge carrier barrier layer (3) and the further charge carrier barrier layer (35) is either unstressed or compressively strained; and - the further charge carrier barrier layer (35) is further away from the active area (20) than the charge carrier barrier layer (3) and has a higher Al content than the charge carrier barrier layer (3).

Described herein are techniques to reduce or remove the impact of secondary path photons and / or charge carriers on storage bins of an integrated device to improve noise performance, and thus, sample analysis. Some embodiments relate to optical rejection techniques such as including an optical barrier positioned to block at least some photons from reaching the storage bins. Some embodiments relate to electrical rejection techniques such as including an electrical barrier configured to block at least some charge carriers from reaching the storage bins along at least one secondary path. Some embodiments relate to an integrated device in which at least one storage bin is shaped and / or positioned relative to the photodetector to facilitate receipt of some charge carriers (e.g., fluorescent emission charge carriers) and / or photons and to impede receipt of other charge carriers (e.g., noise charge carriers) and / or photons.

Device for controlling at least one light-emitting diode (LED1) to generate short light pulses (LP),- with an H-bridge (H) consisting of a first half-bridge (HB1: T1, T2) with a first transistor (T1) and a second transistor (T2) and a second half-bridge (HB2: T2, T3) with a third transistor (T3) and a fourth transistor (T4),- wherein the H-bridge (H) is controlled by a control unit (ST) and- wherein the H-bridge (H) can be operated by the control unit (ST) in pulsed mode (GPB) and in quasi-continuous mode (QDB) and- wherein the first half-bridge (HB1: T1, T2) is supplied with electrical energy from a first positive supply voltage (VCC1) and a first negative supply voltage (GND1) and- wherein the second half-bridge (HB2: T3,T4) is supplied with electrical energy from a second positive supply voltage (VCC2) and a second negative supply voltage (GND2) and- wherein the light-emitting diode (LED1) is connected with its cathode (K) to the output of the first half-bridge (HB1: T1, T2) and- wherein the light-emitting diode (LED1) is connected with its anode (A) to the output of the second half-bridge (HB2: T3, T4) and- wherein the first positive supply voltage (VCC1) and the second positive supply voltage (VCC2) can be equal and- wherein the first negative supply voltage (GND1) and the second negative supply voltage (GND2) can be equal and- wherein the light source, in particular the one or more light-emitting diodes (LED1), represents the load of the H-bridge (H) between the output of the first half-bridge (HB1: T1, T2) and the output of the second half-bridge (HB2: T3, T4) and- wherein the control device (ST) is designed to operate in pulsed mode (GPB) a “PAn” condition,in which a forward voltage in the forward direction of the light-emitting diode (LED1) is applied to the light-emitting diode (LED1) through the H-bridge (H), is not maintained by the H-bridge (H) for longer than a turn-on time (τpp), and- wherein the control device (ST) is designed so that in pulsed operation (GPB) a "PAus" state, in which a reverse voltage against the forward direction of the light-emitting diode (LED1) is applied to the light-emitting diode (LED1) through the H-bridge (H), is not maintained by the H-bridge (H) for longer than a clearing time (τpn), and- wherein the clearing time (τpn) is less than the charge carrier lifetime (τ) in the PN junction of the light-emitting diode (LED1), and- wherein the turn-on time (τpp) is less than the charge carrier lifetime (τ) in the PN junction of the light-emitting diode (LED1).

The invention concerns an optoelectronic device comprising a hole injection channel with inclined sidewalls extending through the active layer and an underlying first n-doped layer, such that charge carriers from a second p-doped layer arranged above the active layer are injected both vertically and laterally into the underlying active layer. Improved mobility of holes and a resultant higher rate of recombination results in improved quantum efficiency. The dimensions and location of the hole injection channel are controllable, allowing greater uniformity of performance. A method of manufacturing such an optoelectronic device based on an epitaxial lateral overgrowth process and an optoelectronic arrangement comprising such optoelectronic devices are also disclosed.

Transistors with metal oxide channel material that is in-situ doped for desired charge carrier concentrations. The metal oxide channel material may be deposited by atomic layering of multiple constituent metals with an oxidation of each layer. Such an ALD process may be performed by cyclically depositing a precursor of one of the metals upon a substrate during a deposition phase, and oxidizing the absorbed precursor during an oxidation phase. For a quinary metal oxide, each of three metal precursors may be introduced and oxidized during the ALD process, and charge carrier concentrations may be modulated by further introducing a fourth metal precursor during the ALD process in a manner that disperses this dopant metal within the film at a significantly lower chemical concentration than the other metals.

In one aspect, a field-effect transistor device includes: a semiconductor layer of a wide-bandgap semiconductor layer, the semiconductor layer comprising a source region, a drain region and a floating body region between the source region and the drain region; a first gate and a second gate arranged along the floating body region of the semiconductor layer, wherein the first gate is arranged at a first side of the semiconductor layer and the second gate is arranged at a second side of the semiconductor layer, opposite the first side; and a charge storage island arranged along the floating body region in contact with the second side of the semiconductor layer such that the charge storage island is arranged between the floating body region and the second gate. The charge storage island is configured to define a potential well for charge carriers attracted from a channel.

This invention provides a bidirectional transient voltage suppressor with low dynamic resistance and high surge capability, comprising: a heavily doped semiconductor substrate of a first conductivity type; a first epitaxial layer disposed on the substrate; a conduction modulation buried layer disposed on the first epitaxial layer; a second epitaxial layer disposed on the conduction modulation buried layer; a heavily doped first conductivity type region disposed on the second epitaxial layer; a first electrode disposed on the front side of the heavily doped first conductivity type region and a second electrode disposed on the back side of the substrate; the conduction modulation buried layer is disposed inside the double epitaxial body region and is configured to form a high-concentration conductivity modulation region of charge carriers under transient high current impact conditions, forming a body region-dominated conduction path between the first epitaxial layer and the second epitaxial layer, so that the conduction current changes from concentrated conduction in the PN junction region to a laterally extended and planar distributed overall conduction mode within the body region, thereby reducing the dynamic resistance of the device and improving the surge carrying capacity of the device.

The invention discloses a passivation solution and application thereof, a passivation layer and a preparation method and application thereof, and a perovskite solar cell, and relates to the technical field of perovskite solar devices, the passivation solution is used for passivating a perovskite light absorption layer of the perovskite solar cell, and comprises acetylsalicylic acid; acetylsalicylic acid is adopted as the main component of the passivation solution to passivate the perovskite light absorption layer of the perovskite solar cell, carboxyl and ester groups in the molecular structure of acetylsalicylic acid both have lone pair electrons, and have strong coordination with uncoordinated Pb < + > defects on the surface of the perovskite light absorption layer, so that the deep energy level defects are effectively passivated, and the perovskite light absorption layer of the perovskite solar cell is passivated. And non-radiative recombination of current carriers is reduced. A benzene ring structure in acetylsalicylic acid molecules forms a compact and hydrophobic protective layer on the surface of the perovskite light absorption layer through pi-pi interaction, and erosion of moisture and oxygen in a solvent and an external environment in the subsequent processing process is effectively blocked, so that the environmental stability of the perovskite solar device is remarkably improved.

A near-infrared radiation detector comprises: a substrate comprising a semiconductor; a substrate electrode formed in contact with the substrate; an active layer formed over the substrate, the active layer comprising a ferroelectric material; and an active layer electrode formed in contact with the active layer and substantially transparent to near-infrared radiation. The detector is operable without applied external bias so that, when near-infrared radiation is incident on the detector, charge carriers are generated by a photovoltaic effect in the substrate / active layer heterojunction and a temperature gradient is generated in the active layer, providing a pyro-phototronic current signal indicative of the near-infrared radiation incident on the detector. Also disclosed is a corresponding method of detecting near-infrared radiation.

A complementary field-effect transistor (CFET) circuit with a direct vertical connector and a method for manufacturing the same are disclosed. In one aspect, a semiconductor structure includes: a first field-effect transistor (FET) of a first charge carrier type, the first field-effect transistor (FET) including a first source / drain (S / D) region (412b) and a second source / drain (S / D) region (412a) and one or more channels (408b), the one or more channels being electrically connected to the first S / D region and the second S / D region through a first gate structure; a second FET of a second charge carrier type, the second FET being disposed above the first FET in the Z direction and including a third S / D region (414b) and a fourth S / D region (414a) and one or more channels (408a), the one or more channels being electrically connected to the third S / D region and the fourth S / D region through a second gate structure; and a vertical connector (420) extending in the Z direction from the top surface of the first S / D region (412b) to the bottom surface of the third S / D region (414b) and electrically coupling the first S / D region to the third S / D region.