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4358 results about "Charge carrier" patented technology

In physics, a charge carrier is a particle or quasiparticle that is free to move, carrying an electric charge, especially the particles that carry electric charges in electrical conductors. Examples are electrons, ions and holes. In a conducting medium, an electric field can exert force on these free particles, causing a net motion of the particles through the medium; this is what constitutes an electric current. In conducting media, particles serve to carry charge...

Method of manufacturing surface textured high-efficiency radiating devices and devices obtained therefrom

A device for emitting radiation at a predetermined wavelength is presented. This device has a cavity with an active layer in which said radiation is generated by charge carrier recombination. The edges of the device define the region or space for radiation and / or charge carrier confinement. At least one of the edges of this cavity has a substantially random grating structure. The edge of the device has substantially random grating structure and can extend as at least one edge of a waveguide forming part of this radiation emitting device. The radiation emitting device of the present invention can have a cavity comprising a radiation confinement space that includes confinement features for the charge carriers confining the charge carriers to a subspace being smaller than the radiation confinement space within the cavity. The emitting device can comprise at least two edges forming, in cross-section, a substantially triangular shape. The angle between these two edges is smaller than 45°. At least one of the two edges has a transparent portion. the devices according to the present invention can be arranged in arrays.
Owner:SIGNIFY HLDG BV

Light emitting devices with layered III-V semiconductor structures

A semiconductor light emitting device is disclosed, including a semiconductor substrate, an active region comprising a strained quantum well layer, and a cladding layer for confining carriers and light emissions, wherein the amount of lattice strains in the quantum well layer is in excess of 2% against either the semiconductor substrate or cladding layer and, alternately, the thickness of the quantum well layer is in excess of the critical thickness calculated after Matthews and Blakeslee.
Owner:RICOH KK

Solar cell

The present invention provides a thin film amorphous silicon-crystalline silicon back heterojunction and back surface field device configuration for a heterojunction solar cell. The configuration is attained by the formation of heterojunctions on the back surface of crystalline silicon at low temperatures. Low temperature fabrication allows for the application of low resolution lithography and/or shadow masking processes to produce the structures. The heterojunctions and interface passivation can be formed through a variety of material compositions and deposition processes, including appropriate surface restructing techniques. The configuration achieves separation of optimization requirements for light absorption and carrier generation at the front surface on which the light is incident, and in the bulk, and charge carrier collection at the back of the device. The shadowing losses are eliminated by positioning the electrical contacts at the back thereby removing them from the path of the incident light. Back contacts need optimization only for maximum charge carrier collection without bothering about shading losses. A range of elements/alloys may be used to effect band-bending. All of the above features result in a very high efficiency solar cell. The open circuit voltage of the back heterojunction device is higher than that of an all-crystalline device. The solar cell configurations are equally amenable to crystalline silicon wafer absorber as well as thin silicon layers formed by using a variety of fabrication processes. The configurations can be used for radiovoltaic and electron-voltaic energy conversion devices.
Owner:KHERANI NAZIR P +1

Quantum WELL MOS transistor and methods for making same

PCT No. PCT / FR97 / 01075 Sec. 371 Date Feb. 12, 1998 Sec. 102(e) Date Feb. 12, 1998 PCT Filed Jun. 13, 1997 PCT Pub. No. WO97 / 48135 PCT Pub. Date Dec. 18, 1997A new quantum well MOS transistor is described along with a processes for manufacturing it. In this transistor, the source and drain areas are separated from the channel by sufficiently thin insulating layers to enable the passage of charge carriers by the tunnel effect. Each of the source and drain areas is separated from the substrate by an electrically insulating layer that is sufficiently thick to prevent charge carriers from passing through this insulating layer.
Owner:COMMISSARIAT A LENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
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