553 results about "Charge carrier mobility" patented technology

The invention provides a power management chip high-low side driving signal time sequence optimization method and system. The method comprises the following steps: acquiring temperature data of a power management chip under a switch switching transient working condition through an infrared thermal imaging technology, and synchronously acquiring three-dimensional temperature field distribution of junction temperatures on the surface and inside a packaging layer; based on the space continuity of a temperature field, extracting the temperature change characteristics of a power device area, converting the temperature gradient into Seebeck voltage by using a thermoelectric material embedded in a hot spot area, and constructing a dynamic thermoelectric feedback network; according to Seebeck voltage data, a coupling relation between hot carrier concentration and driving signal phase deviation is established, and disturbance of hot carrier mobility change on MOSFET switching delay is quantified; the rising / falling edge slope of the grid voltage is adjusted based on the coupling relation, the phase deviation caused by the hot carrier effect is eliminated through dynamic compensation, and the switching performance is optimized. The dynamic response precision of the power management chip is improved.

The invention discloses an organic electroluminescent compound and a luminescent device. The organic electroluminescent compound has a structure as shown in a formula (1). In the structure of the N-type compound provided by the invention, an electron-rich group formed by carbazole and phenyl connected with the carbazole is substituted by deuterium, and the deuterated P-type compound in the core region is matched, so that the chemical stability, photoelectric stability and thermal stability of the structure of the luminescent material can be effectively improved, the stability of a luminescent device using the material is further improved, and the service life of the luminescent device is prolonged; meanwhile, the N-type compound and the deuterated P-type compound in the core area can form a good Premix material, good P / N stability and mass production stability are achieved in the evaporation process, the formed Premix material has more balanced carrier mobility, the efficiency of a device is greatly improved, and the service life of the device is greatly prolonged. And # imgabs0 #.

The invention provides an endangered animal monitoring method based on a multi-mode floating gate type photoelectric synapse transistor, realizes multi-mode fusion of images (optical signals) and sounds (electric signals) by utilizing the light absorption capability of quantum dots and the high carrier mobility of a two-dimensional channel material, and belongs to the technical field of sensing, storage and calculation integration and endangered animal identification and monitoring. According to the method, a photoelectric synapse device is used as a reservoir, and input time sequence signals are respectively applied to a multi-mode fused photoelectric synapse transistor in the form of light and electric pulse. And along with the co-stimulation of light and electric pulse, the change response of source-drain current is generated, and the fusion processing of the multi-mode signal is realized. By adopting the method, a human multi-sensory fusion signal processing mode is successfully simulated, and accurate recognition under complex and changeable conditions can be realized by utilizing a mode of complementation of visual signals and auditory signals. Under an extreme environment or a high noise condition, edge processing and identification can be carried out on pictures and sounds of endangered animals, and a high-accuracy monitoring result can be obtained without a large amount of data return, so that the energy consumption is reduced and the monitoring efficiency is enhanced.

The invention discloses a doped material based on a hexagonal boron nitride / titanium dioxide heterojunction and a preparation method thereof. According to the material, a heterojunction is formed by hexagonal boron nitride and titanium dioxide, and the light absorption performance, the carrier mobility and the photocatalytic efficiency are optimized by doping a nitrogen element, an iron element and a fluorine element; wherein the doped nitrogen element can reduce a band gap by introducing a defect energy level, and broaden a light absorption range to a visible light region and an infrared light region; the doped iron element can promote carrier separation by introducing an intermediate energy level; the doped fluorine element can inhibit carrier recombination by reducing surface defects. The light absorption efficiency of the material in the ultraviolet light range can be improved by constructing the layered # imgabs0 # heterojunction composite material, and the migration rate of electrons and holes can be improved by doping the N element, the Fe element and the F element in the # imgabs1 #, so that the oxidation-reduction reaction is promoted, and reference significance is provided for further improving the application effect of a photocatalyst in sewage treatment.

The invention relates to the technical field of ITO coating materials, and provides a low-sheet-resistance and high-light-transmittance ITO coating film and a preparation method thereof.The preparation method comprises the steps that S1, an yttrium-doped zirconium oxide substrate is prepared; s2, performing surface activation on the yttrium-doped zirconium oxide substrate; s3, performing magnetron sputtering in a radio frequency magnetron sputtering chamber, and forming a layer of ITO film on the surface of the yttrium-doped zirconia substrate; and S4, annealing treatment and gradient cooling treatment are carried out. The epitaxial growth of the ITO coating film is optimized through the prepared yttrium-doped zirconia substrate, and the magnetron sputtering, annealing and gradient cooling processes are combined, so that the microstructure of the film is optimized, the carrier mobility and the uniformity and stability of the film are improved, the grain boundary defect and carrier scattering loss in the ITO coating film are reduced, and the performance of the film is improved. The low sheet resistance and high light transmittance of the ITO coating film are synergistically improved, and the obtained ITO coating film has important application value in the fields of high-performance optoelectronic devices, transparent conductive films and the like.

The invention relates to the field of crystal detection, and discloses a multifunctional comprehensive scintillation crystal and semiconductor material energy spectrum test system, which comprises a crystal adaptation module for judging the type and size of a placed crystal through an optical identification and parameter matching mechanism, and a signal acquisition module for amplifying, filtering and digitally processing an acquired signal, the signal correction module is used for correcting waveform distortion and baseline drift through a dynamic gain adjustment algorithm of a low-noise pre-amplifier and a multi-channel pulse analyzer; the data analysis module is used for generating an energy spectrum curve according to input signals and calculating energy resolution, counting rate, light attenuation time or carrier mobility, and the environment calibration module is used for dynamically evaluating shading degree, environment light, temperature and electromagnetic interference through an optical sensor and a temperature and humidity detector in the camera obscura and outputting updated calibration parameters. The method has the advantages of improving the detection efficiency, precision and consistency.

The invention discloses a method for measuring the intrinsic carrier mobility of a semiconductor material, and relates to the technical field of semiconductor material performance measurement. The method comprises the following steps: establishing a measurement system for the intrinsic carrier mobility of the semiconductor material; using an optical delay line to continuously change the relative time delay between the probe light and the pump light, obtaining the light intensity of the probe light under the action of the pump light and without the action of the pump light, testing to obtain a transient reflection dynamic spectrum of the semiconductor material, and extracting to obtain a Brillouin oscillation signal; calculating an electron deformation potential, a hole deformation potential and a semiconductor material elastic modulus based on the Brillouin oscillation signal; and calculating the intrinsic carrier (electron and hole) mobility of the semiconductor material based on the electron deformation potential, the hole deformation potential and the elastic modulus of the semiconductor material. Aiming at the lack of a method for experimentally measuring the intrinsic carrier mobility of a material at present, the measurement method disclosed by the invention fills the blank in the field.

The invention discloses a P-type tellurium oxide thin film field effect transistor and a preparation method thereof. The transistor is provided with a bottom gate top contact structure. The preparation method comprises the following steps: firstly, cleaning the silicon / silicon dioxide substrate, then depositing a tellurium oxide film as the semiconductor active layer by using a metal mask and an electron beam evaporation method, and finally preparing a layer of nickel with the thickness of about 50nm on the active layer by using the mask to serve as the source electrode and the drain electrode. Compared with a traditional tellurium oxide transistor, the tellurium oxide transistor prepared by the method has the advantages that the carrier mobility and the switching ratio are obviously improved, and the hysteresis effect can be ignored. The electrical performance of the tellurium oxide transistor with the bottom gate top contact structure is improved, and the tellurium oxide transistor has the advantages of being low in cost and simple in process step.

A display panel and a manufacturing method therefor, and a display apparatus. The display panel comprises a base substrate, a pixel define layer located on the base substrate, and a light-emitting functional layer located on the side of the pixel define layer away from the base substrate. The pixel define layer comprises a defining portion for defining a pixel opening. The light-emitting functional layer comprises carrier layers, wherein the carrier layers are consecutive and cover the pixel define layer. Each carrier layer comprises a first area and a second area except the first area, wherein the orthographic projection of the first area on a first surface of the base substrate is located in the orthographic projection of the defining portion on the first surface of the base substrate, and the carrier mobility of the first area is smaller than the carrier mobility of the second area. The present application can prevent a crosstalk current from being formed between adjacent sub-pixels of the display panel.

The invention belongs to the technical field of organic electroluminescent materials, and provides an iridium-containing heterocyclic phosphorescent doping material and an organic electroluminescent device.The doping material has a compound general formula shown in the formula I. Quinoline and a naphthalene ring are connected through silane or germane, and a silicon or germanium six-membered heterocyclic structure is formed. And reacting with iridium metal and a diketone monomer to obtain the iridium metal heterocyclic phosphorescent organic light-emitting material. The heteroatom silicon or germanium in the material can adjust molecular orbital HOMO and LUMO energy levels, and the polarity effect of heteroatoms promotes electron migration, reduces interface potential barriers and electron injection barriers, reduces carrier injection loss and improves carrier mobility, so that driving voltage is reduced, and the external quantum efficiency of a device is improved. In addition, the silicon or germanium heterocyclic ring has better rigidity, so that the overall stability of the structure is enhanced, and the rigid structure can prolong the service life of the device.

The invention provides a junction-free transistor, which comprises a substrate, and a buried oxide layer, a core layer and a shell layer which are sequentially stacked on the substrate, the doping concentration of the shell layer is smaller than that of the core layer, the shell layer is provided with a grid electrode, and the size of the shell layer in a first direction along the surface of the substrate is larger than that of the grid electrode in the first direction, that is, the size of the shell layer in the first direction is smaller than that of the grid electrode. Compared with the condition that the size of the shell layer in the first direction is equal to the size of the grid electrode in the first direction, the size of the shell layer in the first direction is increased in the scheme, so that carriers in a channel are less acted by a source leakage field and are almost only controlled by a grid electrode electric field, and when the device starts, due to the fact that the doping concentration of the shell layer is low or the shell layer is not doped, the performance of the device is improved. Therefore, the carrier mobility is high, the device can have lower off-state current and higher on-state current, and the performance of the device is improved.

Disclosed is a thin-film transistor substrate in which carrier mobilities of active layers of a first thin-film transistor and a second thin-film transistor which require different characteristics are set to be different from each other, thereby satisfying both the different characteristics required for the first and second thin-film transistors having different functions. Further, a display device including the thin-film transistor substrate is disclosed.

The invention relates to a compensation polarization doped aluminum nitride Schottky diode and a manufacturing method thereof. The compensation polarization doped aluminum nitride Schottky diode comprises a substrate, an unintentionally doped AlN layer, a Si doped AlN layer and a Si compensation doped Al component slowly-decreasing layer from bottom to top. The surface of the Si-doped AlN layer is in Schottky contact with the anode of the diode; the Si compensation doped Al component slowly-decreasing layer is from AlN to Al < x > Ga < 1-x > N from bottom to top, the value range of x is 0-0.3, and ohmic contact is formed between the Si compensation doped Al component slowly-decreasing layer and the cathode of the diode. According to the aluminum nitride Schottky diode, through compensation polarization doping, the metal contact performance is improved, the problems that the material surface is rough and the carrier mobility is low due to impurity doping are solved, and the Schottky diode with the high potential barrier and the low ideal factor is achieved.

The invention relates to the technical field of kits, in particular to a MoS2 back gate field effect transistor based on a wet transfer process and a preparation method of the MoS2 back gate field effect transistor. The MoS2 back gate field effect transistor is formed by sequentially arranging a silicon-based substrate, a SiO2 insulating layer, a MoS2 conducting channel layer and an Ag source drain electrode from bottom to top; a high-quality single-layer MoS2 thin film is prepared through a chemical vapor deposition (CVD) method, PMMA is adopted as a supporting layer, clean Van der Waals contact of the MoS2 thin film and a SiO2 / Si substrate is achieved through a wet transfer process of NaOH solution etching, deionized water cleaning and acetone stripping of the supporting layer, and finally a source electrode and a drain electrode are prepared by combining photoetching and thermal evaporation processes. According to the method, the problems of pollutant residues and traps of an interface between MoS2 and the substrate in the traditional process are effectively solved, the carrier mobility, transconductance and on-state current of the device are remarkably improved, the sub-threshold swing is reduced, and the method is suitable for manufacturing a two-dimensional material integrated circuit device with low power consumption and high performance.

The invention relates to a field effect transistor and a preparation method thereof, and the field effect transistor comprises an insulating substrate, a two-dimensional material Bi2O2Se channel layer which grows on the insulating substrate in situ, a first electrode and a second electrode which are arranged on the two-dimensional material Bi2O2Se channel layer, a two-dimensional material MoO3 layer which is arranged on the two-dimensional material Bi2O2Se channel layer, and a third electrode which is arranged on the two-dimensional material MoO3 layer, the two-dimensional material MoO3 layer completely covers the two-dimensional material Bi2O2Se channel layer; the width of a depletion region of the Bi2O2Se channel layer is controlled through voltage applied to the MoO3 layer, so that the switching function of the transistor is achieved, a good sub-threshold characteristic is obtained, meanwhile, due to the high carrier mobility characteristic of the two-dimensional Bi2O2Se material, a remarkable electrical response can be obtained only by applying small source and drain voltage, and the performance of the transistor is improved. And excellent sub-threshold characteristics and conduction current performance are presented.

The present application provides a junctionless transistor, comprising a substrate (100), and a buried oxide layer (110), a core layer (150), and a shell layer (160) sequentially stacked on the substrate (100). The doping concentration of the shell layer (160) is less than the doping concentration of the core layer (150), a gate (170) is provided on the shell layer (160), and the dimension of the shell layer (160) in a first direction parallel to the surface of the substrate (100) is greater than the dimension of the gate (170) in the first direction. Compared with a scenario where the dimension of the shell layer (160) in the first direction is equal to the dimension of the gate (170) in the first direction, in the present application, the dimension of the shell layer (160) in the first direction is increased, so that charge carriers in a channel are less influenced by source-drain electric fields and are controlled almost exclusively by a gate electric field. During device operation, due to the low doping concentration or absence of doping in the shell layer (160), the charge carrier mobility is high, and therefore, the device can have a lower off-state current and a higher on-state current, thereby improving the device performance.

The invention discloses a preparation method of a thin film transistor. The core of the preparation method is to construct a quasi-double-channel structure. Taking an insulating layer of the thin film transistor as a first metal oxide, and processing the surface of the insulating layer to obtain an oxygen-deficient surface; depositing a second metal oxide on the anoxic surface as a channel layer; a metal-oxygen bond of the insulating layer is higher than a metal-oxygen bond of the channel layer; and after the deposition of the second metal oxide is finished, a two-dimensional oxygen-deficient surface is spontaneously formed on the contact surface of the insulating layer and the channel layer through annealing treatment, so that the thin film transistor with the quasi-double-channel structure is obtained. Compared with a traditional thin film transistor, the thin film transistor has the advantages that the positive bias voltage stability and the negative bias voltage stability are obviously improved, and meanwhile, the mobility is greatly improved. The invention has the characteristics of high carrier mobility, small threshold voltage drift and high long-term working reliability, and is simple in preparation process and low in cost. The quasi-double-channel structure is expected to be widely applied to oxide thin film transistors.

The utility model discloses a quantum dot light emitting diode, a display substrate and a display device. The quantum dot light-emitting diode comprises a first electrode, a second electrode, and a quantum dot light-emitting layer, a first electron transport layer and a second electron transport layer which are arranged between the first electrode and the second electrode, wherein the first electron transport layer and the second electron transport layer are sequentially arranged on one side, close to the second electrode, of the quantum dot light-emitting layer; wherein the first electron transport layer and the second electron transport layer are made of inorganic nanoparticles, the conduction band bottom energy level of the first electron transport layer is matched with the conduction band bottom energy level of the quantum dot light-emitting layer, and the conduction band bottom energy level of the second electron transport layer is larger than the work function of the second electrode and smaller than the conduction band bottom energy level of the first electron transport layer; the carrier mobility of the second electron transport layer is greater than that of the first electron transport layer, and the second electron transport layer is configured to adjust the length of the optical microcavity between the first electrode and the second electrode.

According to the composition for the organic optoelectronic device and the organic optoelectronic device provided by the invention, a ternary GH system mode is adopted, i.e., a double P-type material is matched with a single N-type material to form a main body material, so that the injection of current carriers is improved, and meanwhile, the material is ensured to have relatively high current carrier mobility; and the efficiency and the service life of the device are improved.

A transistor structure may be formed in an interconnect layer (e.g., a backend region) of a semiconductor device. The transistor structure is formed such that an interfacial layer is included between a gate dielectric layer and an oxide-semiconductor channel layer of the transistor structure. The interfacial layer provides a substrate on which the oxide-semiconductor channel layer may be formed to have a particular crystal lattice structure to achieve greater charge carrier mobility in the oxide-semiconductor channel layer than without the interfacial layer. Additionally and / or alternatively, the interfacial layer may prevent or reduce the likelihood of contamination from oxygen (O2) and / or hydrogen (H2) from the gate dielectric layer and other layers surrounding the transistor structure.

The invention discloses a stacked display unit and a display. The unit comprises a sapphire substrate, a light-emitting chip arrangement layer and a unit driving chip, wherein the light-emitting chip arrangement layer and the unit driving chip are vertically stacked on the sapphire substrate. The light-emitting chip arrangement layer comprises Micro-LED chips generating red light, green light and blue light, first insulation packaging layers are filled among the chips, and signal pads and common pads are arranged for electrode connection. The unit driving chip is arranged on the first insulation packaging layer, and a driving pin of the unit driving chip is electrically connected with the signal pad and the common pad. The second insulating packaging layer covers the signal pads and the common pads, but exposes the unit driving chips, and is provided with contact pads which are connected with data and power supply pins of the driving chips. According to the design, the occupation of the horizontal space of the display unit is reduced, the resolution ratio is improved, active driving is realized, and the loss of the luminous efficiency of the Micro-LED chip is avoided. Wherein the unit driving chip can be a silicon substrate, and due to the fact that the carrier mobility of the unit driving chip is higher, large-current driving is supported, and the display performance of the Micro-LED can be better exerted.

The invention discloses a rare bismuth II type superlattice material and a preparation method thereof. The superlattice material has an InAs (Bi) / GaSb or InAs (Bi) / InAsSb superlattice structure formed by alternately laminating InAs (Bi) layers and GaSb layers or InAsSb layers, and the InAs (Bi) layers are formed by introducing Bi elements into the InAs layers. The preparation method of the superlattice material comprises the following steps: (1) selecting an InSb, InAs or GaSb substrate, performing thermal cleaning on the substrate at 500 DEG C, and cleaning the substrate by using atomic hydrogen in an ultrahigh vacuum environment; (2) alternately laminating InAs (Bi) layers and GaSb layers or InAsSb layers by utilizing a molecular beam epitaxial growth technology, and finally growing a GaSb layer or InAsSb layer as a stop layer, (3) carrying out rapid thermal annealing treatment at the temperature of 380-420 DEG C; the time is 0.5 to 1 min; and (4) characterizing the photoluminescence property of the superlattice. According to the invention, the strain distribution and the energy band structure of the material are obviously improved, the more flexible wavelength regulation and control capability is realized, the hole effective quality is reduced, and the carrier mobility and the quantum efficiency are improved.

The invention discloses a high-speed photoelectric detector based on a mixed surface plasma slit waveguide and a preparation method of the high-speed photoelectric detector, and belongs to the technical field of integrated optoelectronic devices. Comprising a substrate, a mixed surface plasma slit waveguide, metal gates on the two sides, a Van der Waals heterostructure and metal source and drain electrodes on the two sides. The Van der Waals heterojunction is composed of an upper hexagonal boron nitride layer, a lower hexagonal boron nitride layer and a middle two-dimensional material. According to the invention, the hexagonal boron nitride is used for packaging the two-dimensional material, so that the carrier mobility of the two-dimensional material can be improved, and the photoelectric response of the detector is enhanced; according to the invention, the distance between the metal gate and the optical waveguide is shortened, a transverse electric mode transmitted in the waveguide is regulated and controlled, a hybrid surface plasma slit mode with a strong local area is formed, the interaction between an optical field and a two-dimensional material layer is enhanced, and the responsivity of the detector is remarkably improved; the Fermi level of the two-dimensional material can be dynamically regulated and controlled by introducing the grid bias voltage, the photo-generated current separation efficiency is enhanced, and the responsivity and the signal-to-noise ratio of the detector can be improved.

A thin-film transistor and an array substrate are provided. The thin-film transistor includes a substrate and an active layer on the substrate. The active layer includes multiple layers of oxides arranged in a stacked manner; the multiple layers of oxides include a channel layer, a transition layer, and a first barrier layer; the channel layer is a layer having the maximum carrier mobility in the multiple layers of oxides; the channel layer is a crystalline oxide layer or an amorphous oxide layer; the transition layer is in direct contact with the channel layer; the first barrier layer is the outermost oxide layer among the multiple layers of oxide; the first barrier layer and the transition layer are both crystalline oxide layers; the band gap of the first barrier layer and the band gap of the transition layer are both greater than the band gap of the channel layer.

The present application provides a display panel and a display device. The display panel includes a plurality of pixel units, each pixel unit includes a plurality of sub-pixels, and the plurality of sub-pixels are divided into a first type of sub-pixels and a second type of sub-pixels. The brightness life of the first type of sub-pixels is shorter than the brightness life of the second type of sub-pixels. Each sub-pixel includes a cathode, an anode, and a light-emitting layer and a carrier transport layer located between the cathode and the anode. In addition, the carrier mobility of the carrier transport layer of the first type of sub-pixel is different from the carrier mobility of the carrier transport layer of the second type of sub-pixel. By adjusting the carrier mobility, the brightness difference between sub-pixels of different types can be reduced, and the problem of display color cast can be improved.

This invention relates to the field of display technology, specifically to an organic electroluminescent compound and its applications. An organic electroluminescent compound has the structure shown in formula (1). Based on the structure of formula (1), further limiting the types of substituents can improve the structural stability of the compound. Furthermore, the HOMO and LUMO energy levels of the organic electroluminescent compound have a high degree of matching with adjacent energy levels, resulting in a more balanced carrier mobility. Consequently, organic electroluminescent devices containing this organic electroluminescent compound exhibit lower driving voltage, higher luminous efficiency, and longer lifetime.

The application provides a power management chip high-low side driving signal timing optimization method and system. Wherein, the method collects temperature data of the power management chip under switching transient working condition by infrared thermal imaging technology, synchronously obtains three-dimensional temperature field distribution of the surface and internal junction temperature of the packaging layer; based on the spatial continuity of the temperature field, the temperature variation characteristics of the power device area are extracted, and the temperature gradient is converted into the Seebeck voltage by using the thermoelectric material embedded in the hot spot area to construct a dynamic thermoelectric feedback network; the coupling relationship between the hot carrier concentration and the driving signal phase shift is established according to the Seebeck voltage data, the disturbance of the hot carrier mobility change on the MOSFET switching delay is quantified; based on the coupling relationship, the rising / falling edge slope of the gate voltage is adjusted, the phase deviation caused by the hot carrier effect is eliminated through dynamic compensation, and the switching performance is optimized. The application improves the dynamic response accuracy of the power management chip.

Various embodiments of the present application are directed towards a group III-V device including a rough buffer layer. The rough buffer layer overlies a silicon substrate, a buffer structure overlies the rough buffer layer, and a heterojunction structure overlies the buffer structure. The buffer structure causes band bending and formation of a two-dimensional hole gas (2DHG) in the rough buffer layer. The rough buffer layer includes silicon or some other suitable semiconductor material and, in some embodiments, is doped. A top surface of the rough buffer layer and / or a bottom surface of the rough buffer layer is / are rough to promote carrier scattering along the top and bottom surfaces. The carrier scattering reduces carrier mobility and increases resistance at the 2DHG. The increased resistance increases an overall resistance of the silicon substrate, which reduces substrate loses and increases a power added efficiency (PAE).

A field effect transistor and a manufacturing method thereof, wherein the field effect transistor comprises: a source (13), a drain (14) and a gate (12); a channel region (11) is provided between the source (13) and the drain (14); an inner isolation layer (110) is provided between the gate (12) and the source (13) and between the gate (12) and the drain (14); the inner isolation layer (110) covers a portion of the channel region (11), wherein the inner isolation layer (110) includes donor impurities or acceptor impurities. The structure can reduce the on-resistance of the channel region (11) of the field effect transistor and maintain high carrier mobility in the channel region (11), thereby improving the performance of the field effect transistor.

According to the semiconductor device, the manufacturing method of the semiconductor device and the electronic device provided by the invention, two semiconductor layers with different carrier mobility are arranged, the semiconductor layer with low carrier mobility covers the semiconductor layer with high carrier mobility, and the semiconductor layer with high carrier mobility is located in the coverage range of the first electrode, so that the reliability of the semiconductor device is improved. Therefore, when ion implantation is carried out on the semiconductor layer to form the source contact region and the drain contact region, the implanted ions are mainly concentrated in a region with low carrier mobility, so that the ion diffusion distance can be reduced, and the effective channel length of the semiconductor device is ensured.