26results about How to "Increase drive current" patented technology

The invention relates to a redundant feedback latch multilevel anti-single-particle reinforced trigger of a FinFET (FinFET) process, which comprises a data input structure, a clock input structure, four clock control structures, a delay structure, a data master latch structure, a data slave latch structure and a data output structure, the trigger latches data for both the data master latch structure and the data slave latch structure by using a redundancy feedback circuit, and delays one path of data by using a delay structure to filter external single-particle transient pulses at a data end; through a redundancy feedback latch structure and a delay unit, the circuit realizes multi-dimensional reinforcement of single-particle unit / multi-bit upset and single-particle transient, and the single-particle radiation reinforcement resistance of the trigger is significantly improved. In addition, a design reinforcing method combining a circuit and a layout is preferably adopted, the number of Fins in unit grid spacing is designed to be the maximum, an interdigital structure is used for devices at sensitive nodes, meanwhile, the sensitive nodes are arranged in an isolated mode, and the single-particle multi-bit upset resisting capacity is further enhanced.

The invention relates to an input voltage power failure locking and startup and shutdown instruction control circuit and a working method thereof. The circuit comprises a short circuit protection unit, a surge suppression unit, an EMI filtering unit, a DC / DC conversion unit, an output filtering unit and a control circuit unit. The control circuit unit comprises an input bus power failure locking unit, a shutdown control instruction unit, a startup control instruction unit and a startup and shutdown state locking unit. The method is suitable for a power supply and distribution system in aerospace electronic equipment, and can be widely applied to other various power supply and distribution systems which work reliably for a long time. According to the method, the reliability of pulse instruction control on and off of the power supply and distribution system in the electronic equipment for space navigation can be guaranteed, when the primary input bus voltage breaks down or returns to normal, the power supply can be effectively in the off state, the effective on and off instruction can be retransmitted through the platform, and it is guaranteed that the system is reliably restarted and operated.

The invention relates to a method for forming a semiconductor structure, which comprises the following steps of: providing a substrate which comprises an NMOS (N-channel Metal Oxide Semiconductor) region and a PMOS (P-channel Metal Oxide Semiconductor) region, and respectively arranging a gate layer and a source-drain region formed in the substrate at two sides of the gate layer on the surface of the substrate in the NMOS region and the PMOS region; stress layers are formed on the surface of the substrate and the side wall and the top surface of the gate layer; carrying out stress relief treatment on the stress layer of the PMOS region; carrying out annealing treatment on the stress layer of the NMOS region; patterning the stress layer after the stress relief treatment and the annealing treatment until the top surface of the gate layer and the top surface of the source-drain region are exposed; forming metal silicide on the exposed top surface of the gate layer and the exposed top surface of the source and drain region; therefore, the cost can be saved, the manufacturing time can be shortened, the performance of the formed semiconductor structure is not influenced, and the method has a wide application range.

The invention provides a force feedback sensor ground self-detection circuit and method, and the circuit comprises a power amplifier drive circuit which is used for receiving a ground self-detection excitation signal and driving a torque device to work according to the ground self-detection excitation signal, and a modulation circuit which is used for carrying out the carrier adjustment of a weak output signal of the torque device. The demodulation circuit is used for recovering an original external excitation signal from the modulated output signal; the correction circuit is used for correcting the demodulated output; the gain adjusting circuit is used for carrying out gain adjustment on the corrected output signal and feeding back the corrected output signal to the power amplifier driving circuit; the output stage circuit is used for outputting the signal after gain adjustment; and the sampling circuit is used for adjusting the gain of the closed loop formed by the self-detection circuit. By adopting the circuit, the power supply of the flight control system can be directly controlled, the purpose of ground self-inspection by using a non-isolated power supply is achieved, and the problem of high development cost of a force feedback sensor caused by a traditional self-inspection circuit is solved.

The invention discloses a blood oxygen monitoring method, device and equipment and a computer readable storage medium, is applied to the technical field of blood oxygen monitoring, aims to solve the problem that existing blood oxygen monitoring is low in accuracy, and provides the method applied to the blood oxygen monitoring equipment, and comprises the steps that under the condition that it is detected that a finger is inserted into the blood oxygen monitoring equipment, a blood oxygen signal is collected; determining a signal-to-noise ratio of the pulsation part signal according to the blood oxygen signal; under the condition that the signal-to-noise ratio of the pulsation part signal is lower than a first preset signal-to-noise ratio threshold value, the driving current of a light source located in the blood oxygen monitoring equipment is controlled to be increased; the driving current of the light source is directly adjusted based on the signal-to-noise ratio of the pulsation part signal, so that the signal-to-noise ratio of the pulsation part signal is improved, the adjusting effect is good, the measurement error can be effectively reduced, and the calculation accuracy of the final blood oxygen saturation degree can be improved.

This patent discloses an active driving device using a gate wrapping structure to drive an inorganic light emitting diode display and lighting device and a manufacturing method thereof, which can effectively reduce the area occupied by the active driving circuit and increase the effective display area of ​​the inorganic light emitting diode light emitting device.

The invention provides a thin film transistor and a manufacturing method thereof, an array substrate and a display panel. The manufacturing method of the thin film transistor comprises the steps of providing a substrate; preparing a metal oxide active layer on one side of the substrate; preparing a first insulating layer on one side, far away from the substrate, of the metal oxide active layer; preparing a gate on one side, away from the substrate, of the first insulating layer; and injecting ions at least comprising fluorine elements into the first injection region and the second injection region. The fluorine-containing ions are injected into the first injection region and the second injection region to form the source region and the drain region respectively, and the carrier concentration is improved and the conductor resistance of the source and the drain is reduced by utilizing the strong electronegativity of the fluorine element, so that the on-state driving current of the thin film transistor is improved, and the device performance is improved.

The present application discloses a display module and a display device, wherein the display module includes a light-emitting unit and a driving circuit, wherein the driving circuit includes a controller, a control chip, a detection module and a compensation feedback module, wherein the output end of the control chip includes a plurality of output channels, each of which is connected in series with a row of lamp beads, wherein the detection module is connected to the plurality of output channels, receives the driving current output by the controller, and detects whether the lamp beads in the light-emitting unit are abnormal; wherein the compensation feedback module is connected to the detection module and the controller, and when the detection module detects an abnormal lamp bead, the compensation feedback module notifies the controller to turn off or reduce the driving current of the output channel corresponding to the abnormal lamp bead, and at the same time increases the driving current of the output channel corresponding to the row of lamp beads adjacent to the abnormal lamp bead. Through the above design, the display problem of dark spots or dark lines that occurs when the LED is abnormal can be improved.

The application discloses a TBC battery and a preparation method thereof. The TBC battery comprises a substrate and a P-zone assembly arranged on the back of the substrate. The P-zone assembly comprises a first electrode, a first tunneling silicon oxide layer, a boron-doped polysilicon layer and a first passivation layer which are sequentially stacked on the back of the substrate. The first electrode penetrates through the first passivation layer and the boron-doped polysilicon layer. The P-zone assembly further comprises a tunneling silicon nitride layer arranged between the first tunneling silicon oxide layer and the boron-doped polysilicon layer. The tunneling silicon nitride layer is used to block the boron element in the boron-doped polysilicon layer from being precipitated to the first tunneling silicon oxide layer. The application inhibits the precipitation of the boron element in the boron-doped polysilicon layer through the silicon nitride layer, enhances the passivation effect, and further improves the final conversion efficiency and reliability of the battery.

The invention provides a semiconductor device and a preparation method thereof, the semiconductor device comprises a substrate, a plurality of source lines, a plurality of source pads, a plurality of unit structures, a gate structure and a plurality of drain structures, the plurality of source lines are located on the substrate, extend along a first direction and are arranged at intervals along a second direction; each source electrode bonding pad is located on the corresponding source electrode line, extends in the second direction and is located between the adjacent source electrode lines; the plurality of unit structures are arranged on the source electrode bonding pad along the first direction and the second direction and are connected with the source electrode bonding pad, and at least two unit structures which are mutually staggered in the first direction are positioned on the same source electrode bonding pad; the gate structures extend in the second direction and are connected with the unit structures located on the same source electrode bonding pad; the plurality of drain electrode structures are respectively located above the corresponding source electrode bonding pads, and each drain electrode structure is connected with the unit structure connected with the corresponding source electrode bonding pad; the electrical performance of the semiconductor device is improved.

The invention relates to a pumping unit frequency conversion cabinet shutdown time-delay protection system, which comprises a shutdown time-delay protection device for performing shutdown time-delay protection on a frequency converter, and is characterized in that the shutdown time-delay protection device of the frequency converter comprises a power supply circuit for converting 220V alternating-current phase voltage into 12V direct-current voltage and providing the 12V direct-current voltage for a time-base integrated circuit NE555; a low trigger end THR port of the time-base integrated circuit NE555 receives a shutdown signal of the frequency converter, and a discharge end DIS port of the time-base integrated circuit NE555 is connected with a base electrode of the triode Q1 through a resistor R2; an emitting electrode of the triode Q1 is grounded, and a coil of a relay RLY1 is connected in series between a collector electrode of the triode Q1 and + 12V direct-current voltage; and a normally open contact of the relay RLY1 is connected in series in a coil loop of an alternating current contactor of an output loop of the frequency converter. The device not only realizes shutdown instant trigger delay protection, but also can be immediately started to run after a period of time delay.

A gate drive circuit adapted to high junction temperature environments, and its turn-on and turn-off methods, are disclosed. The gate drive circuit includes a main three-terminal transistor, a turn-off circuit, and an auxiliary circuit. The added auxiliary circuit generates an auxiliary current signal, either in the same direction or opposite to the control signal current, to the control electrode of the main three-terminal transistor during the turn-on and turn-off processes within a preset time period. This disclosure enables the generation of corresponding positive or negative auxiliary current signals at the control electrode of the three-terminal transistor. During the conduction process, the auxiliary circuit can generate a reverse auxiliary current signal at the control electrode of the three-terminal transistor during the current rise phase, reducing the drive current of the turn-on signal to decrease di. d / dt, suppressing the turn-on current; during the turn-off process, the auxiliary circuit can generate a unidirectional auxiliary current signal at the control electrode of the three-terminal transistor in the current-decreasing segment, increasing the drive current of the turn-off signal and accelerating the turn-off speed.

An embodiment of the present application proposes a phase change memory and a manufacturing method thereof, wherein the phase change memory comprises: a phase change memory unit, wherein the phase change memory unit comprises at least a first electrode, a gating layer, and a second electrode stacked in sequence; the gating layer comprises a first sub-gating layer and a second sub-gating layer stacked alternately; the material of the first sub-gating layer comprises at least germanium, a chalcogen element, and a first doping element; wherein the chalcogen element comprises sulfur and / or selenium; the material of the second sub-gating layer comprises a preset metal element; when the first electrode and the second electrode receive a voltage, the first doping element and the preset metal element are used to provide metal ions for the gating layer.

The application provides a two-dimensional multi-bridge channel transistor with self-aligned source-drain doping and a preparation method thereof. The two-dimensional multi-bridge channel transistor comprises a substrate and a plurality of channel structures arranged on the substrate. Each of the plurality of channel structures comprises a gate metal layer arranged on the substrate, a first high-k gate dielectric layer arranged around the first gate metal layer, a low-k gate dielectric layer arranged around the side surface of the first high-k gate dielectric layer, and a two-dimensional semiconductor material layer arranged on the high-k gate dielectric layer and the low-k gate dielectric layer, wherein part of the two-dimensional semiconductor material is induced to phase change into a two-dimensional semimetal / metal material layer by a solid source doping source. According to the two-dimensional multi-bridge channel transistor and the preparation method thereof, the source-drain contact resistance is reduced, the low-k sidewall process compatible with the two-dimensional semiconductor integrated circuit is realized, the parasitic is reduced, and the speed of the transistor is improved.

This application provides a CMOS device and its fabrication method, relating to the field of semiconductor technology. The method includes providing a substrate; sequentially depositing a buffer film layer and a tensile stress film layer on the substrate surface; irradiating the tensile stress film layer in an NMOS region to enhance the tensile stress of the tensile stress film layer in the NMOS region; removing the tensile stress film layer and the buffer film layer, and transferring the stress of the tensile stress film layer to the NMOS region; forming a source region and a drain region in a PMOS region to form a PMOS transistor located in the PMOS region, wherein the source region and drain region of the PMOS transistor are respectively formed in the PMOS regions on both sides of a first gate structure. Irradiating the tensile stress film layer in the NMOS region reduces the hydrogen content of the tensile stress film layer in the NMOS region, enhances the tensile stress of the tensile stress layer in the NMOS region, and alleviates the impact of tensile stress on the PMOS region. The method is simple, does not require multiple tensile stress layer growth and removal, and reduces costs.

The application relates to a semiconductor structure and a forming method thereof. The semiconductor structure comprises a substrate, a first transistor comprising a first channel in the substrate and a first end on the surface of the substrate, the first end being used for connecting with a first type of storage unit, and a second transistor comprising a second channel in the substrate and a second end on the surface of the substrate, the second end being used for connecting with a second type of storage unit, and the width of the second channel is greater than that of the first channel. The application can make the manufacturing process of the first transistor compatible with that of the second transistor, and simplify the manufacturing method of the semiconductor structure. Furthermore, the application is helpful to improve the integration density of the storage unit with the first transistor and / or the second transistor in the memory, and reduce the size of the storage unit, and lays a foundation for expanding the application field of the memory.

The invention belongs to the technical field of semiconductors, and provides a preparation method of a PMOS (P-channel Metal Oxide Semiconductor) transistor, which is suitable for manufacturing the PMOS transistor with the line width of a source / drain structure smaller than 40nm, and comprises the following steps of: providing a substrate, and forming a source / drain groove on the substrate; growing a SiGe material in the source / drain groove to form a SiGe layer, and growing a Si thin film layer on the surface of the SiGe layer to form a laminated structure of the SiGe layer and the Si thin film layer; growing a first Co thin film layer on the laminated structure, and then performing annealing treatment to enable Co in the first Co thin film layer to react with Si in the Si thin film layer to generate a first CoSi2 thin film layer; wherein the overall structure formed in the source / drain groove is a source / drain electrode, and the first CoSi2 thin film layer is the upper structure of the source / drain electrode. The invention also provides a PMOS (P-channel Metal Oxide Semiconductor) transistor, a CMOS (Complementary Metal Oxide Semiconductor) circuit and a preparation method of the CMOS circuit. According to the technical scheme, Si epitaxy is carried out on the SiGe layer to form the Si thin film layer, so that enough Si is provided for the subsequent CoSi2 manufacturing process, and formation of low-resistance-phase CoSi2 is promoted.

This application provides a semiconductor device and a method for manufacturing the same. The semiconductor device includes a substrate, a source electrode, a drain electrode, and a channel structure disposed on one side of the substrate. The channel structure is located between the source electrode and the drain electrode. The channel structure includes a stack of multiple nanosheets, a gate electrode surrounding the nanosheets, and a cavity. The cavity is located at least between the channel structure and the substrate. The cavity is formed by the channel structure, the source electrode, the drain electrode, and the substrate surrounding the cavity. In other words, the cavity is located below the channel structure, the source electrode, and the drain electrode, without any contacting film layers, thus forming a fully floating structure. This can significantly improve the gate control performance of the semiconductor device, reduce the subthreshold swing of the semiconductor device, reduce leakage current and parasitic capacitance, increase the drive current, and improve the performance of the semiconductor device.

The present application provides a complementary metal oxide semiconductor (CMOS) field effect device, comprising a substrate; a first n-type doped S / D region and a second n-type doped S / D region; a first p-type doped S / D region and a second p-type doped S / D region; a first channel layer disposed above the substrate, the first channel layer comprising a first sub-layer and a second sub-layer; wherein the first and second n-type doped S / D regions are disposed on a first side of the first channel layer, and the first and second p-type doped S / D regions are disposed on a second side of the first channel layer, the second side being opposite to the first side; wherein an energy of a conduction band edge of the first sub-layer is lower than an energy of a conduction band edge of the second sub-layer; and wherein an energy of a valence band edge of the first sub-layer is lower than an energy of a valence band edge of the second sub-layer; and a gate structure adjacent to the first sub-layer and the second sub-layer of the first channel layer.

The invention provides a semiconductor device, electronic equipment and a preparation method of the semiconductor device. Relates to the technical field of semiconductors. The semiconductor device comprises a P-type transistor, the P-type transistor comprises a first electrode, a second electrode, a channel, a grid electrode and a grid electrode side wall, and the first electrode comprises boron; in addition, the semiconductor device further comprises a first film layer and a dielectric barrier layer, the first film layer is located on the first electrode, the first film layer comprises boron, and the boron content in the first film layer is larger than that in the first electrode; the surface of the substrate comprises a first region located on the periphery of the first pole, the first region can correspond to a channel of the P-type transistor, and at least part of the first region is covered by the dielectric barrier layer. Boron in the first film layer can be inhibited from diffusing into a channel of the P-type transistor by using the dielectric barrier layer. Therefore, the hole mobility of the channel layer can be improved, and the driving circuit of the P-type transistor is improved.

The embodiments of the present disclosure provide a semiconductor structure and a manufacturing method thereof. The semiconductor structure comprises a substrate and a plurality of memory cell transistors on the substrate. Each memory cell transistor comprises a nanosheet group, the nanosheet group comprising a plurality of nanosheets arranged at intervals and extending along a first direction, the nanosheet comprising a channel region; a gate layer covering a plurality of channel regions of the nanosheet group; the first direction is parallel to a surface of the substrate; and a plurality of data storage elements are located on one side of the nanosheet group along the first direction, each data storage element being electrically connected to the plurality of nanosheets of one memory cell transistor.

This application provides a semiconductor device and a method for fabricating the same. The method includes: providing a substrate comprising a first region and a second region; forming a hard mask layer on the substrate to expose a field oxide layer region in the first region and an isolation region in the second region containing a portion of the isolation structure adjacent to the active region; performing an oxidation process to form a field oxide layer in the first region and a bird's beak oxide layer on the active region in the second region, the bird's beak oxide layer having a thin center and thick edges; and removing the hard mask layer and the bird's beak oxide layer to expose an active region in the second region with an upwardly curved upper surface. This application forms an upwardly curved active region without increasing process steps, and increases the effective width / length of the device without increasing the active region layout size, thereby simultaneously suppressing threshold voltage drift and increasing the device drive current, achieving high performance, low power consumption, and improved reliability.

The application discloses a preparation method of a semiconductor device and electronic equipment, and the method comprises the following steps: alternately stacking a plurality of insulating layers and metal layers on a substrate to form a laminated structure; forming a plurality of transistors arranged in a multilayer array in the laminated structure, wherein the transistors comprise a via, a first isolation layer, a second isolation layer, a channel layer, a gate dielectric layer and a metal gate layer; the first isolation layer and the second isolation layer are located on two opposite sidewalls of the via; the channel layer covers the sidewalls of the first isolation layer and the second isolation layer respectively to form a first channel, a second channel, a third channel and a fourth channel; the gate dielectric layer covers the channel layer; and the metal gate layer covers the gate dielectric layer.

The invention discloses a semiconductor device and a manufacturing method thereof, and electronic equipment, and the manufacturing method of the semiconductor device comprises the steps: forming sacrificial layers and conductive layers which are sequentially and alternately arranged on a substrate in the thickness direction of the substrate, enabling the sacrificial layers and the conductive layers which are sequentially and alternately arranged to form a stacked structure, and enabling the lattice mismatch degree of the sacrificial layers and the conductive layers to be smaller than or equal to 0.5%; forming a groove extending along a direction perpendicular to the substrate in the stack structure through patterned etching, the groove exposing a side wall of the conductive layer and a side wall of the sacrificial layer; selectively etching the side wall of the exposed sacrificial layer, removing the sacrificial layer to form a cavity, reserving the conductive layer, and exposing at least part of the side surface of the conductive layer by the cavity; filling the cavity and the groove with an insulating layer; removing part of the insulating layer to form a channel which exposes at least part of the side surface of the conductive layer; and sequentially forming a gate insulating layer and a gate electrode on the side surface of the exposed conductive layer.

This application provides a semiconductor structure, its manufacturing method, and an electronic device. The manufacturing method of the semiconductor structure includes: fabricating a first sacrificial structure on one side of a substrate; fabricating a second sacrificial structure; the second sacrificial structure and the first sacrificial structure having different heights and thicknesses; fabricating a first trench; exposing the second sacrificial structure and the first sacrificial structure on the sides of the first trench; fabricating a semiconductor layer; the semiconductor layer at least conformally covering the first trench; replacing the first and second sacrificial structures with a first gate structure and a second gate structure to obtain a transistor; the first gate structure includes a first gate electrically isolated from the semiconductor layer, and the second gate structure includes a second gate electrically isolated from the semiconductor layer. This application achieves a transistor with dual gates of different heights and thicknesses, which can comprehensively enhance the gate's control over the channel region, improve the channel electric field, enhance carrier transport, increase the drive current, and enable the semiconductor structure to have a high on / off ratio.

This invention relates to a semiconductor structure comprising: multiple memory modules, each memory module including: a first memory cell; a second memory cell located on one side of the first memory cell; a third memory cell located on the other side of the first memory cell; a first transistor, with its first terminal electrically connected to the input terminal of the first memory cell; a second transistor, with its first terminal also electrically connected to the input terminal of the first memory cell; a third transistor, with its first terminal electrically connected to the input terminal of the second memory cell, and the channel width of the third transistor being greater than the channel widths of both the first and second transistors; and a fourth transistor, with its first terminal electrically connected to the input terminal of the third memory cell, and the channel width of the fourth transistor being greater than the channel widths of both the first and second transistors. This application can effectively improve the drive current of the memory cell.