39results about How to "Improve shutdown characteristics" patented technology

A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a heterojunction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the heterojunction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

A method for forming and the structure of a strained lateral channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a single crystal semiconductor substrate wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect the body region. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials and alloy composition.

The present invention provides, as a porous layer that can be used for a member for a non aqueous secondary battery having excellent shutdown characteristics, a porous layer including a polyvinylidene fluoride-based resin, wherein, assuming that a sum of individual amounts of crystal form α and crystal form β contained in the polyvinylidene; fluoride-based resin is 100 mol %, the amount of crystal form α contained in the polyvinylidene fluoride-based resin is not less than 10 mol % and not more than 65 mol %.

A method for forming and the structure of a strained vertical channel of a field effect transistor, a field effect transistor and CMOS circuitry is described incorporating a drain, body and source region on a sidewall of a vertical single crystal semiconductor structure wherein a hetero-junction is formed between the source and body of the transistor, wherein the source region and channel are independently lattice strained with respect to the body region and wherein the drain region contains a carbon doped region to prevent the diffusion of dopants (boron) into the body. The invention reduces the problem of leakage current from the source region via the hetero-junction and lattice strain while independently permitting lattice strain in the channel region for increased mobility via choice of the semiconductor materials.

A double port regulator assembly includes a first fluid port and a second fluid port. A fixed valve seat assembly is disposed proximate the first fluid port and a floating valve seat assembly is disposed proximate the second fluid port. A first valve plug cooperates with the fixed valve seat assembly to open and close the first fluid port and a second valve lug cooperates with the floating valve seat assembly to open and close the second fluid port. The floating valve seat assembly includes a floating valve seat that is movable with respect to the fixed valve seat.

An anode-short tunnel pump IGBT belongs to the technical field of semiconductor power devices. With an anode-short structure and a tunnel pump structure simultaneously introduced into a traditional IGBT, or a tunnel pump structure into an anode-short IGBT, or an anode-short structure into a tunnel pump IGBT, the invention gives the advantages of both the anode-short IGBT and the tunnel pump IGBT to the anode-short tunnel pump IGBT so as to improve the turn-off characteristic of the device and lower the conductive voltage drop of the device. The invention can better reconcile the positive saturation voltage drop with the turn-off time, and optimize the conductive characteristic of the device, so that the invention is suitable in particular for application environments characterized by high voltage, heavy current and high frequency.

A polyethylene microporous membrane and a manufacturing method thereof are provided. The polyethylene microporous membrane exhibits a Gurley air permeability of 1 to 1,000 sec/100mL/25mum and in which the total length of widths of waves in the widthwise direction of the microporous membrane is at most one-third of the overall width of the microporous membrane. The present invention provides the polyethylene microporous membrane having excellent flatness without impairing the other important physical properties such as permeability.

The invention discloses an insulated gate bipolar transistor (IGBT) with deep energy level impurity implantation and belongs to the technical field of semiconductor power devices. Deep energy level N-type impurities are implanted into an N-drift region (8) on the basis of the traditional Planar FS-IGBT. According to the characteristic that the ionization degree of the deep energy level impurities is raised and the impurity concentration is raised along with the temperature increase, the parasitic PNP transistor alpha PNP of the IGBT can be effectively reduced, so that the high-temperature leakage current of the IGBT is reduced, and the overall loss of the IGBT is reduced further; and moreover, the electron concentration increased in the N-drift region (8) and holes in the drift region are accelerated and compounded, and the deep energy level impurity self is a deathnium, the electron hole recombination is accelerated, the turnoff process of the IGBT is reduced, the turnoff characteristics are effectively improved, and the reliability of the IGBT is improved.

A laminated polyolefin microporous membrane is disclosed. The laminated polyolefin microporous membrane includes a first polyolefin microporous membrane, and a second polyolefin microporous membrane. A shutdown temperature of the laminated polyolefin microporous membrane is from 128° C. to 135° C., an air permeation resistance increase rate from 30° C. to 105° C. per 20 μm of thickness of the laminated polyolefin microporous membrane is less than 1.5 sec/100 cc Air/° C., and a variation range in an F25 value of the laminated polyolefin microporous membrane in a longitudinal direction is not greater than 1 MPa. The F25 value represents a value determined by dividing the load at 25% elongation of a sample of the laminated polyolefin microporous membrane as measured with a tensile tester by the cross-sectional area of the sample polyolefin microporous membrane.

The invention discloses a low-on-resistance trench silicon carbide power device and a manufacturing method thereof. The cellular structure comprises an N-type substrate, an N-type epitaxial layer anda trench; a graphene layer is arranged on the side wall of the trench; a gate oxide layer and a polycrystalline silicon gate are arranged in the trench; a passivation layer is arranged above the polycrystalline silicon gate; a P-type body region, an N-type source region and a P-type body contact region are arranged on the two sides of the trench; a P-type shielding layer is arranged below the graphene layer; source metal is arranged on the upper surface of the source region; and drain metal is arranged on the lower surface of the substrate. According to the power device, an electron beam method is used, metal and a carbon source gas are used for assisting, and the graphene layer grows on the side wall of the trench. The power device is characterized in that the graphene layer on the side wall of the trench reduces the on resistance. The shielding layer below the graphene layer shields the current flowing through the graphene layer when the device is in an off state, and the turn-off characteristic of the device is improved. The growth of the graphene layer is assisted by metal nickel and the carbon source gas, so that the uniformity, the thickness and the growth rate of the graphene layer are improved.

The invention discloses an array substrate, a preparation method thereof, a display panel and a device. The array substrate comprises a pixel circuit, the pixel circuit comprises a first transistor and a second transistor, the first transistor comprises a first active layer, the second transistor comprises a second active layer, and both the first active layer and the second active layer comprisesilicon; the array substrate further comprises a first type inorganic layer, a second type inorganic layer and a first via hole, the first via hole is located above the first active layer and at leastpenetrates through the second type inorganic layer, and the hydrogen ion concentration in the first active layer is smaller than that in the second active layer. The first active layer is subjected to high-temperature processing through the first via hole, so that the hydrogen ion concentration in the first active layer is smaller than that in the second active layer, the high-temperature processing frequency of the second transistor is reduced while good performance of the first transistor is guaranteed, and it is guaranteed that the second transistor is small in sub-threshold swing, good inturn-off characteristic and small in leakage current; and good overall characteristics of the pixel circuit are ensured.

The present invention provides a microporous membrane having an excellent balance of temperature characteristics, shrinkage characteristics, permeability, and strength, and thereby realizes a separator for a non-aqueous electrolyte secondary battery and a non-aqueous electrolyte secondary battery, having excellent performance and excellent safety. A polyolefin microporous membrane having;

a temperature difference not less than 7.2° C. between a shutdown shrinkage temperature and a maximum shrinkage temperature in a TD measured by TMA;

a shrinkage rate difference less than 25% between a shutdown shrinkage rate and a maximum shrinkage rate in the TD;

a pin puncture strength at a membrane thickness of 16 μm being not less than 400 gf; and

a ratio of pin puncture strength to air permeation resistance at a membrane thickness of 16 μm being from 2.0 to 4.0 (gf/(sec/100 cc)).

The invention discloses a polyethylene composition for preparing a power lithium battery diaphragm, and the composition is formed by blending polyethylene resin and diluent. According to an ultra-high molecular weight polyethylene/high density polyethylene/linear low density polyethylene/diluent system, the character of mechanical property of the diaphragm can be greatly improved by means of ultra-high molecular weight polyethylene, and the mechanical strength of a lithium battery diaphragm finished product is improved. Linear low density polyethylene can produce enough free radicals under low irradiation intensity, a polyethylene chain of a long molecular chain is protected, and the lithium battery diaphragm finished product keeps the excellent mechanical property and has the high fusing-off temperature. According to the lithium battery diaphragm prepared through the polyethylene composition, high porosity, high insulativity and good turn-off characteristic of an ordinary polyethylene lithium battery diaphragm are kept, high tearing strength, high puncture resistance strength and high-fusing temperature are achieved, and the polyethylene composition is suitable for manufacturing power lithium batteries.

A configuration in which a voltage (a gate on voltage) of only one system is used as a voltage for turning scanning lines to a selected state is employed (single power supply system configuration). A unit circuit that constitutes a shift register within a gate driver includes a thin film transistor whose source terminal is connected to an output control node. In such a configuration, when the external power supply is stopped, a voltage supplied to a gate terminal of the thin film transistor and a voltage supplied to a drain terminal of the thin film transistor are set to the gate on voltage.

The invention discloses a novel driving topology and a driving method and a crosstalk suppression method thereof, which are suitable for a silicon carbide metal-oxide semiconductor field effect transistor of a half-bridge circuit. The novel driving topology comprises a primary side logic processing unit, two isolation units, two secondary side logic processing units, two multi-level driving circuits, two driving resistance networks and two turn-off drain current detection feedback circuits. According to the present invention, the next multi-level pulse signal is determined according to the feedback information of a detection circuit, the feedback self-adaption can be detected to optimize the turn-off characteristic, and the influence of inherent detection circuit hardware delay of the detection circuit is effectively eliminated through the subtraction of the secondary side logic control units. Therefore, the turn-off transient oscillation and voltage overshoot of a half-bridge circuit switching tube are suppressed. When an active tube acts, the influence of crosstalk is suppressed by adjusting the grid-source electrode level of a passive tube, so that parasitic opening and grid-source electrode negative voltage overshoot are prevented, the use reliability of the device is improved, and the service life of the device is prolonged.

This porous polyolefin film: has a shutdown temperature of 133 DEG C or lower; a porosity of 41% or higher; a value of 12,500 or higher for (longitudinal (MD) direction tensile elongation (%) * longitudinal (MD) direction tensile strength (MPa) + width (TD) direction tensile elongation (%) * width (TD) direction tensile strength (MPa))/2; and satisfies formula (1),where TSD (DEG C) is the shutdowntemperature and Tm (DEG C) is the lowest melting point of the melting points of respective layers. Formula (1) is Tm-TSD >= 0. Provided is a porous polyolefin film that offers excellent safety against internal short-circuit, thermal runaway, or the like without lowering the permeability of conventional microporous membranes.

The present invention addresses the problem of providing a microporous polyolefin membrane which has not only a low shutdown temperature but also an excellent membrane strength at the shutdown temperature, and imparts excellent shutdown characteristics and high safety if used as a separator for secondary batteries. The present invention provides, as a solution, the microporous polyolefin membrane which has a shutdown temperature of 135 DEG C or less, while having a crystal melting rate of 50% or less at the shutdown temperature.