3778 results about "Oxide semiconductor" patented technology

The invention provides a temperature compensation method and device for a silicon carbide MOS drive control chip, and the method comprises the steps: obtaining a junction temperature-electrical parameter set of a silicon carbide MOS, and carrying out the thermoelectric coupling simulation modeling processing of a junction temperature-electrical parameter mapping data set, and obtaining three-dimensional temperature-efficiency characteristic data; performing real-time parameter analysis and dynamic execution on the three-dimensional temperature-efficiency characteristic data to obtain an optimized switching characteristic waveform; extracting the optimized switching characteristic waveform frequency domain characteristics, and generating a dynamic frequency modulation parameter; and performing dead time iterative optimization on the dynamic frequency modulation parameters to obtain a control parameter combination of the silicon carbide MOS.

The invention discloses an irradiation-reinforced SiC super-junction MOS (Metal Oxide Semiconductor) structure and a preparation process thereof, and belongs to the technical field of MOS semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; by arranging the lightly doped N layer in the middle of the N drift layer and arranging the laterally symmetrical trapezoidal P-layers on the two sides of the N drift layer, the device can interact with electrons in the N drift layer, accelerate carrier recombination, reduce the influence of redundant carriers on the performance of the device, effectively reduce the performance degradation caused by irradiation, and improve the performance of the device. According to the invention, the concave heavily-doped N layer is formed at the bottom end of the lightly-doped N layer, so that the carrier concentration of the region can be greatly improved, and the conductivity is remarkably enhanced.

The invention discloses a scene self-adaptive aging test method and system for an extra-high voltage MOS (Metal Oxide Semiconductor), and relates to the related technical field of MOS test, and the method comprises the steps: building a device aging test platform; performing test condition analysis on the application scene information of the target extra-high voltage MOS device; performing pretest adjustment on the target extra-high voltage MOS device, and determining an aging test update parameter table; performing aging test monitoring on the target extra-high voltage MOS device; and calling an extra-high voltage MOS aging adaptive evaluator to process and evaluate the device aging scene test data stream set to obtain a device scene aging performance test result. The technical problems that in the prior art, due to the fact that an MOS aging test lacks scene adaptability, the aging process of the MOS device in the actual application environment is difficult to accurately simulate, the test pertinence is insufficient, and the result accuracy is poor are solved, and the technical effect of improving the MOS device aging test pertinence and the result accuracy is achieved.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

The invention discloses an unmanned aerial vehicle edge intelligent analysis terminal based on a single Beidou, and relates to the technical field of satellite navigation and unmanned aerial vehicles, and the terminal comprises an edge calculation unit which is in communication connection with a high-definition image collection module, a high-precision positioning module, a Beidou short message communication module and a ground control station; the high-definition image acquisition module is used for acquiring high-definition image data through a CMOS (Complementary Metal Oxide Semiconductor) sensor; the high-precision positioning module is used for acquiring centimeter-level positioning data in the flight process of the unmanned aerial vehicle through an RTK technology and an INS system; the edge calculation unit is used for carrying out target recognition through a lightweight convolutional neural network in combination with a YOLOv5 target detection algorithm; the Beidou short message communication module is used for realizing short message communication between the unmanned aerial vehicle and a ground control station by using RDSS service; and the ground control station is used for creating a user interface by using Qt, carrying out data visualization through Tableau and adopting a security protocol. According to the scheme, remote control, remote information transmission and high-precision positioning functions in a complex environment of the unmanned aerial vehicle are realized.

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with low threshold voltage, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, an N well layer, a P well layer and a heavily doped P layer are formed in the semiconductor epitaxial layer through ion implantation, the grid electrode comprises a triangular grid electrode and a rectangular grid electrode, the grid oxide layer covering the surface of the triangular grid electrode is in contact with the N substrate layer, and the N drift layer is divided into a left part and a right part by the grid oxide layer. According to the invention, the grid electrode is designed to further comprise the triangular grid electrode, the electric field effect of the grid electrode between the tip part of the triangular grid electrode and the drain electrode is better, but the grid oxide layer wrapped by the triangular grid electrode at the tip part is thicker, so that charges flowing out of the drain electrode gather towards the inside of the heavily doped N layer more quickly along the grid oxide layer; at the moment, more charge flow can be provided in a smaller grid voltage environment.

The invention provides a germanium-silicon groove preparation method, which comprises the following steps of: forming a PMOS (P-channel Metal Oxide Semiconductor) gate structure and an NMOS (N-channel Metal Oxide Semiconductor) gate structure on a semiconductor substrate, arranging a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer in hard mask layers of the PMOS gate structure and the NMOS gate structure, exposing the second silicon nitride layer through a gate side wall, and covering a germanium-silicon mask layer, a patterned photoresist protection NMOS gate structure is formed, the germanium-silicon mask layer exposed in the PMOS region is etched, a groove is formed, and at least part of the second silicon nitride layer is reserved at the top of the PMOS gate to protect the silicon oxide layer; according to the method, the first silicon nitride layer and the germanium-silicon mask layer are etched, germanium-silicon deposition is carried out, and the residual second silicon nitride layer and the germanium-silicon mask layer are removed together through wet etching, so that the height difference of the hard mask layer caused by the conventional process of the PMOS gate and the NMOS gate is eliminated, the process load is avoided, the process steps are simplified, and the process cost is reduced.

The invention provides a metal oxide semiconductor electrostatic protection device. The metal oxide semiconductor electrostatic protection device comprises a substrate; a well region of a first conductivity type disposed in the substrate; the source electrode region is formed in the well region of the first conduction type, the source electrode region comprises a first heavily doped region, and the first heavily doped region is of a second conduction type; a drain region; a gate structure; the body contact region comprises a third heavily doped region, and the third heavily doped region is of the first conduction type; wherein the drain region comprises a plurality of second heavily doped regions, the plurality of second heavily doped regions are of a second conduction type, and the plurality of second heavily doped regions are arranged at positions adjacent to the gate structure; the fourth heavily doped region is of the second conduction type, and the fourth heavily doped region is not arranged close to the gate structure; and a lightly doped drain region of the second conductivity type disposed below the plurality of second heavily doped regions and the fourth heavily doped regions. By changing the structure of the drain electrode heavily doped region, the ESD current distribution is improved, and the ESD endurance capability of the device is improved.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

An integrated circuit includes a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region and the drain region. The nanosheets also alternate with field plate conductor layers that extend between the gate conductor layers and the drain region.

The invention provides an LDMOS (Laterally Diffused Metal Oxide Semiconductor) drift region LOCOS growth method. The LDMOS drift region LOCOS growth method comprises the following steps: providing a silicon substrate; defining an LOCOS region on the surface of the silicon substrate, wherein the region except the LOCOS region in the silicon substrate is a non-LOCOS region; surface modification is carried out on the silicon substrate in the LOCOS area, a lattice damage area is formed in the LOCOS area, and the area outside the lattice damage area in the silicon substrate is a non-lattice damage area; the oxide growing on the surface of the silicon substrate is consumed through a furnace tube, and the growth rate of the oxide in the lattice damage area is larger than that of the oxide in the non-lattice damage area; the oxide is etched, the oxide in the non-LOCOS area is removed, and the remaining oxide in the LOCOS area serves as LOCOS. According to the technical scheme, the LOCOS is generated through the difference formed by the silicon substrate by utilizing the characteristics that crystal lattices are damaged after the ions are injected into the silicon substrate and the speed of generating oxides during high-temperature oxidation is higher than that of generating oxides during high-temperature oxidation of the silicon substrate, and compared with a traditional mode, the proportion of beaks is reduced, so that the size of the device is reduced.

The present disclosure relates to a ferroelectric thin film transistor and may include: a substrate; a gate electrode layer formed on the substrate; a ferroelectric layer formed on the gate electrode layer, including a hafnium-based oxide, and including an uneven portion having at least one or more step that is formed on the gate electrode layer; a semiconductor channel layer formed on the ferroelectric layer and including an oxide semiconductor; a drain electrode layer connected to the semiconductor channel layer at one side of the gate electrode layer; and a source electrode layer connected to the semiconductor channel layer at the other side of the gate electrode layer.

A display apparatus includes a substrate including a display area in which a display element is arranged, a first thin-film transistor arranged in the display area and including a first semiconductor layer and a first gate electrode insulated from the first semiconductor layer, the first semiconductor layer including a silicon semiconductor, a first interlayer insulating layer covering the first gate electrode, a second thin-film transistor on the first interlayer insulating layer and including a second semiconductor layer and a second gate electrode insulated from the second semiconductor layer, the second semiconductor layer including an oxide semiconductor, and an upper electrode arranged on the first interlayer insulating layer and including a same material as that of the second semiconductor layer and at least overlapping the first gate electrode.

The invention discloses a neuron circuit and brain-like computing system based on multi-neuromorphic behaviors, and the neuron circuit maps an appreciation-Ross model to the field of physical circuits through a capacitance dynamic response mechanism and the cross-interval nonlinear characteristics of a metal-oxide semiconductor field effect transistor. Then the expanded appreciation-Ross model is realized through the design of a metal-oxide semiconductor field effect transistor; the neuron circuit comprises a membrane voltage circuit, a slow variable circuit and a recovery variable circuit. The membrane voltage circuit is used for receiving an input signal and accumulating membrane voltage; the slow variable circuit is used for accumulating a slow variable according to the membrane voltage and enabling the neuron circuit to enter a hyperpolarization stage after the slow variable is greater than a preset threshold value; the recovery variable circuit is used for outputting a recovery variable according to the film voltage delay and resetting the film voltage to a resting potential through the recovery variable.

The invention provides an IO port hot plug application circuit and device, and the circuit comprises a pull-down driving module which comprises an MOS tube Mn0, a capacitor C1 and a current source, and the capacitor C1 is connected in parallel between a grid electrode and a source electrode of the MOS tube Mn0; the current source is connected to the grid electrode of the MOS tube Mn0 and provides charging and discharging current for the capacitor C1; the drain electrode of the MOS tube Mn0 is connected with an SCL or SDA signal line, and the source electrode of the MOS tube Mn0 is grounded; the positive input end of the comparator CMP is connected with a reference level, and the negative input end of the comparator CMP is connected with an SDA or SCL signal line; the digital control system comprises a feedback loop of a main switch signal Hjen of a hot plug process and a real-time driving signal Hjctrl of an MOS (Metal Oxide Semiconductor) tube of an analog circuit; the output end of the pull-down driving module is connected with the IO interface, the output end of the comparator CMP is connected to the signal detection end of the digital control system, and the Hjctrl signal end of the digital control system is connected to the control end of the pull-down driving module.

The invention relates to a class-C voltage-controlled oscillator with negative-pressure substrate bias and a use method thereof. Aiming at the problem that a traditional C-type voltage-controlled oscillator is difficult to start, the C-type voltage-controlled oscillator provided by the scheme adopts different circuits to simultaneously control the grid voltage and the substrate voltage of the cross-coupled pair transistors, so that the transistors are effectively prevented from entering a linear region, and the C-type voltage-controlled oscillator is quickly started and stably works in a C-type oscillation mode. The circuit structure of the scheme comprises an NMOS (N-channel Metal Oxide Semiconductor) cross coupling circuit, a PMOS (P-channel Metal Oxide Semiconductor) cross coupling circuit, an LC resonant cavity circuit, an amplitude detection circuit, a Schmidt signal processing circuit and a negative voltage charge pump circuit. Wherein the Schmidt signal processing circuit and the negative voltage charge pump circuit rapidly process an initial oscillation signal and provide negative voltage required by the system, and a substrate of the NMOS cross coupling tube is biased. According to the scheme, the design structure is simple, the tuning range is wide, and a new thought is provided for research and design of quick start of the C-type voltage-controlled oscillator.

The utility model relates to the related field of voltage reference circuits, in particular to a voltage reference circuit with a simple structure and capable of realizing high-voltage application, which comprises a resistor R5 connected with a high-voltage power supply, MOS (Metal Oxide Semiconductor) transistors PM1, PM2 and PM3, triodes Q0, Q1 and Q2, and MOS transistors NM0 and NM5, compared with a traditional structure, the circuit is simple in structure and easy to implement, and due to the fact that an operational amplifier and a band-gap reference circuit are not needed, and the number of electronic components is small, the circuit area is greatly reduced; the high-voltage-resistant voltage-reducing and voltage-stabilizing circuit is simple in structure, low in process requirement, free of a high-voltage process and free of additional special devices, adopts a low-voltage process to enable the circuit to generate a low-voltage reference capable of bearing a high-voltage power supply of more than 100V, achieves the purposes of high-voltage resistance, voltage reduction and voltage stabilization, and has the characteristics of low cost and convenience in design, so that the high-voltage-resistant voltage-reducing and voltage-stabilizing circuit has very high use value and application value and is suitable for popularization.

A scan driver includes stages which sequentially output scan signals to scan signal lines during an active period of an N-th frame, and at least one of the stages includes an output node controller that supplies a gate-on voltage to a pull-up node in response to a gate control signal of a display driver; and an output controller that outputs a scan signal to a scan signal line by outputting a scan clock signal to a scan signal line in case that the gate-on voltage is supplied to the pull-up node, wherein the output node controller includes a thin-film transistor including a first active layer, and directly or indirectly connected to the pull-up node, and another thin-film transistor including a second active layer including an oxide semiconductor material different from a oxide semiconductor material of the first active layer, and directly connected to the pull-up node.

The invention discloses a floating-point number index maximum value searching circuit and an in-memory computing chip. The searching circuit comprises an SRAM (Static Random Access Memory) unit matrix which comprises a plurality of rows and columns of SRAM units, wherein each unit comprises NMOS (N-channel Metal Oxide Semiconductor) tubes N1-N5 and PMOS (P-channel Metal Oxide Semiconductor) tubes P1 and P2; n1, N2, P1 and P2 are in reverse cross coupling to form a pair of storage nodes Q and QB; the grid electrode of the N5 is connected with a node QB; the grid electrode of the N3 in the ith row is connected with a word line WLLlt; igt; the grid electrode of the N4 is connected with a word line WLRlt; igt; ; the drain electrode of each column of N5 is connected in series with the source electrode of the next column of N5, and the source electrode of the first column of N5 is connected with a signal SELlt; igt; the N5 drain electrode of the last column is connected with a signal PRE; in the jth column, N3 is a corresponding node Q and a bit line BLlt; jgt; the transmission tube N4 is a corresponding node QB and a bit line BLBlt; jgt; and a transmission tube. According to the invention, the number of searching cycles is saved, the calculation time is shortened, the subsequent calculation amount is reduced, the efficiency is improved, the power consumption is reduced, and the defects of relatively high power consumption, complex hardware implementation, relatively long calculation delay and the like of an existing circuit are overcome.

The invention provides an MOSFET and a manufacturing method thereof. The MOSFET includes a substrate; the epitaxial layer is arranged on the substrate; the trench gate group comprises a first trench gate and a plurality of second trench gates, the first trench gate extends into the epitaxial layer from the surface of the side, away from the substrate, of the epitaxial layer, the first trench gate extends in the first direction on the plane where the epitaxial layer is located, and the second trench gates are arranged at intervals in the first direction; the orthographic projection of the second trench gate on the substrate is located in the orthographic projection range of the first trench gate on the substrate, the top of the second trench gate is in contact with the bottom of the first trench gate, and a gate layer in the second trench gate is connected with a gate layer in the first trench gate; each shielding region wraps the bottom and all the side walls of the second trench gate and extends towards the surface of the side, away from the substrate, of the epitaxial layer so as to cover the side wall of the first trench gate, and the multiple shielding regions are arranged at intervals. The shielding region has a three-dimensional structure, so that the stress of a trench gate oxide electric field can be reduced, the cell size of the MOSFET can be reduced, and the current density of the MOSFET can be improved.

The invention provides a silicon carbide MOS drive control chip overcurrent protection method and device, and the method comprises the steps: setting a forward sampling channel and a reverse sampling channel at a source sampling resistor, setting different sampling time windows for different sampling channels, carrying out the peak shifting setting of the time windows of the double sampling channels, and carrying out the peak shifting setting of the time windows of the double sampling channels, thereby achieving the overcurrent protection of a silicon carbide MOS drive control chip. The time period with the strongest common-mode interference can be avoided; meanwhile, the switching speed of the silicon carbide MOS device is mapped into a theoretical common-mode interference waveform, and the waveform and a bidirectional sampling signal are synthesized, so that a common-mode interference component in the sampling signal can be accurately separated, and the synthesized current signal is more accurate; on the basis, current signals are compensated by combining on-resistance change caused by junction temperature change, and overcurrent protection is carried out by adopting a graded protection strategy. According to the method, the influence of common-mode interference on current sampling is effectively overcome through peak shifting design on sampling channel time and common-mode interference separation based on switching speed.

The invention relates to the technical field of MOS transistors, and discloses a low-power-consumption operation control method, device and equipment of an MOS transistor and a storage medium, and the method comprises the steps: collecting the working state feature data of the MOS transistor; performing change trend analysis on the working state characteristic data to obtain a current power consumption state and a power consumption fluctuation range; executing optimal threshold voltage adjustment parameter calculation based on the current power consumption state and the power consumption fluctuation range to obtain a target threshold voltage value; executing body bias control and grid voltage compensation according to the target threshold voltage value to obtain a body bias voltage control signal and a grid voltage control signal; and the power supply voltage and the working frequency of the MOS transistor are dynamically adjusted according to the body bias voltage and the grid voltage control signal, a voltage frequency working point is obtained, the sudden load change is rapidly responded, meanwhile, all control parameters are accurately adjusted, and the global optimal operation state of the MOS transistor is achieved.

The invention relates to a method and a circuit for accelerating suppression of transient energy of a mining intrinsic safety battery, and belongs to the field of mining intrinsic safety equipment. The circuit comprises at least two stages of cascaded protection modules, and each stage of protection module has the same circuit structure. Wherein the protection module comprises a current acquisition and comparison chip, a comparator, MOS (Metal Oxide Semiconductor) transistors Q1 and Q2, a voltage stabilizing diode and a resistor component. A protection circuit formed by at least two cascaded protection modules is arranged between an intrinsic safety type battery and mining equipment; and the output voltage and the output current of the intrinsic safety type battery are monitored in real time through the protection circuit. And if the output voltage or the output current is monitored to be abnormal, the connection between the intrinsic safety type battery and the mining equipment is quickly disconnected through the protection circuit, so that the instantaneous energy of the mining equipment is prevented from exceeding a dangerous value. The comparator can quickly act within about 15 microseconds to disconnect the mos tube, and the transient energy is controlled within 20 microseconds, which completely conforms to the specification.

The invention discloses a polarization insensitive filter based on a sub-wavelength grating structure, and belongs to the technical field of integrated photonic devices. The filter comprises an input transition waveguide, a multimode waveguide grating and an output transition waveguide which are connected in sequence. The multimode waveguide grating is composed of a central sub-wavelength grating waveguide and Bragg gratings symmetrically distributed on the two sides, and the effective refractive indexes of TE polarization and TM polarization are equal by adjusting the waveguide width and duty ratio of the central sub-wavelength grating, so that the polarization sensitivity of the device is eliminated fundamentally. And the input / output transition waveguide adopts a transition mode of mixing a tapered waveguide and a sub-wavelength grating waveguide, so that low-loss mode transmission between a straight waveguide and a multimode grating is realized. According to the invention, the anisotropic equivalent medium characteristic of the sub-wavelength grating is utilized, a function of simultaneously and effectively filtering TE and TM polarization is realized, and the filter has the advantages of polarization insensitivity, flexible design, compact structure, simple process and compatibility with a CMOS (Complementary Metal Oxide Semiconductor) process, and has important application value in the fields of optical communication, optical interconnection and the like.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) structure with a nanosheet full-surrounding grid electrode and a manufacturing process thereof, the MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a grid oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the grid electrode comprises a grid electrode covering layer and a grid electrode nanosheet; a plurality of grid nanosheets are arranged in a single MOS cell, are distributed in a horizontal matrix, extend to the inside of the grid covering layer and are in direct contact with the grid covering layer. Through the three-dimensional embedded contact between the nanosheet grids in horizontal matrix distribution and the high-conductivity covering layer, the static control capability of the channel is remarkably enhanced, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of a traditional planar device is broken through.

An electronic device includes a substrate, a first silicon transistor, a second silicon transistor and a first oxide semiconductor transistor. The first silicon transistor, the second silicon transistor and the first oxide semiconductor transistor are disposed on the substrate. The first silicon transistor has a first terminal electrically connected to a first voltage level, a second terminal and a control terminal. The second silicon transistor has a first terminal electrically connected to the second terminal of the first silicon transistor, a second terminal electrically connected to a second voltage level, and a control terminal electrically connected to the control terminal of the first silicon transistor. The first oxide semiconductor transistor has a first terminal electrically connected to the first terminal of the second silicon transistor. Wherein, a voltage value of the first voltage level is greater than a voltage value of the second voltage level.

The invention discloses an ultra-wideband high-linearity phased array switch, which comprises three ports, namely a transmitting end TX port, an antenna end ANT port and a receiving end RX port, and is characterized in that when a transmitting branch is switched on, a signal is transmitted from the TX port to the ANT port; when the receiving branch is conducted, a signal is transmitted from the ANT port to the RX port; the transmitting branch comprises a matching inductor L2, a transistor M5, a transistor M6, a transistor M1, a transistor M2 and a matching inductor L1, the receiving branch comprises a matching inductor L1, a transistor M3, a transistor M4, a transistor M7, a transistor M8 and a matching inductor L3, the proposed switch is designed by adopting a classic series-parallel structure, a deep N-well NMOS (N-channel Metal Oxide Semiconductor) transistor is used, and the matching inductor L1, the transistor M5, the transistor M6, the transistor M1, the transistor M2 and the matching inductor L3 are matched. The isolation degree of the transistor of the turn-off branch is improved by adopting a negative body bias technology, and meanwhile, the power processing capacity of the turn-off transistor is improved by adopting a negative voltage bias technology and a transistor stacking technology together.

The utility model provides a single-stage bridgeless conversion device integrating a Buck-Boost circuit and a full-bridge LCC circuit. The single-stage bridgeless conversion device comprises the bridgeless Buck-Boost circuit and the full-bridge LCC circuit. The Buck-Boost circuit comprises three switching tubes Q1, Q2 and Q3, and one of the switching tubes Q3 is multiplexed as an upper tube of the full-bridge LCC circuit. The Buck-Boost circuit is provided with three MOS (Metal Oxide Semiconductor) tubes, so that one MOS tube can be multiplexed as a switch tube Q3 of the LCC circuit. The MOS tubes Q1 and Q2 serve as input rectification MOS tubes to replace diodes, the loss can be obviously reduced, the efficiency can be improved, meanwhile, the voltage stress is equal to the input voltage, the MOS tubes can select 500V MOS tubes with high cost performance, two power diodes are omitted in a main loop, and meanwhile the full-bridge LCC can achieve higher power output and can be wider in application range.