2396 results about "Oxide semiconductor" patented technology

An integrated circuit includes a nanosheet laterally-diffused metal oxide semiconductor (LDMOS) transistor. The transistor includes source and drain regions having a first conductivity type that extend into a semiconductor substrate. A nanosheet region including semiconducting nanosheets extends between the source region and the drain region. The nanosheets alternate with gate conductor layers that extend between the source region and the drain region. The nanosheets also alternate with field plate conductor layers that extend between the gate conductor layers and the drain region.

The present disclosure relates to a ferroelectric thin film transistor and may include: a substrate; a gate electrode layer formed on the substrate; a ferroelectric layer formed on the gate electrode layer, including a hafnium-based oxide, and including an uneven portion having at least one or more step that is formed on the gate electrode layer; a semiconductor channel layer formed on the ferroelectric layer and including an oxide semiconductor; a drain electrode layer connected to the semiconductor channel layer at one side of the gate electrode layer; and a source electrode layer connected to the semiconductor channel layer at the other side of the gate electrode layer.

The invention provides an IO port hot plug application circuit and device, and the circuit comprises a pull-down driving module which comprises an MOS tube Mn0, a capacitor C1 and a current source, and the capacitor C1 is connected in parallel between a grid electrode and a source electrode of the MOS tube Mn0; the current source is connected to the grid electrode of the MOS tube Mn0 and provides charging and discharging current for the capacitor C1; the drain electrode of the MOS tube Mn0 is connected with an SCL or SDA signal line, and the source electrode of the MOS tube Mn0 is grounded; the positive input end of the comparator CMP is connected with a reference level, and the negative input end of the comparator CMP is connected with an SDA or SCL signal line; the digital control system comprises a feedback loop of a main switch signal Hjen of a hot plug process and a real-time driving signal Hjctrl of an MOS (Metal Oxide Semiconductor) tube of an analog circuit; the output end of the pull-down driving module is connected with the IO interface, the output end of the comparator CMP is connected to the signal detection end of the digital control system, and the Hjctrl signal end of the digital control system is connected to the control end of the pull-down driving module.

The invention provides an MOSFET and a manufacturing method thereof. The MOSFET includes a substrate; the epitaxial layer is arranged on the substrate; the trench gate group comprises a first trench gate and a plurality of second trench gates, the first trench gate extends into the epitaxial layer from the surface of the side, away from the substrate, of the epitaxial layer, the first trench gate extends in the first direction on the plane where the epitaxial layer is located, and the second trench gates are arranged at intervals in the first direction; the orthographic projection of the second trench gate on the substrate is located in the orthographic projection range of the first trench gate on the substrate, the top of the second trench gate is in contact with the bottom of the first trench gate, and a gate layer in the second trench gate is connected with a gate layer in the first trench gate; each shielding region wraps the bottom and all the side walls of the second trench gate and extends towards the surface of the side, away from the substrate, of the epitaxial layer so as to cover the side wall of the first trench gate, and the multiple shielding regions are arranged at intervals. The shielding region has a three-dimensional structure, so that the stress of a trench gate oxide electric field can be reduced, the cell size of the MOSFET can be reduced, and the current density of the MOSFET can be improved.

The invention relates to the technical field of MOS transistors, and discloses a low-power-consumption operation control method, device and equipment of an MOS transistor and a storage medium, and the method comprises the steps: collecting the working state feature data of the MOS transistor; performing change trend analysis on the working state characteristic data to obtain a current power consumption state and a power consumption fluctuation range; executing optimal threshold voltage adjustment parameter calculation based on the current power consumption state and the power consumption fluctuation range to obtain a target threshold voltage value; executing body bias control and grid voltage compensation according to the target threshold voltage value to obtain a body bias voltage control signal and a grid voltage control signal; and the power supply voltage and the working frequency of the MOS transistor are dynamically adjusted according to the body bias voltage and the grid voltage control signal, a voltage frequency working point is obtained, the sudden load change is rapidly responded, meanwhile, all control parameters are accurately adjusted, and the global optimal operation state of the MOS transistor is achieved.

The invention discloses a polarization insensitive filter based on a sub-wavelength grating structure, and belongs to the technical field of integrated photonic devices. The filter comprises an input transition waveguide, a multimode waveguide grating and an output transition waveguide which are connected in sequence. The multimode waveguide grating is composed of a central sub-wavelength grating waveguide and Bragg gratings symmetrically distributed on the two sides, and the effective refractive indexes of TE polarization and TM polarization are equal by adjusting the waveguide width and duty ratio of the central sub-wavelength grating, so that the polarization sensitivity of the device is eliminated fundamentally. And the input / output transition waveguide adopts a transition mode of mixing a tapered waveguide and a sub-wavelength grating waveguide, so that low-loss mode transmission between a straight waveguide and a multimode grating is realized. According to the invention, the anisotropic equivalent medium characteristic of the sub-wavelength grating is utilized, a function of simultaneously and effectively filtering TE and TM polarization is realized, and the filter has the advantages of polarization insensitivity, flexible design, compact structure, simple process and compatibility with a CMOS (Complementary Metal Oxide Semiconductor) process, and has important application value in the fields of optical communication, optical interconnection and the like.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses an MOSFET (metal oxide semiconductor field effect transistor) structure with a nanosheet full-surrounding grid electrode and a manufacturing process thereof, the MOSFET structure comprises a plurality of MOS cells which are arranged in parallel, each MOS cell comprises a drain electrode, a semiconductor epitaxial layer, a grid electrode, a grid oxide layer and a source electrode, the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, an N well layer, a P + layer and a P well layer, the grid electrode comprises a grid electrode covering layer and a grid electrode nanosheet; a plurality of grid nanosheets are arranged in a single MOS cell, are distributed in a horizontal matrix, extend to the inside of the grid covering layer and are in direct contact with the grid covering layer. Through the three-dimensional embedded contact between the nanosheet grids in horizontal matrix distribution and the high-conductivity covering layer, the static control capability of the channel is remarkably enhanced, the grid resistance is reduced, higher current driving density and better switching characteristics are realized, and the physical limitation of a traditional planar device is broken through.

The invention relates to the technical field of semiconductors, and discloses an LDMOS (Laterally Diffused Metal Oxide Semiconductor) device and a preparation method thereof, and the LDMOS device comprises a substrate layer comprising a drift region, a field oxide layer and a gate oxide layer which are located on the surface of the substrate layer, a gate structure, a polycrystalline silicon structure at the side part, a first dielectric layer and a first conductive column, the metal field plate, the second conductive through hole and the field plate connecting structure are arranged at the side part of the gate metal layer; wherein the field oxide layer is located on the surface of the drift region, and the gate structure, the drift region and the field oxide layer between the gate structure and the drift region form a first field plate structure; the metal field plate, the polycrystalline silicon structure and the first dielectric layer therebetween form a first capacitor, the polycrystalline silicon structure, the drift region and the field oxide layer therebetween form a second capacitor, and the first capacitor and the second capacitor are coupled in series to form a second field plate structure; the first field plate structure and the second field plate structure are connected through the field plate connecting structure and the second conductive through hole to form a double-field-plate structure. According to the invention, the breakdown voltage of the device can be improved under the condition of low on-resistance.

A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.

The present invention provides a planar silicon carbide (SiC) metal oxide semiconductor field effect transistor (MOSFET) device and a manufacturing method therefor. Some shallow trenches are arranged based on that a channel current is still parallel to a (0001) crystal plane of a SiC crystal, to further effectively use a crystal plane having a high channel mobility, for example, a (1120) crystal plane, a (1100) crystal plane, or a (0338) crystal plane, of the SiC crystal, thereby effectively reducing channel resistance of the planar SiC MOSFET device. In addition, source regions, well regions, and a channel are formed without protection from an additional ion implanted layer (IMP layer), leading to simple processes.

The invention relates to the technical field of semiconductor manufacturing, and discloses an MOS (Metal Oxide Semiconductor) tube gate forming system adopting a high-K metal gate. A material deposition regulation and control module of the system analyzes the matching degree of deposition uniformity and thickness stability and generates a material deposition control parameter set; an interface processing optimization module adjusts the cavity interface processing balance based on the parameter set, and generates an interface processing optimization parameter set; the gate forming control module adjusts metal gate deposition parameters accordingly, and generates a gate forming regulation and control result; a parameter calibration intervention module dynamically adjusts parameters based on the result, and generates a calibration intervention adjustment data set; and the quality verification promotion module optimizes preparation path parameters according to the parameters and generates a quality verification data table. According to the system, through cooperative work of all the modules, accurate control over the whole preparation process of the MOS transistor grid electrode is achieved, the thickness uniformity, defect control capacity and electrical performance stability of the grid electrode are effectively improved, and the manufacturing requirements of high-precision semiconductor devices are met.

A ferroelectric field effect transistor includes a channel layer, a gate electrode facing the channel layer, a ferroelectric layer provided between the channel layer and the gate electrode, an oxygen-deficient layer provided between the channel layer and the ferroelectric layer, a diffusion barrier layer provided between the channel layer and the oxygen-deficient layer and configured to reduce or prevent oxygen exchange between the channel layer and the oxygen-deficient layer, and a source electrode and a drain electrode, electrically connected to the channel layer, wherein the channel layer and the oxygen-deficient layer include an oxide semiconductor material, and a concentration of oxygen vacancies in the oxygen-deficient layer may be greater than a concentration of oxygen vacancies in the channel layer.

A vertical channel oxide semiconductor field effect transistor and a manufacturing method, relating to the technical field of information materials and devices. In the oxide semiconductor field effect transistor, a trench-shaped oxide semiconductor channel layer is used, the trench is then filled with an oxide semiconductor material, and an oxygen vacancy concentration of a material of an oxide semiconductor filling layer is less than an oxygen vacancy concentration of a material of the oxide semiconductor channel layer; and by using an oxide semiconductor having a low carrier concentration as an internal filling material, a threshold regulation capability of the vertical channel oxide semiconductor field effect transistor can be effectively improved, and the impacts of interface damage and unnecessary doping can be avoided, thereby achieving a vertical channel oxide semiconductor field effect transistor of which a threshold can be accurately regulated.

The invention relates to a structured light illumination confocal super-resolution measurement system and method, and relates to the technical field of optical measurement. The system comprises a digital micromirror device (DMD), a sample platform, an electric displacement platform, a microscopic imaging assembly, a complementary metal oxide semiconductor (CMOS) imaging assembly and computer equipment, and the DMD is used for adjusting the point light source array and the structured light field. According to the DMD-based confocal super-resolution measurement method, a structured light field and a signal-noise separation technology are combined, and high-precision and high-resolution three-dimensional surface reconstruction can be realized. By using the flexibility of the DMD and the advantages of the super-resolution technology, the spatial resolution and speed of confocal imaging are effectively improved, so that the measurement process is more accurate. In addition, low-rank decomposition and self-supervised deep learning methods are fused, the image reconstruction process is optimized, noise interference is suppressed, and the overall performance of the system is further improved.

Provided is a semiconductor device which exhibits favorable electrical properties. This semiconductor device comprises an oxide semiconductor layer, a first insulating layer, a conductive layer having a portion overlapping the oxide semiconductor layer with the first insulating layer interposed therebetween, and a second insulating layer having a portion overlapping the first insulating layer with the oxide semiconductor layer interposed therebetween. The oxide semiconductor layer contains indium. The thermal expansion coefficient of the second insulating layer is less than the thermal expansion coefficient of the oxide semiconductor layer. The first insulating layer has a function of capturing oxygen and hydrogen, and the second insulating layer has a region containing excess oxygen.

A semiconductor die for an inductor-based switching power converter includes a semiconductor layer stack, a first enhancement mode, N-channel metal oxide semiconductor field effect transistor (first NMOS FET) formed in the semiconductor layer stack, a second enhancement mode, N-channel metal oxide semiconductor field effect transistor (second NMOS FET) formed in the semiconductor layer stack, first driver circuitry formed in the semiconductor layer stack, second driver circuitry formed in the semiconductor layer stack, and bootstrap capacitance. The first driver circuitry is configured to drive the first gate from a bootstrap power rail in response to a first control signal, and the second driver circuitry is configured to drive the second gate in response to a second control signal. The bootstrap capacitance includes one or more bootstrap trench capacitors formed in the semiconductor layer stack, and each bootstrap capacitor is electrically coupled between the bootstrap power rail and the switching node.

The invention relates to a method and system for extracting a flicker noise model of a high-voltage MOS device, and the method comprises the steps: designing high-voltage MOS devices of different sizes, and carrying out the measurement to obtain the DC characteristic data of each device in an operable voltage range and the flicker noise characteristic data of each device under different bias voltage conditions; based on the direct-current characteristic data, performing model fitting on the direct-current performance of the high-voltage MOS device to obtain a direct-current characteristic model, the direct-current characteristic model comprising an intrinsic current part and a collision ionization current part; and based on the direct current characteristic model and the flicker noise characteristic data, carrying out model fitting on flicker noise brought by the intrinsic current part and flicker noise brought by the collision ionization current part to obtain a flicker noise model. By fitting the noise source model associated with the magnitude of the collision ionization current, the flicker noise characteristics of the collision ionization current part are subjected to function characterization, and the flicker noise characteristic characterization precision of the high-voltage MOS device under high-voltage bias is improved.

A power inverter is provided. The power inverter includes: first, second and third legs configured to output alternating voltages having different phases. Each the first leg, the second leg, and the third leg includes: a first power metal oxide semiconductor field effect transistor (MOSFET) on a SiC substrate, and connected between a power terminal of direct current voltage and an output terminal configured to output a voltage of a corresponding phase among the first phase, the second phase and the third phase; a second power MOSFET on the SiC substrate, and connected between the output terminal and a ground terminal; and a redundancy circuit including a redundancy power transistor configured to replace the first power MOSFET based on the first power MOSFET failing and replace the second power MOSFET based on the second power MOSFET failing.

The invention discloses a photosensitive pixel unit and an image sensor. The photosensitive pixel unit comprises a semiconductor substrate; a charge accumulation electrode, a transmission control electrode, and a signal readout electrode; the dielectric layer covers the charge accumulation electrode, the transmission control electrode and the signal reading electrode and is provided with an opening part; the N-type semiconductor layer is positioned above the dielectric layer, is in ohmic contact with the signal reading electrode through the opening part, and sequentially comprises a nanocrystalline particle layer, a metal oxide semiconductor thin film layer and an interface layer which is arranged between the nanocrystalline particle layer and the metal oxide semiconductor thin film layer and has two-dimensional electron gas characteristics from bottom to top; the photoelectric conversion layer is located above the N-type semiconductor layer; and the top electrode is positioned above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, the transmission control electrode and the signal reading electrode.

An in / near-sensor artificial intelligence (AI) architecture that facilitates knowledge inference at a source of data, wherein the architecture comprises a three-dimensional (3D) stacked complementary metal-oxide-semiconductor (CMOS) image sensor that comprises a multi-layer computational structure that enables AI-based knowledge inference before readout electronics. The multi-layer computational structure comprises a hierarchical attention-oriented region-based processing (HARP) module that is configured between a processing unit and readout circuitry that is coupled to an image sensor.

Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.

The invention relates to a high-side power NMOS (N-channel Metal Oxide Semiconductor) gate drive circuit in synchronous rectification buck. The high-side power NMOS gate drive circuit comprises a high-voltage storage circuit, a gate charge discharge circuit, a gate voltage control capacitor C2, a level shift circuit and a logic control circuit. The high-voltage storage circuit stores an input voltage VIN on a capacitor C1 and is used for shortening the conduction delay of a high-side power tube MLD1; when the low-side power tube MLD2 is conducted, the gate charge leakage circuit MN1 realizes complete turn-off of the tube MLD1, and prevents the high-side power tube MLD1 and the low-side power tube MLD2 from being conducted at the same time; the grid voltage controls the capacitor C2 to turn on and turn off the MN1 tube under the floating potential. The logic control circuit controls the conduction of the MLD1 and the MLD2 through a first signal SWH and a second signal SWL of the PWM generator, so that the conduction delay is further shortened; the level shift circuit converts a low level into a high level based on VIN so as to prevent the MOS tube from being broken down.

The invention provides an image sensor pixel unit with a polarization response characteristic light trapping structure and a preparation method of the image sensor pixel unit. The image sensor pixel unit comprises a semiconductor substrate, a multi-layer structure arranged on the substrate and a polarization response unit. The multi-layer structure comprises an anti-reflection layer, a filling and leveling layer and a micro-lens layer. The polarization response unit adopts an all-dielectric sub-wavelength grating based on a backscattering technology, and the polarization response unit and the deep trench isolation structure are synchronously formed by adopting the same process, so that photoelectric isolation between pixels is realized, and a polarization selection function is also realized. The anti-reflection layer is a multi-layer dielectric film stack, and interface reflection is effectively restrained. By optimizing the design of a polarization selection-transmission-convergence cooperative structure, polarization selection and light enhancement functions are integrated, an all-dielectric material system is adopted to be completely compatible with a CMOS (complementary metal oxide semiconductor) process, and quantum efficiency is remarkably improved while high-efficiency polarization detection is realized.

The invention provides a gate-source short-circuit SiC MOS device failure analysis method and related equipment, and the method comprises the steps: responding to the determination that the functional characteristics of a source and a drain have no abnormal conditions, carrying out the analysis of the cause of a short-circuit fault of a gate and the source based on the characteristics of a silicon carbide material and an MOS device failure mechanism, and carrying out the analysis of the short-circuit fault of the gate and the source. Comprising the following steps: judging whether gate source chemical lap joint caused by internal water vapor exists or not through a dry chip; unsealing the chip to expose the interior of the chip, testing the chip, and judging whether a metallization layer migration short circuit caused by high temperature occurs or not; analyzing whether breakdown caused by high electric field stress exists in the gate oxide layer; according to the failure analysis method provided by the invention, the reason of the failure of the SiC MOS device can be accurately analyzed, and the problem that the microdefect of the SiC MOS device cannot be positioned by a traditional means is solved.

In a semiconductor device including an oxide semiconductor film, a semiconductor device including a transistor with excellent electric characteristics is provided. The present invention is a semiconductor device including a glass substrate and a channel-etching transistor. The channel-etching transistor includes a gate electrode, a first insulating film, a second insulating film, an oxide semiconductor film, a source electrode, a drain electrode, a third insulating film, a pixel electrode, and a conductive film containing copper. The source electrode and the drain electrode each include a first conductive film, a second conductive film provided over and in contact with the first conductive film, and a third conductive film provided over and in contact with the second conductive film. The second conductive film contains a first element, the first conductive film and the third conductive film contain the same second element, and the oxide semiconductor film contains indium, gallium, and zinc.

The present disclosure describes a semiconductor device assembly including a first wafer having complementary metal oxide semiconductor (CMOS) devices including a plurality of string drivers, where each of the plurality of string drivers includes a field effect transistor (FET), a global word line connected to a source of the FET, and a local word line vertically passing through the FET; and a second wafer having a memory array including a plurality of word lines, each of the word lines connected to a corresponding one of the string drivers of the first wafer through a local word line of the corresponding one of the string drivers, wherein the backside surface of the first wafer is bonded to the front side surface of the second wafer to form a wafer stack WOW bond.

An apparatus comprising a pair of inverters configured in a cross-coupled configuration, wherein an inverter of the pair of inverters comprises a static random-access memory (SRAM) physically unclonable function (PUF) circuit, wherein the SRAM PUF circuit comprises an inverter; and an inverter cell comprising a p-channel metal-oxide-semiconductor (PMOS) transistor, an n-channel metal-oxide-semiconductor (NMOS) transistor, and output node, and a control signal input, wherein: (i) the PMOS transistor comprises (a) a drain terminal that is coupled to an output and (b) a source terminal that is coupled to a supply voltage, (ii) the NMOS transistor comprises a gate terminal that is coupled to a gate of the PMOS transistor that inhibits a path between the supply voltage and ground, and (iii) responsive to a low state provided to the control signal input, the control signal input causes the PMOS transistor to charge the output node to the supply voltage.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory.SOLUTION: Thin film transistor integrated circuits such as an LSI, a CPU, and a memory are manufactured using semiconductors whose channel regions are formed using semiconductors which are intrinsic or substantially intrinsic by removal of an impurity which serves as an electronic donor (donor) and whose energy gap is larger than that of silicon semiconductors. With the use of the thin film transistor, power consumption due to leakage current can be reduced.SELECTED DRAWING: Figure 1

A semiconductor device with little characteristic variation is provided. A transistor includes an oxide semiconductor; a first conductor and a second conductor over the oxide semiconductor; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator that is positioned over the first insulator and the second insulator and provided with a first opening overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned over the oxide semiconductor and between the first conductor and the second conductor; and a third conductor over the fourth insulator. A capacitor includes the second conductor; the third insulator provided with a second opening reaching the second conductor; a fifth insulator positioned inside the second opening; and a fourth conductor over the fifth insulator. A plug is positioned to penetrate the first insulator, the third insulator, the first conductor, and the oxide semiconductor. The plug is electrically connected to the first conductor. The first insulator and the second insulator are each formed using a metal oxide including an amorphous structure.

A memory device that can be miniaturized or highly integrated can be provided. The memory device includes a memory cell, a first insulator, and a second insulator. The memory cell includes a capacitor and a transistor over the capacitor. The capacitor includes a second conductor, a third insulator over the second conductor, and a third conductor over the third insulator. Part of the second conductor, part of the third insulator, and part of the third conductor are placed in an opening portion formed in the first insulator. The transistor includes the third conductor, a fourth conductor over the second insulator, an oxide semiconductor, a fourth insulator over the oxide semiconductor, and a fifth conductor over the fourth insulator. Part of the oxide semiconductor is placed in an opening portion formed in the second insulator and the fourth conductor. The oxide semiconductor includes a region in contact with a top surface of the third conductor, a region in contact with a side surface of the fourth conductor, and a region in contact with part of a top surface of the fourth conductor. The oxide semiconductor has a stacked-layer structure.