1460 results about "Oxide semiconductor" patented technology

A ferroelectric field effect transistor includes a channel layer, a gate electrode facing the channel layer, a ferroelectric layer provided between the channel layer and the gate electrode, an oxygen-deficient layer provided between the channel layer and the ferroelectric layer, a diffusion barrier layer provided between the channel layer and the oxygen-deficient layer and configured to reduce or prevent oxygen exchange between the channel layer and the oxygen-deficient layer, and a source electrode and a drain electrode, electrically connected to the channel layer, wherein the channel layer and the oxygen-deficient layer include an oxide semiconductor material, and a concentration of oxygen vacancies in the oxygen-deficient layer may be greater than a concentration of oxygen vacancies in the channel layer.

A vertical channel oxide semiconductor field effect transistor and a manufacturing method, relating to the technical field of information materials and devices. In the oxide semiconductor field effect transistor, a trench-shaped oxide semiconductor channel layer is used, the trench is then filled with an oxide semiconductor material, and an oxygen vacancy concentration of a material of an oxide semiconductor filling layer is less than an oxygen vacancy concentration of a material of the oxide semiconductor channel layer; and by using an oxide semiconductor having a low carrier concentration as an internal filling material, a threshold regulation capability of the vertical channel oxide semiconductor field effect transistor can be effectively improved, and the impacts of interface damage and unnecessary doping can be avoided, thereby achieving a vertical channel oxide semiconductor field effect transistor of which a threshold can be accurately regulated.

The invention relates to a structured light illumination confocal super-resolution measurement system and method, and relates to the technical field of optical measurement. The system comprises a digital micromirror device (DMD), a sample platform, an electric displacement platform, a microscopic imaging assembly, a complementary metal oxide semiconductor (CMOS) imaging assembly and computer equipment, and the DMD is used for adjusting the point light source array and the structured light field. According to the DMD-based confocal super-resolution measurement method, a structured light field and a signal-noise separation technology are combined, and high-precision and high-resolution three-dimensional surface reconstruction can be realized. By using the flexibility of the DMD and the advantages of the super-resolution technology, the spatial resolution and speed of confocal imaging are effectively improved, so that the measurement process is more accurate. In addition, low-rank decomposition and self-supervised deep learning methods are fused, the image reconstruction process is optimized, noise interference is suppressed, and the overall performance of the system is further improved.

The invention discloses a photosensitive pixel unit and an image sensor. The photosensitive pixel unit comprises a semiconductor substrate; a charge accumulation electrode, a transmission control electrode, and a signal readout electrode; the dielectric layer covers the charge accumulation electrode, the transmission control electrode and the signal reading electrode and is provided with an opening part; the N-type semiconductor layer is positioned above the dielectric layer, is in ohmic contact with the signal reading electrode through the opening part, and sequentially comprises a nanocrystalline particle layer, a metal oxide semiconductor thin film layer and an interface layer which is arranged between the nanocrystalline particle layer and the metal oxide semiconductor thin film layer and has two-dimensional electron gas characteristics from bottom to top; the photoelectric conversion layer is located above the N-type semiconductor layer; and the top electrode is positioned above the photoelectric conversion layer and is arranged opposite to the charge accumulation electrode, the transmission control electrode and the signal reading electrode.

Various embodiments of solid state transducer (“SST”) devices are disclosed. In several embodiments, a light emitter device includes a metal-oxide-semiconductor (MOS) capacitor, an active region operably coupled to the MOS capacitor, and a bulk semiconductor material operably coupled to the active region. The active region can include at least one quantum well configured to store first charge carriers under a first bias. The bulk semiconductor material is arranged to provide second charge carriers to the active region under the second bias such that the active region emits UV light.

The invention relates to a high-side power NMOS (N-channel Metal Oxide Semiconductor) gate drive circuit in synchronous rectification buck. The high-side power NMOS gate drive circuit comprises a high-voltage storage circuit, a gate charge discharge circuit, a gate voltage control capacitor C2, a level shift circuit and a logic control circuit. The high-voltage storage circuit stores an input voltage VIN on a capacitor C1 and is used for shortening the conduction delay of a high-side power tube MLD1; when the low-side power tube MLD2 is conducted, the gate charge leakage circuit MN1 realizes complete turn-off of the tube MLD1, and prevents the high-side power tube MLD1 and the low-side power tube MLD2 from being conducted at the same time; the grid voltage controls the capacitor C2 to turn on and turn off the MN1 tube under the floating potential. The logic control circuit controls the conduction of the MLD1 and the MLD2 through a first signal SWH and a second signal SWL of the PWM generator, so that the conduction delay is further shortened; the level shift circuit converts a low level into a high level based on VIN so as to prevent the MOS tube from being broken down.

The invention provides an image sensor pixel unit with a polarization response characteristic light trapping structure and a preparation method of the image sensor pixel unit. The image sensor pixel unit comprises a semiconductor substrate, a multi-layer structure arranged on the substrate and a polarization response unit. The multi-layer structure comprises an anti-reflection layer, a filling and leveling layer and a micro-lens layer. The polarization response unit adopts an all-dielectric sub-wavelength grating based on a backscattering technology, and the polarization response unit and the deep trench isolation structure are synchronously formed by adopting the same process, so that photoelectric isolation between pixels is realized, and a polarization selection function is also realized. The anti-reflection layer is a multi-layer dielectric film stack, and interface reflection is effectively restrained. By optimizing the design of a polarization selection-transmission-convergence cooperative structure, polarization selection and light enhancement functions are integrated, an all-dielectric material system is adopted to be completely compatible with a CMOS (complementary metal oxide semiconductor) process, and quantum efficiency is remarkably improved while high-efficiency polarization detection is realized.

In a semiconductor device including an oxide semiconductor film, a semiconductor device including a transistor with excellent electric characteristics is provided. The present invention is a semiconductor device including a glass substrate and a channel-etching transistor. The channel-etching transistor includes a gate electrode, a first insulating film, a second insulating film, an oxide semiconductor film, a source electrode, a drain electrode, a third insulating film, a pixel electrode, and a conductive film containing copper. The source electrode and the drain electrode each include a first conductive film, a second conductive film provided over and in contact with the first conductive film, and a third conductive film provided over and in contact with the second conductive film. The second conductive film contains a first element, the first conductive film and the third conductive film contain the same second element, and the oxide semiconductor film contains indium, gallium, and zinc.

An apparatus comprising a pair of inverters configured in a cross-coupled configuration, wherein an inverter of the pair of inverters comprises a static random-access memory (SRAM) physically unclonable function (PUF) circuit, wherein the SRAM PUF circuit comprises an inverter; and an inverter cell comprising a p-channel metal-oxide-semiconductor (PMOS) transistor, an n-channel metal-oxide-semiconductor (NMOS) transistor, and output node, and a control signal input, wherein: (i) the PMOS transistor comprises (a) a drain terminal that is coupled to an output and (b) a source terminal that is coupled to a supply voltage, (ii) the NMOS transistor comprises a gate terminal that is coupled to a gate of the PMOS transistor that inhibits a path between the supply voltage and ground, and (iii) responsive to a low state provided to the control signal input, the control signal input causes the PMOS transistor to charge the output node to the supply voltage.

An object is to reduce leakage current and parasitic capacitance of a transistor used for an LSI, a CPU, or a memory.SOLUTION: Thin film transistor integrated circuits such as an LSI, a CPU, and a memory are manufactured using semiconductors whose channel regions are formed using semiconductors which are intrinsic or substantially intrinsic by removal of an impurity which serves as an electronic donor (donor) and whose energy gap is larger than that of silicon semiconductors. With the use of the thin film transistor, power consumption due to leakage current can be reduced.SELECTED DRAWING: Figure 1

A semiconductor device with little characteristic variation is provided. A transistor includes an oxide semiconductor; a first conductor and a second conductor over the oxide semiconductor; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator that is positioned over the first insulator and the second insulator and provided with a first opening overlapping with a region between the first conductor and the second conductor; a fourth insulator positioned over the oxide semiconductor and between the first conductor and the second conductor; and a third conductor over the fourth insulator. A capacitor includes the second conductor; the third insulator provided with a second opening reaching the second conductor; a fifth insulator positioned inside the second opening; and a fourth conductor over the fifth insulator. A plug is positioned to penetrate the first insulator, the third insulator, the first conductor, and the oxide semiconductor. The plug is electrically connected to the first conductor. The first insulator and the second insulator are each formed using a metal oxide including an amorphous structure.

A memory device that can be miniaturized or highly integrated can be provided. The memory device includes a memory cell, a first insulator, and a second insulator. The memory cell includes a capacitor and a transistor over the capacitor. The capacitor includes a second conductor, a third insulator over the second conductor, and a third conductor over the third insulator. Part of the second conductor, part of the third insulator, and part of the third conductor are placed in an opening portion formed in the first insulator. The transistor includes the third conductor, a fourth conductor over the second insulator, an oxide semiconductor, a fourth insulator over the oxide semiconductor, and a fifth conductor over the fourth insulator. Part of the oxide semiconductor is placed in an opening portion formed in the second insulator and the fourth conductor. The oxide semiconductor includes a region in contact with a top surface of the third conductor, a region in contact with a side surface of the fourth conductor, and a region in contact with part of a top surface of the fourth conductor. The oxide semiconductor has a stacked-layer structure.

The inventive concepts provide a bidirectional switching converter including a first power metal oxide semiconductor field effect transistor (MOSFET) connecting an input voltage node to a switching node, a second power MOSFET connecting the switching node to a ground node, and a zero current detection (ZCD) auto-calibration circuit configured to perform one of an operation of generating a first offset for varying a turn-on time of the first power MOSFET according to an operation mode and an operation of generating a second offset for varying a turn-on time of the second power MOSFET according to the operation mode.

The invention discloses a positive electrode photocatalytic material for a solid-state battery, a preparation method of the positive electrode photocatalytic material, a battery positive electrode and the solid-state battery. The positive electrode photocatalytic material comprises a one-dimensional semiconductor nano array composite structure containing vacancies / defects, the one-dimensional semiconductor nano array composite structure comprises an oxide semiconductor nano array structure containing oxygen vacancies / defects or a sulfide semiconductor nano array structure containing sulfur vacancies / defects; the multi-element alloy nano-particles are binary alloy particles and / or high-entropy alloy particles with more than three elements, and the sizes of the binary alloy particles and / or the high-entropy alloy particles are in sub-nanometer and nanometer scale ranges; and the multi-element alloy nano particles are assembled on the one-dimensional semiconductor nano array composite structure. According to the invention, the photocatalytic characteristic of the low-dimensional semiconductor nano array structure is coupled with the plasmon effect of the multi-component alloy nano particles, so that the wide-spectrum strong absorption of sunlight and the efficient light-heat-electric energy synergistic conversion are realized.

The invention discloses a preparation method of an LDMOS (Laterally Diffused Metal Oxide Semiconductor) and an LDMOS device, and the preparation method of the LDMOS comprises the steps: providing a semiconductor substrate, and forming an LDMOS device region on the semiconductor substrate; forming an oxide layer on the region where the LDMOS device is formed; forming a grid electrode on the oxidation layer corresponding to the area between the source electrode area and the drain electrode area, and forming a step-shaped field plate structure on the corresponding oxidation layer above the drift area; forming a first dielectric layer covering the grid electrode and the stepped field plate structure; forming a first through hole and a second through hole which are respectively communicated to the source region and the drain region in the first dielectric layer, and forming a plurality of third through holes which are respectively communicated to different steps of the stepped field plate structure; the at least one third through hole electrically connects a step of the stepped field plate structure with the drain region. By adopting the method, the drain-source breakdown voltage performance of the device in a conducting state is improved, and the high-voltage breakdown of the drain electrode is effectively prevented.

An active matrix substrate includes a plurality of gate bus lines, a plurality of source bus lines located closer to the substrate side; a lower insulating layer that covers the source bus lines; an interlayer insulating layer that covers the gate bus lines; a plurality of oxide semiconductor TFTs disposed in association with respective pixel regions; a pixel electrode disposed in each of the pixel regions; and a plurality of source contact portions each of which electrically connects one of the oxide semiconductor TFTs to the corresponding one of the source bus lines, in which each of the oxide semiconductor TFTs includes an oxide semiconductor layer disposed on the lower insulating layer, a gate electrode disposed on a portion of the oxide semiconductor layer, and a source electrode formed of a conductive film, and each of the source contact portions includes a source contact hole, and a connection electrode.

The present application relates to a metal oxide semiconductor field effect transistor and a manufacturing method therefor. The metal oxide semiconductor field effect transistor comprises: a source region (142) having a first conductivity type; a drift region (130) having the first conductivity type; a first well region (120) having the first conductivity type, and located below the drift region (130) and connected to the drift region (130); a drain trench structure extending downward from the drift region (130) into the first well region (120), the drain trench structure comprising an insulating dielectric layer (145) located on a sidewall of a first trench, and a conductive material (146) located in the first trench and laterally surrounded by the insulating dielectric layer (145), and at least a portion of the drift region (130) being located between the source region (142) and the drain trench structure; and a gate (152) located on the drift region (130).

Disclosed in the embodiments of the present application are a display panel and a display device. In a display light-transmitting region, among at least two light-emitting devices electrically connected to the same pixel circuit, the two light-emitting devices are connected by means of a wire; and the wire comprises a light-transmitting conductive trace, the light-transmitting conductive trace is disposed in the same layer as a metal oxide semiconductor layer in the pixel circuit, and the light-transmitting conductive trace comprises at least one of materials of the metal oxide semiconductor layer.

The utility model provides an SRAM (Static Random Access Memory) unit, an SRAM circuit and a memory, comprising ten MOS (Metal Oxide Semiconductor) tubes, namely M1, M2, M3, M4, M5, M6, M7, M8, M9 and M10; m1, M3, M5, M6, M7, M8 and M10 are NMOS (N-channel Metal Oxide Semiconductor), and M2, M4 and M9 are PMOS (P-channel Metal Oxide Semiconductor). The SRAM cell may be referred to as a 10T SRAM. The 10T SRAM is obtained by adding four MOS (Metal Oxide Semiconductor) tubes on the basis of the existing 6T SRAM. When the 10T SRAM reads and writes data, the 10T SRAM is similar to an 8T SRAM, and the read-write speed of the 10T SRAM is slightly slower than that of the 8T SRAM, but is higher than that of a 6T SRAM. After the 10T SRAM is combined, the 10T SRAM can be directly used for copying the data, an ALU is not needed when the data is copied, and the speed of copying the data is obviously improved.

The present application relates to a semiconductor device and a semiconductor memory device. The semiconductor device of an embodiment includes an oxide semiconductor layer; a gate electrode; a gate insulating layer; a first electrode and a second electrode electrically connected to the oxide semiconductor layer; a first conductive layer provided at at least one of a position between the oxide semiconductor layer and the first electrode and a position between the oxide semiconductor layer and the second electrode, containing at least one metal element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen (N), and including a first portion and a second portion, the first portion having a higher atomic concentration of the metal element than an atomic concentration of aluminum in the first portion, and the second portion having a higher atomic concentration of aluminum than an atomic concentration of the metal element in the second portion; and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer.

The invention relates to the technical field of integrated circuits, and discloses a substrate bias effect resistant CMOS electronic relay control method and system. The method comprises the following steps: constructing an electronic relay circuit by adopting a P-type substrate high-voltage CMOS (Complementary Metal-Oxide-Semiconductor Transistor) process, and connecting a P-type substrate with a negative power supply Vss; the tube body end of the input-stage PMOS is in short circuit with a source electrode and is connected with an intermediate voltage source, and the substrate bias effect is eliminated by using the isolation characteristic; the NMOS tube adopts an asymmetric isolation structure, a body end and a source electrode are short-circuited and connected with a grounding end, and electrical isolation is realized through an N buried layer; the body source short circuit configuration enables the threshold voltage of the input end to be stabilized at the intermediate value between the intermediate voltage source and the grounding end, and does not drift along with the change of the positive power supply Vdd. According to the invention, the problem that the input threshold voltage is unstable due to the substrate bias effect of the PMOS transistor in the existing N-type substrate electronic relay technology is solved, and the control precision and reliability of the electronic relay under different working voltage conditions are improved.

To provide a semiconductor device with a configuration that can sufficiently reduce parasitic capacitance between wirings. This will be one of the issues to address. [Solution] A stack of a first layer in which part or all of a metal thin film is oxidized and an oxide semiconductor layer is formed. In the thin-film transistor with a bottom gate structure used, the oxide semiconductor overlaps with the gate electrode layer. An oxide insulating layer is formed on a part of the body layer to serve as a channel protective layer, and when the insulating layer is formed... An oxide insulating layer is formed to cover the peripheral edges (including the sides) of the stacked oxide semiconductor layers.

The invention belongs to the field of metal oxide semiconductor-gas sensing, and particularly relates to a Ni < x > Fe < 2-x > O semiconductor gas-sensitive material with asymmetric defects, a preparation method and application, the sensing material is characterized in that Ni is doped in a Fe2O3 framework to form a Ni < x > Fe < 2-x > O bimetallic oxide rich in Ni-Ov-Fe asymmetric defects, Ni is used as a main active site for adsorbing and catalyzing NO2, and the Ni is used as a main active site for adsorbing and catalyzing NO2. And with the mutual reaction with active oxygen on asymmetric defects on the surface of the material, the sensing performance on NO2 is improved. The Ni < x > Fe < 2-x > O sensing material is prepared through a hydrothermal-calcination method, the interaction between Ni element and other atoms in a Fe2O3 frame is remarkable, and the electron transmission capacity is improved. The material is clear in labor division in the NO2 sensing process, NO2 and O2 have respective adsorption activation sites, then reaction is carried out, excellent NO2 sensing response performance and extremely low detection limit (200 ppb) are shown, and a good foundation is laid for development of novel metal oxide semiconductors.

Even if the power supply voltage is cut off, the connections between logic circuit sections, or within each logic circuit section To provide a semiconductor device that can maintain its circuit configuration. Also, to change the connection relationships between logic circuit sections, This invention provides a semiconductor device that allows for high-speed modification of the circuit configuration within each logic circuit section. [Solution] In a reconfigurable circuit, a semiconductor that stores data such as circuit configuration and connection relationships. Oxide semiconductors are used for the body elements. In particular, oxide semiconductors are used in the channel formation region of the semiconductor element. It is being used.

The present disclosure relates to semiconductor structures and, more particularly, to an extended drain metal oxide semiconductor device and methods of manufacture. The structure includes: a gate structure including a gate dielectric material and a gate electrode with a stepped feature; sidewall spacers on sidewalls of the gate electrode, the sidewall spacers including a notched feature adjacent to the gate electrode; and a silicide contact on a surface of the gate electrode, the silicide contact being free of breaks on the surface of the gate electrode.

A semiconductor device having at least a crystalline oxide semiconductor layer, characterized in that the crystalline oxide semiconductor layer has a band gap of 3 eV or more and a field-effect mobility of 30 cm 2 / V·s or more.

This invention provides a modeling method for metal-oxide-semiconductor semiconductors, comprising: establishing an initial sub-circuit simulation model, as follows: where Y_MF is the multi-interdigitation effect correction parameter, NF is the interdigitation index of the gate of the MOS device, and X... nf0 A, X nf1 B, X nf2 C, X nf3 D, X nf4 E, X nf5 F and W are both fitting parameters, W is the channel width, L is the channel length, and X is the channel length. nf6 To obtain the fitting parameters, multiple measured electrical characteristic parameters of metal-oxide-semiconductor semiconductors under different interdigitation indices, different channel widths, and different channel lengths are obtained. The fitting parameters are adjusted so that the errors of the multi-interdigitation effect correction parameters obtained from simulations under different interdigitation indices, different channel widths, and different channel lengths are all within the set values. The corresponding fitting parameter values ​​are then determined. The following multi-interdigitation effect model is established: Y = K + Y_MF.

To suppress the decrease in channel resistance of semiconductor devices using oxide semiconductors. [Solution] A method for manufacturing a semiconductor device includes forming an oxide semiconductor layer on a first insulating layer, forming a second insulating layer on the oxide semiconductor layer, forming a conductive layer on the second insulating layer, forming a resist mask on the second insulating layer and the conductive layer having openings that overlap with at least a portion of the oxide semiconductor layer, and using the resist mask to inject impurities into the oxide semiconductor layer through the second insulating layer.

The application provides an integrated circuit, comprising: a first metal oxide semiconductor field effect transistor (FET), wherein a first effective gate and a second effective gate are arranged in the first FET, and a first redundant gate is arranged between the first effective gate and the second effective gate; the first effective gate, the second effective gate and the first redundant gate surround a first channel; the first effective gate and the second effective gate are connected to a gate end of the first FET; the first channel on both sides of the first effective gate and the first channel on both sides of the second effective gate are respectively connected to a source end and a drain end of the first FET; and the first redundant gate is connected to a redundant potential or is suspended. Through the structure of the redundant gate arranged between the two effective gates, the current density of the GAA tube can be reduced, and the heat dissipation performance of the GAA tube is further improved.

In accordance with at least one example of the description, a method comprises forming a substrate, and forming transducer elements over the substrate, each transducer element including a ferroelectric capacitor and a conductive element spaced from the ferroelectric capacitor by a dielectric material, the ferroelectric capacitor being between the conductive element and the substrate.