6200 results about "Oxide semiconductor" patented technology

The invention relates to the technical field of sensor detection, and discloses a detection method and device based on a multi-mode gas sensor, and the method comprises the following steps: carrying out blending processing on a metal oxide semiconductor and a conductive material to obtain a bimodal nano composite material, and creating a multi-mode gas detection module, the preprocessed multi-mode signal data is acquired and obtained; acquiring and analyzing data of the temperature sensor and the humidity sensor to obtain environmental factor compensation parameters; performing adaptive calibration processing on the preprocessed multi-modal signal data according to the environmental factor compensation parameters to obtain calibrated multi-modal signal data; constructing a multi-input neural network model based on the calibrated multi-modal signal data, and training to obtain a gas recognition model; multi-mode signals collected and calibrated in real time are analyzed and judged based on the gas recognition model, gas type and concentration information is obtained, and high-precision and high-reliability gas detection is achieved.

An integrated structure for an optoelectronic device and a method of fabricating an integrated structure for an optoelectronic device. The method comprises the steps of forming a plurality of epitaxial layers for optical elements on an epitaxial growth substrate, wherein the epitaxial layers are based on a material system different from complementary metal-oxide-semiconductor, CMOS; providing a handle wafer; performing a first dielectric bonding between the epitaxial growth substrate and the handle wafer such that an order of the epitaxial layers for the optical elements is reversed on the handle wafer compared to on the epitaxial growth substrate; removing the epitaxial growth substrate to expose one of the epitaxial layers on the handle wafer; processing the exposed one of the epitaxial layers for providing a common electrode layer for a first contact of each of the optical elements in the optoelectronic device; providing a CMOS integrated circuit, IC, wafer comprising a driver circuit for the optoelectronic device; and performing a second dielectric bonding between the handle wafer and the IC wafer such that an order of the epitaxial layers for the optical elements is reversed on the IC wafer compared to on the handle wafer.

The invention discloses a control circuit of an electronic load, the electronic load and a power supply test system. The circuit comprises an MCU; the signal output end of the MCU is connected with the input end of the DAC module; the closed-loop control circuit comprises a first error amplifier, a mutual inductor, an MOS (Metal Oxide Semiconductor) tube, a current sampling resistor and a power supply end VBUS; a mutual inductor is arranged between a first error amplifier and an MOS tube of the closed-loop control circuit, a power supply end VBUS is connected with a drain electrode of the MOS tube through a primary side of the mutual inductor, a first secondary side of the mutual inductor feeds back an input signal of the first error amplifier, and a second secondary side of the mutual inductor feeds back a driving signal of the first error amplifier to the MOS tube. According to the invention, the dynamic response speed when the electronic load pulls the high-frequency current can be improved, and the test requirements of high precision and high dynamic response are met.

To provide: a transistor with favorable electrical characteristics; a transistor with a high on-state current; a transistor with low parasitic capacitance; or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated.SOLUTION: There is provided a transistor including an oxide semiconductor layer, a semiconductor device, or a memory device. The oxide semiconductor layer includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron microscope, bright spots arranged in a layered manner in a direction parallel to the surface on which the oxide semiconductor layer is to be formed are observed in each of the first region, the second region, and the third region.SELECTED DRAWING: Figure 1

The invention provides a low-on-resistance trench gate silicon carbide VDMOS and a preparation method thereof, and the method comprises the steps: depositing metal on the lower side surface of a silicon carbide substrate, and forming a drain metal layer; epitaxially growing on the upper side surface of the silicon carbide substrate to form a drift layer; performing ion implantation to form a low-resistance region; forming a barrier layer, etching, performing ion implantation, and forming a P + well region, a P-type well region and an N-type source region; a barrier layer is formed again, and the insulating medium is etched and deposited; forming a barrier layer again, etching and depositing metal, and forming a suspension gate; forming a barrier layer again, etching the barrier layer, and depositing to form an insulating medium layer; forming a barrier layer again, etching and depositing metal, and forming a gate metal layer; the barrier layer is re-formed, the barrier layer is etched to form a through hole, the drift layer is etched to the upper side face of the P-type well region, metal is deposited, a source electrode metal layer is formed, the barrier layer is removed, preparation is completed, gate-drain capacitance is reduced, the switching speed of the device is increased, and switching loss is reduced.

An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

The invention provides a temperature compensation method and device for a silicon carbide MOS drive control chip, and the method comprises the steps: obtaining a junction temperature-electrical parameter set of a silicon carbide MOS, and carrying out the thermoelectric coupling simulation modeling processing of a junction temperature-electrical parameter mapping data set, and obtaining three-dimensional temperature-efficiency characteristic data; performing real-time parameter analysis and dynamic execution on the three-dimensional temperature-efficiency characteristic data to obtain an optimized switching characteristic waveform; extracting the optimized switching characteristic waveform frequency domain characteristics, and generating a dynamic frequency modulation parameter; and performing dead time iterative optimization on the dynamic frequency modulation parameters to obtain a control parameter combination of the silicon carbide MOS.

The invention discloses an irradiation-reinforced SiC super-junction MOS (Metal Oxide Semiconductor) structure and a preparation process thereof, and belongs to the technical field of MOS semiconductors. Comprising a drain electrode, a semiconductor epitaxial layer, a source electrode and a grid electrode; the semiconductor epitaxial layer comprises an N substrate layer, an N drift layer, a P + layer, an N well layer and a P well layer; by arranging the lightly doped N layer in the middle of the N drift layer and arranging the laterally symmetrical trapezoidal P-layers on the two sides of the N drift layer, the device can interact with electrons in the N drift layer, accelerate carrier recombination, reduce the influence of redundant carriers on the performance of the device, effectively reduce the performance degradation caused by irradiation, and improve the performance of the device. According to the invention, the concave heavily-doped N layer is formed at the bottom end of the lightly-doped N layer, so that the carrier concentration of the region can be greatly improved, and the conductivity is remarkably enhanced.

The invention discloses a scene self-adaptive aging test method and system for an extra-high voltage MOS (Metal Oxide Semiconductor), and relates to the related technical field of MOS test, and the method comprises the steps: building a device aging test platform; performing test condition analysis on the application scene information of the target extra-high voltage MOS device; performing pretest adjustment on the target extra-high voltage MOS device, and determining an aging test update parameter table; performing aging test monitoring on the target extra-high voltage MOS device; and calling an extra-high voltage MOS aging adaptive evaluator to process and evaluate the device aging scene test data stream set to obtain a device scene aging performance test result. The technical problems that in the prior art, due to the fact that an MOS aging test lacks scene adaptability, the aging process of the MOS device in the actual application environment is difficult to accurately simulate, the test pertinence is insufficient, and the result accuracy is poor are solved, and the technical effect of improving the MOS device aging test pertinence and the result accuracy is achieved.

The disclosure relates to a π type trench gate silicon carbide MOSFET device and a fabrication method thereof. To protect a trench gate oxide layer without increasing a channel resistance and process complexity, a second conductivity type of heavily doped deep well inserted with double gate trenches along the sidewalls of deep well is designed. The deep well is connected to the source metal directly. The electric potential is clamped to the source during the voltage blocking and turn-off state, which reduces the electric field in the gate oxide and reduces the miller capacitance. An interlayer dielectric layer is deposited above the conductive dielectric polysilicon layers and extends outward separately to cover a part of the source region. A smaller cell pitch can be achieved by controlling the spacing between the first and the second trench gate, thereby increasing the channel density and reducing the channel resistance.

The invention relates to the technical field of MOS (Metal Oxide Semiconductor) semiconductors, and discloses a double-gate structure for a high-performance MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and an optimization method, the double-gate structure comprises a plurality of MOS cells, and each MOS cell comprises a drain electrode, a source electrode, a gate electrode, a gate oxide layer and a semiconductor epitaxial layer; the semiconductor epitaxial layer comprises an N substrate layer, an N diffusion layer, a P-layer, a P well layer and an N well layer, two grid electrodes are arranged in a single MOS cell and are respectively positioned on the left side and the right side in a grid oxide layer, and the section outline of the grid oxide layer is semicircular; polycrystalline silicon is arranged in the gate oxide layer and located between the two grid electrodes, and the polycrystalline silicon is in ohmic contact with the source electrode. Through the double-gate structure, geometric shape optimization, doping layer design and process innovation, the switching speed, the voltage endurance capability, the thermal stability and the integration degree of the MOSFET are remarkably improved, meanwhile, the leakage current and the on-resistance are reduced, and the MOSFET is suitable for high-performance power devices and high-frequency application scenes.

The invention discloses an unmanned aerial vehicle edge intelligent analysis terminal based on a single Beidou, and relates to the technical field of satellite navigation and unmanned aerial vehicles, and the terminal comprises an edge calculation unit which is in communication connection with a high-definition image collection module, a high-precision positioning module, a Beidou short message communication module and a ground control station; the high-definition image acquisition module is used for acquiring high-definition image data through a CMOS (Complementary Metal Oxide Semiconductor) sensor; the high-precision positioning module is used for acquiring centimeter-level positioning data in the flight process of the unmanned aerial vehicle through an RTK technology and an INS system; the edge calculation unit is used for carrying out target recognition through a lightweight convolutional neural network in combination with a YOLOv5 target detection algorithm; the Beidou short message communication module is used for realizing short message communication between the unmanned aerial vehicle and a ground control station by using RDSS service; and the ground control station is used for creating a user interface by using Qt, carrying out data visualization through Tableau and adopting a security protocol. According to the scheme, remote control, remote information transmission and high-precision positioning functions in a complex environment of the unmanned aerial vehicle are realized.

The invention relates to a rabbit meat freshness detection method based on an electronic nose technology. The volatile gas release mode of the rabbit meat under different storage conditions including temperature, humidity and time is analyzed through experiments, and key putrefying gas including dimethylamine, hydrogen sulfide and aldehydes and the concentration change trend are recognized; a metal oxide semiconductor (MOS) or an electrochemical sensor matched with the gas is screened according to the identified main decay gas, and a sensitive material means comprising a tin oxide thin film doped with platinum is optimized; a response matrix of different sensors to target gas is established through experiments, and a multi-sensor signal fusion algorithm is optimized; a temperature and humidity sensor is introduced, and environmental noise correction is performed in combination with odor signals; adopting a convolutional neural network feature extraction method to extract nonlinear features associated with the rabbit meat decay stage; docking the extracted smell features with the dynamic distribution model, and unifying the quantization dimension through a feature standardization algorithm; and correcting the predicted corruption trend in real time in combination with a smell distribution dynamic model.

The invention discloses a power-on reset circuit, and relates to the technical field of integrated circuits, in order to eliminate static power consumption of the power-on reset circuit and reduce power consumption of the power-on reset circuit, the power-on reset circuit comprises a discharge delay circuit, a current mirror circuit and a buffer circuit; the discharge delay circuit comprises a capacitor and an NMOS (N-channel Metal Oxide Semiconductor) tube M4, and the NMOS tube M4 is used for discharging the capacitor; the current mirror image circuit comprises an NMOS tube M2, an NMOS tube M3 and a PMOS tube M9. The grid electrode of the NMOS tube M2 and the grid electrode of the PMOS tube M9 are respectively connected with the output end of the buffer circuit; the grid electrode of the NMOS tube M3 is respectively connected with the source electrode of the PMOS tube M9, the drain electrode of the NMOS tube M2 and the grid electrode of the NMOS tube M4; the current mirror image circuit is used for turning off the NMOS tube M2 after the reset signal is ended, and pulling up the drain electrode voltage of the NMOS tube M3 to the power supply voltage through the PMOS tube M9, so that the NMOS tube M3 enters a deep linear region, and a direct current path from the power supply to the ground in the current mirror image circuit is cut off; and the buffer circuit is used for outputting a reset signal according to the voltage change of the capacitor in the discharge delay circuit.

The invention relates to the technical field of MOS semiconductors, and discloses a low-groove high-power MOS device which comprises a plurality of MOS cells which are arranged in parallel, and each MOS cell comprises a metal source electrode, a grid electrode, a semiconductor epitaxial layer and a drain electrode; wherein the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and an N well layer; the N-well layer comprises a heavily doped N-well layer I and a lightly doped N-well layer II; the P well layer comprises a heavily doped P well layer I, a heavily doped P well layer II, a heavily doped P well layer III, a lightly doped P well layer I and a lightly doped P well layer II. According to the invention, the lightly-doped P-well layers are arranged at the left and right lower corners of the gate, so that the phenomenon that the lightly-doped P-well layers and the gate oxide layer are punctured together in the background is avoided, and the stable use of the MOS device in high-power equipment is realized.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a VDMOSFET (vertical double-diffused metal oxide semiconductor field effect transistor) device with low threshold voltage, which comprises a drain electrode, a semiconductor epitaxial layer, a source electrode, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and is characterized in that an N substrate layer, an N drift layer, an N well layer, a P well layer and a heavily doped P layer are formed in the semiconductor epitaxial layer through ion implantation, the grid electrode comprises a triangular grid electrode and a rectangular grid electrode, the grid oxide layer covering the surface of the triangular grid electrode is in contact with the N substrate layer, and the N drift layer is divided into a left part and a right part by the grid oxide layer. According to the invention, the grid electrode is designed to further comprise the triangular grid electrode, the electric field effect of the grid electrode between the tip part of the triangular grid electrode and the drain electrode is better, but the grid oxide layer wrapped by the triangular grid electrode at the tip part is thicker, so that charges flowing out of the drain electrode gather towards the inside of the heavily doped N layer more quickly along the grid oxide layer; at the moment, more charge flow can be provided in a smaller grid voltage environment.

The invention provides a germanium-silicon groove preparation method, which comprises the following steps of: forming a PMOS (P-channel Metal Oxide Semiconductor) gate structure and an NMOS (N-channel Metal Oxide Semiconductor) gate structure on a semiconductor substrate, arranging a first silicon nitride layer, a silicon oxide layer and a second silicon nitride layer in hard mask layers of the PMOS gate structure and the NMOS gate structure, exposing the second silicon nitride layer through a gate side wall, and covering a germanium-silicon mask layer, a patterned photoresist protection NMOS gate structure is formed, the germanium-silicon mask layer exposed in the PMOS region is etched, a groove is formed, and at least part of the second silicon nitride layer is reserved at the top of the PMOS gate to protect the silicon oxide layer; according to the method, the first silicon nitride layer and the germanium-silicon mask layer are etched, germanium-silicon deposition is carried out, and the residual second silicon nitride layer and the germanium-silicon mask layer are removed together through wet etching, so that the height difference of the hard mask layer caused by the conventional process of the PMOS gate and the NMOS gate is eliminated, the process load is avoided, the process steps are simplified, and the process cost is reduced.

Provided are a transistor with favorable electrical characteristics, a transistor with a high on-state current, a transistor with low parasitic capacitance, or a transistor, a semiconductor device, or a memory device which can be miniaturized or highly integrated. An oxide semiconductor layer included in the transistor, the semiconductor device, or the memory device includes a first region, a second region over the first region, and a third region over the second region. The first region is located in a range from a surface on which the oxide semiconductor layer is to be formed to greater than or equal to 0 nm to less than or equal to 3 nm in a direction substantially perpendicular to the surface. In cross-sectional observation of the oxide semiconductor layer using a transmission electron 10 microscope, bright spots arranged in a layered manner in a direction parallel to the surface are observed in each of the first region, the second region, and the third region.

The invention discloses a capacitive battery active equalization circuit and a method thereof. The capacitive battery active equalization circuit comprises a plurality of single batteries, a power MOS (Metal Oxide Semiconductor) tube circuit, an energy storage circuit and a control loop, the control loop comprises an ADC module, a PID module, a constant current controller and a power MOS tube driving module. The corresponding end of the ADC module is electrically connected with the corresponding ends of the plurality of single batteries and the PID module; the corresponding end of the PID module is connected with the corresponding end of the power MOS tube driving module through the constant current controller; and the corresponding end of the power MOS tube driving module is electrically connected with the corresponding end of the power MOS tube circuit. Compared with the scheme in the current market, the device has the advantages of low cost, small size, easiness in integration, simplicity in control, high safety and the like, and can store the energy of the battery with high voltage to the capacitor and carry the energy stored on the capacitor to the battery with low voltage, so that the aim of balancing the electric quantity of the battery is fulfilled.

A memory device that operates at high speed is provided.The memory device includes first and second memory cells, first and second bit lines, first and second switches, and a sense amplifier. The sense amplifier comprises a first node and a second node. The first memory cell is electrically connected to the first node through the first bit line and the first switch, and the second memory cell is electrically connected to the second node through the second bit line and the second switch. The sense amplifier amplifies the potential difference between the first node and the second node. The first memory cell and the second memory cell include an oxide semiconductor in a channel formation region.

The invention relates to the technical field of MOS (metal oxide semiconductor), and discloses a shallow-channel super-junction MOS device and a preparation process thereof, the shallow-channel super-junction MOS device comprises a drain electrode, a source electrode, a semiconductor epitaxial layer, a grid electrode and a grid oxide layer covering the surface of the grid electrode, and the semiconductor epitaxial layer comprises an N substrate layer and a drift layer; a P well layer, a P-layer II and an N well layer are formed in the drift layer through ion implantation; the cross section of the grid electrode is T-shaped; a first P-layer is formed in the N well layer through ion implantation, and a narrow heavily doped N layer is formed in the drift layer and located between two adjacent second P-layers through ion implantation. After the gate voltage is accessed, a charge channel is formed in the P-layer 2, so that the N-well layer and the drift layer can form a path, and the existence of the P-layer 1 can inhibit the collection of charges flowing in the N-well layer to the gate region, so that the number of parasitic charges can be greatly reduced, and the response speed of the MOS semiconductor device is improved.

Disclosed examples include microelectronic devices, e.g. Integrated circuits. One example includes a microelectronic device including a nanosheet lateral drain extended metal oxide semiconductor (LDMOS) transistor with source and drain regions having a first conductivity type extending into a semiconductor substrate having an opposite second conductivity type. A superlattice of alternating layers of nanosheets of a channel region and layers of gate conductor are separated by a gate dielectric, the superlattice extending between the source region and the drain region. A drain drift region of the first conductivity type extends under the drain region and a body region of the second type extends around the source region.

The invention provides a metal oxide semiconductor electrostatic protection device. The metal oxide semiconductor electrostatic protection device comprises a substrate; a well region of a first conductivity type disposed in the substrate; the source electrode region is formed in the well region of the first conduction type, the source electrode region comprises a first heavily doped region, and the first heavily doped region is of a second conduction type; a drain region; a gate structure; the body contact region comprises a third heavily doped region, and the third heavily doped region is of the first conduction type; wherein the drain region comprises a plurality of second heavily doped regions, the plurality of second heavily doped regions are of a second conduction type, and the plurality of second heavily doped regions are arranged at positions adjacent to the gate structure; the fourth heavily doped region is of the second conduction type, and the fourth heavily doped region is not arranged close to the gate structure; and a lightly doped drain region of the second conductivity type disposed below the plurality of second heavily doped regions and the fourth heavily doped regions. By changing the structure of the drain electrode heavily doped region, the ESD current distribution is improved, and the ESD endurance capability of the device is improved.

The embodiment of the invention provides a manufacturing method of a semiconductor structure, the semiconductor structure and a CMOS (Complementary Metal Oxide Semiconductor) circuit. The manufacturing method of the semiconductor structure comprises the following steps: providing a semiconductor substrate; wherein the semiconductor substrate comprises a semiconductor substrate, and a buffer layer and a stress layer which cover the semiconductor substrate; the semiconductor substrate comprises an NMOS region and a PMOS region; a PMOS gate structure is formed on the surface of the PMOS region; the buffer layer covering the side surface of the PMOS gate structure and the buffer layer covering the surface of the semiconductor substrate form an adjacent region; removing a part of the stress layer covering the PMOS region in the semiconductor substrate, and forming a stress layer residual part on the surface, far away from the semiconductor substrate, of the adjacent region of the buffer layer; executing an ion implantation process in the PMOS region; wherein the region for executing the ion implantation process comprises a stress layer residual part, so that the etching rate of etching the stress layer residual part is increased; and etching to remove the residual part of the stress layer. According to the embodiment of the invention, the overall electrical performance of the CMOS circuit is improved.

A complementary metal oxide semiconductor (CMOS) device embedded with micro-electro-mechanical system (MEMS) components in a MEMS region is disclosed. The MEMS components, for example, are infrared (IR) thermosensors. The MEMS sensors are integrated on the CMOS device monolithically after CMOS processing. For example, the MEMS sensors are formed over a BEOL dielectric of a CMOS device. The device is encapsulated with a CMOS compatible IR transparent cap to hermetically seal the MEMS sensors in the MEMS region.

The embodiment of the invention provides a display panel and a display device, relates to the technical field of display, and is used for optimizing the layout design of a pixel circuit. The display panel comprises a substrate and a pixel circuit located on one side of the substrate. The pixel circuit comprises a driving transistor, and an active layer of the driving transistor is located on an oxide semiconductor layer; a first electrode of the data write-in transistor is electrically connected with the data line, and a second electrode of the data write-in transistor is electrically connected with a first electrode of the driving transistor through a first connecting line; the first connecting line is located at one side of the oxide semiconductor layer away from the substrate.

The invention provides a high-precision current limiting circuit of an LDO (Low Dropout Regulator) with an NMOS (N-channel Metal Oxide Semiconductor) tube as a power tube, which is applied to the technical field of current limiting circuits and comprises a voltage loop and a current loop, and the voltage loop is used for monitoring and stabilizing the output voltage VOUT of a power tube NM1; and the current loop is used for acquiring a sampling current according to the load current of the power tube NM1, comparing the sampling current with a reference current IREF, and when the sampling current is higher than the reference current IREF, driving and controlling the output voltage VOUT of the power tube NM1 to be reduced so as to limit the load current of the power tube NM1 to continue to rise. When the LDO works normally, the output voltage VOUT of the power tube NM1 is stabilized through the voltage loop, and when the load current is too high, the output voltage VOUT of the power tube NM1 is driven and controlled to be reduced through the current loop, so that the load current of the power tube NM1 is prevented from continuing to rise, and the stability and the safety of the LDO are improved.

An improved silicon carbide (SiC) super junction (SJ) MOSFET having at least two buried P-shield (BPS) regions facing each other for gate oxide electric-field and saturation current reductions is disclosed. The two BPS regions are spaced apart from a body region and formed either adjoining sidewalls or below a bottom of a P column region. Moreover, a saturation current pitching (SCP) structure formed in a Junction Field Effect Transistor (JFET) region sandwiched between the two BPS regions limits saturation current of the device in a forward conduction stage for the short-circuit capability improvement.

The invention relates to the technical field of optical elements, systems or instruments, in particular to a temperature field testing method based on combination of colorimetric temperature measurement and multispectral imaging, and solves the technical problems of low temperature field temperature measurement reconstruction precision and low temporal-spatial resolution of an existing temperature measurement method. The method comprises the following steps: determining a spectral range and a temperature measurement range of a temperature field of a solid engine combustion chamber by utilizing an LIBS (Laser-induced Breakdown Spectroscopy) technology, coupling and packaging a multispectral optical filter and a CMOS (Complementary Metal Oxide Semiconductor) sensor, calibrating a multispectral camera by utilizing a blackbody furnace, and acquiring a spectral image of the temperature field by utilizing the multispectral camera. And obtaining a two-dimensional temperature field of the combustion chamber of the solid engine by using a colorimetric temperature measurement method, and performing comprehensive evaluation. According to the invention, multispectral information of the solid propellant combustion chamber flame can be obtained, and high space-time resolution detection of the two-dimensional temperature field of the solid engine combustion chamber is realized.

The invention relates to a method for mechanically regulating and controlling a nerve cell calcium ion signal by using an Airy beam to control an optical bullet, which comprises the following steps: firstly preparing the optical bullet and culturing HT-22 cells, then dynamically regulating and controlling the cell calcium ion signal, and finally monitoring and recording an image in the regulation and control process in real time through a CMOS (Complementary Metal Oxide Semiconductor) camera. According to the method, non-contact mechanical stimulation on nerve cells can be realized. The spatial resolution limitation of the traditional nerve regulation and control technology is broken through, and a non-invasive and high-biocompatibility nerve signal regulation and control means is provided. Besides, in combination with a real-time fluorescence monitoring technology, the regulation and control effect can be intuitively evaluated, and a brand new tool is provided for neuroscience research and clinical application.