Memory cell (102), comprising: a lower
electrode (106); an upper
electrode (108) that lies above the lower
electrode (106); and a
dielectric stack (104) comprising several
dielectric layers (104h, 104l1, 104l2) stacked between the lower and upper electrodes (106, 108); wherein the multiple
dielectric layers (104h, 104l1 104l1, 104l2) have a first
dielectric layer (104h) and the first
dielectric layer (104h) those of the dielectric
layers (104h, 104l) n 104l1, 104l2) is the one that is closest to the lower electrode (106) and has the highest
electron affinity (X1) from the dielectric layers (104h, 104l1 104l1, 104l2), wherein the multiple dielectric layers (104h, 104l, 104l1, 104l2) have a second
dielectric layer (104l1) and a third dielectric layer (10412), and wherein the second dielectric layer (104l1) is located between the first and the third dielectric layer (104h, 104l2), wherein the second dielectric layer (104l1) has an
electron affinity (X2) between that of the first dielectric layer (104h) and that of the third dielectric layer (104l2), or wherein the third dielectric layer (10412) has an
electron affinity (X3) between that of the first dielectric layer (104h) and that of the second dielectric layer (104l1).