337 results about "Electron affinity" patented technology

A thin-film transistor including an oxide semiconductor layer is disclosed. The oxide semiconductor layer includes a first area, a second area and a third area forming a well-type potential in the film-thickness direction. The first area forms a well of the well-type potential and has a first electron affinity. The second area is disposed nearer to the gate electrode than the first area and has a second electron affinity smaller than the first electron affinity. The third area is disposed farther from the gate electrode than the first area and has a third electron affinity smaller than the first electron affinity. At least an oxygen concentration at the third area is lower than an oxygen concentration at the first area.

Nano-architected/assembled solar cells and methods for their manufacture are disclosed. The solar cells comprise oriented arrays of nanostructures wherein two or more different materials are regularly arrayed and wherein the presence of two different materials alternates. The two or more materials have different electron affinities. The two materials may be in the form of matrixed arrays of nanostructures. The presence of the two different materials may alternate within distances of between about 1 nm and about 100 nm. An orientation can be imposed on the array, e.g. through solution deposition surfactant templation or other methods.

Photovoltaic devices, such as solar cells, and methods for their manufacture are disclosed. A device may be characterized by an architecture where two more materials having different electron affinities are regularly arrayed such that their presence alternates within distances of between about 1 nm and about 100 nm. The materials are present in a matrix based on a porous template with an array of template pores. The porous template is formed by anodizing a layer of metal. A photovoltaic device may include such a porous template disposed between a base electrode and a transparent conducting electrode. A first charge-transfer material fills the template pores, A second (complementary) charge-transfer material fills additional space not occupied by the first charge-transfer material.

A group III nitride semiconductor light emitting device according to the present invention includes an immediate layer formed of Al_xGa_1-x-yIn_yN (0<x<1, 0<y<1, x+y<1) between an active layer and a cladding layer and an electron blocking layer formed of p-type group III nitride semiconductor having a smaller electron affinity than that of the intermediate layer so as to be in contact with the intermediate layer. The semiconductor light emitting layer may be a laser diode or a LED.

Device are described that include a semiconductor material layer and at least one graphene-based electrode disposed over a portion of the semiconductor material layer, such that the at least one graphene-based electrode forms an overlap region with the semiconductor material layer. The device includes a means for providing charge carriers in the at least one graphene-based electrode proximate to the overlap region, to reduce a difference between a work function of the at least one graphene-based electrode and an electron affinity of the semiconductor material layer, to reduce a Schottky barrier height between the semiconductor material layer and the at least one graphene-based electrode.

Structures, systems and methods for floating gate transistors utilizing oxide-conductor nanolaminates are provided. One floating gate transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A floating gate is separated from the channel region by a first gate oxide. The floating gate includes oxide-conductor nanolaminate layers to trap charge in potential wells formed by different electron affinities of the oxide-conductor nanolaminate layers.

An organic photoelectric conversion element comprises: a pair of electrodes; an organic photoelectric conversion layer arranged between the pair of electrodes; and an positive hole blocking layer arranged between one of the pair of electrodes and the organic photoelectric conversion layer, wherein an ionization potential of the positive hole blocking layer is larger than a work function of the adjoining electrode by 1.3 eV or more, and wherein an electron affinity of the positive hole blocking layer is equal to or larger than that of the adjoining organic photoelectric conversion layer. An electron blocking layer may be arranged between the other one of the pair of electrodes and the organic photoelectric conversion layer, wherein its electron affinity is smaller than a work function of the adjoining electrode by 1.3 eV or more, and its ionization potential is equal to or smaller than that of the adjoining organic photoelectric conversion layer.

There has been a problem in conventional Si-type floating-gate type nonvolatile semiconductor memory devices that the charge retention characteristic is low due to insufficiently large electron affinity of Si, therefore improvement of the memory performances, such as scaling down of a memory cell and increasing operation speed, have been difficult to be achieved due to the essential problem. In order to solve the above problem, in the nonvolatile semiconductor memory device of the present invention, a material having large work function or large electron affinity or a material having a work function close to that of semiconductor substrate or of a control gate, is employed for a floating gate retaining charges. Further, an amorphous material having small electron affinity for an insulating matrix is used. Further, at a time of deposition of charge retention layer, the supply ratio of the nano-particle material and the insulating matrix material, such as the mixture ratio of materials of both phases in a target in a sputtering method, is adjusted. By these methods, the charge retention characteristic of the floating-gate type nonvolatile semiconductor memory device can be improved, and the above-mentioned problem of the nonvolatile semiconductor memory device can be solved.

A gallium nitride based field effect transistor having good current hysteresis characteristics in which forward gate leakage can be reduced. In a gallium nitride-based field effect transistor (100) having a gate insulation film (108), part or all of a material constituting the gate insulation film (108) is a dielectric material having a relative dielectric constant of 9-22, and a semiconductor crystal layer A (104) in contact with the gate insulation film (108) and a semiconductor crystal layer B (103) in the vicinity of the semiconductor crystal layer A (104) and having a larger electron affinity than the semiconductor crystal layer A (104) constitute a hetero junction. A hafnium oxide such as HfO₂, HfAlO, HfAlON or HfSiO is preferably contained, at least partially, in the material constituting the gate insulation film (108).

A non-linear element (such as a diode) which includes an oxide semiconductor and has a favorable rectification property is provided. In a transistor including an oxide semiconductor in which the hydrogen concentration is 5×10¹⁹/cm³ or lower, a work function φms of a source electrode in contact with the oxide semiconductor, a work function φmd of a drain electrode in contact with the oxide semiconductor, and electron affinity χ of the oxide semiconductor satisfy φms≦χ<φmd, and an area of contact between the drain electrode and the oxide semiconductor is larger than an area of contact between the source electrode and the oxide semiconductor. By electrically connecting a gate electrode and the drain electrode in the transistor, a non-linear element having a favorable rectification property can be achieved.

Structures, systems and methods for transistors utilizing oxide nanolaminates are provided. One transistor embodiment includes a first source/drain region, a second source/drain region, and a channel region therebetween. A gate is separated from the channel region by a gate insulator. The gate insulator includes oxide insulator nanolaminate layers with charge trapping in potential wells formed by different electron affinities of the insulator nanolaminate layers.

Disclosed is a novel flash memory device using a high-permittivity dielectric such as HfO₂ or TiO₂ as a charge trapping layer. Numerical simulation shows that the novel trapping material will enhance the retention time/programming speed ratio by 5 orders of magnitude, compared to the conventional Si₃N₄ trapping layer. Capacitors with HfO₂ deposited by RTCVD as the charge trap/storage layer in SONOS-type flash memory devices were fabricated and characterized. Compared against devices with Si₃N₄ trapping layer, faster programming speed as well as good retention time is achieved with low programming voltage.

An organic electroluminescent element including one or more organic compound layers including at least one luminescent layer between an anode and a cathode, wherein the luminescent layer includes at least two host compounds and at least two phosphorescent materials, and the phosphorescent materials include a phosphorescent material (D1) that satisfies at least one of the following conditions: (a) when the ionization potential of the phosphorescent material (D1) is defined as Ip(D1) and the minimum value out of the ionization potentials of the at least two host compounds as Ip(H)min, ΔIp1 as defined by ΔIp1=Ip(D1)−Ip(H)min satisfies ΔIp1<0 eV, and (b) when the electron affinity of the phosphorescent material (D1) is defined as Ea(D1) and the maximum value out of the electron affinities of the at least two host compounds as Ea(H)max, ΔEa1 as defined by ΔEa1=Ea(H)max−Ea(D1) satisfies ΔEa1<0 eV.

It is an object of the present invention to obtain an organometallic complex that is capable of converting an excited triplet state into luminescence, a light-emitting element that can be driven for a long time, is high in luminous efficiency, and has a favorable long lifetime, and a light-emitting device using the light-emitting element. The present invention provides a light-emitting element that has a pair of electrodes (an anode and a cathode) and a light-emitting layer between a pair of electrodes, where the light-emitting layer includes an organometallic complex represented by the following general formula (5) and one of a compound that has a larger energy gap than the organometallic complex and a compound that has a larger ionization potential and a smaller electron affinity than the organometallic complex, and provides a light-emitting device using the light-emitting device.

Disclosed is a highly reliable organic electroluminescent device, in particular, a phosphorescent organic electroluminescent device using a low-molecular-weight host material, wherein a good balance between electron and hole injection and an efficient mechanism of phosphorescence are maintained. The organic electroluminescent device contains a light-emitting layer between an anode layer and a cathode layer and the light-emitting layer comprises a phosphorescent dopant material and a host material with a molecular weight of not more than 10,000. The host material is composed of a first host material and a second host material that is different from the first host material and the first host material differs from the second host material by not more than 0.1 eV in the ionization potential (IP), by not more than 0.1 eV in the electron affinity (EA), and by not more than 0.1 eV in the triplet energy (T1).

A method of producing a field emission device includes laying a group III-nitride semiconductor layer over a substrate, placing a photoresist mask over the group III-nitride semiconductor layer, patterning a generally circular grid in the photoresist mask and the group III-nitride semiconductor layer, and forming the group III-nitride semiconductor layer into generally pointed tips using an inductively coupled plasma dry etching process, wherein the group III-nitride semiconductor layer comprises a group III-nitride semiconductor material having a low positive electron affinity or a even a negative electron affinity, wherein the inductively coupled plasma dry etching process selectively creates an anisotropic deep etch in the group III-nitride semiconductor layer, and wherein the inductively coupled plasma dry etching process creates an isotropic etch in the group III-nitride semiconductor layer. Preferably, the photoresist layer is approximately 1.7 microns in thickness, and the fabricated tips have a radius of curvature of less than 100 nanometers.