1896 results about "Semiconductor memory" patented technology

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

Memory cell structures, semiconductor memory devices, and their fabrication methods are disclosed. In an embodiment, method for fabricating a semiconductor device includes: forming a lower interconnect over a base layer; forming a memory cell structure over the lower interconnect; and forming an upper interconnect over the memory cell structure, wherein the forming of the memory cell structure includes: forming an initial selection element material layer; performing a first doping process that provides first dopants into the initial selection element material layer to reform the initial selection element material layer into a first doped selection element material layer; performing a second doping process that provides second dopants into the first doped selection element material layer to reform the first doped selection element material layer into a second doped selection element material layer; and forming a selection element layer by patterning the second doped selection element material layer.

A semiconductor memory device according to an embodiment, the device includes a first stacked body including a first stepped portion in which a plurality of first conductive layers are processed stepwise; a second stacked body disposed above the first stacked body, including a second stepped portion in which a plurality of second conductive layers are processed stepwise; a first insulating layer that covers the first and second stepped portions; a first layer that is interposed in the first insulating layer above the first stepped portion so as to be disposed at a height position between the first and second stacked bodies; and a first contact that extends downward from above the first stepped portion through the first insulating layer and the first layer and is connected to any one conductive layer of the plurality of first conductive layers processed stepwise.

A semiconductor memory device includes an external resistor in a board, and a plurality of memory dies mounted on the board and that are designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation and outputs a first done signal indicating completion of the first impedance calibration operation to the slave dies through a first impedance pad. Each of the slave dies includes a second impedance pad, and receives the first done signal through the second impedance pad, generates an identification signal based on the first done signal, performs a second impedance calibration operation sequentially with respect to the other slave dies based on the identification signal, and outputs a second done signal indicating completion of the second impedance calibration operation through the second impedance pad.

A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.

A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.

Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.

A semiconductor memory device of an embodiment includes: a first stacked body in which a plurality of conductive layers is stacked apart from each other in a stacking direction; a plate-shaped portion that extends in the first stacked body in the stacking direction and in a first direction intersecting the stacking direction, the plate-shaped portion dividing the first stacked body in a second direction intersecting the stacking direction and the first direction; and a pillar that extends in the first stacked body in the stacking direction and in which a memory cell is formed at each of intersection portions with at least some of the plurality of conductive layers, wherein between each the plurality of conductive layers, a first layer and a first insulating layer are disposed, the first layer including at least one of a Si—C bond or a Si—Si bond, the first insulating layer including a Si—O bond, the first insulating layer covering upper and lower surfaces of the first layer in the stacking direction and an end surface of the first layer facing a side wall of the plate-shaped portion LI, the first layer includes Si—C bonds or Si—Si bonds more than the first insulating layer, and the first insulating layer includes Si—O bonds more than the first layer.

A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

A charge pump circuit of a semiconductor memory device, which may include a first pumping stage that includes a first pumping capacitor and a second pumping capacitor, a first transfer stage that transfers a voltage of the first pumping capacitor when a clock signal is at a high level or transfers a voltage of the second pumping capacitor when a inverse clock signal is at the high level, a second pumping stage that includes a third pumping capacitor and a fourth pumping capacitor, and a second transfer stage that transfers a voltage of the third pumping capacitor when the clock signal is at the high level or transfers a voltage of the fourth pumping capacitor when the inverse clock signal is at the high level. The second transfer stage may output multiple times of the input voltage.

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory block including a plurality of memory cells, a voltage generation circuit configured to generate a read voltage and a pass voltage to be applied to word lines of the memory block during a read operation on the memory block, a temperature measurement circuit configured to measure a temperature before or after the read operation is performed, and output a temperature code corresponding to the measured temperature, and a block read counter configured to determine a read count increment of the memory block depending on the read operation based on the temperature code, and to update a read count value for the memory block by adjusting the read count value depending on the read count increment.

To provide a semiconductor storage device which enables high-speed operation.SOLUTION: A semiconductor storage device includes a substrate, a plurality of memory blocks, and a control circuit. The control circuit is configured to be able to consecutively execute a second program operation, after subsequently executing a first precharge operation and a first program operation in a first-mode write operation. In the first precharge operation, a predetermined voltage is supplied to a first word line. In the first program operation, a first voltage is supplied to a first selection gate line, a first program voltage is supplied to the first word line, and a write path voltage smaller than the first program voltage is supplied to a second word line. In the second program operation, the first voltage is supplied to a second selection gate line, a second program voltage larger than the write path voltage is supplied to the first word line, and the write path voltage is supplied to the second word line.SELECTED DRAWING: Figure 12

An IC structure includes a memory stack including a plurality of semiconductor die. The semiconductor memory dies horizontally separate with each other, wherein each semiconductor die includes a top surface, a bottom surface, four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions. The area of the bottom surface or the top surface is larger than that of any sidewall. A first part of the plurality of edge pads is located within an upper portion of the first sidewall of the semiconductor die, a second part of the plurality of edge pads is located within a lower portion of the first sidewall of the semiconductor die. One the semiconductor die includes at least one thermal edge portion exposed from the second sidewall.

According to one embodiment, a semiconductor memory device includes a memory cell array; a member; and a conductor portion intersecting the member, wherein the memory cell array includes word lines on one side in a Z direction regarding a source line, the conductor portion is included in a same layer as the source line, includes a surface on an other side in the Z direction having a height substantially equivalent to a height of a surface on the other side of the source line, and the member includes a contact surrounding the word lines, and an insulating film covering a side surface of the contact from one end of the contact on the one side to a height on the one side regarding an other end of the contact.

A semiconductor memory device includes a substrate, a conductive line extending in a first horizontal direction above the substrate, an isolation insulating layer including a channel trench extending in a second horizontal direction intersecting with the first horizontal direction and extending from an upper surface to a lower surface of the isolation insulating layer, above the conductive line, a channel structure disposed above the conductive line, a gate electrode extending in the second horizontal direction, in the channel trench, a capacitor structure above the isolation insulating layer, and a contact structure interposed between the channel structure and the capacitor structure, wherein the channel structure includes an amorphous oxide semiconductor layer disposed in the channel trench above the conductive line, and an upper crystalline oxide semiconductor layer interposed between the amorphous oxide semiconductor layer and the contact structure.

A semiconductor memory device includes a bit line extending in a first direction, an active pattern on the bit line, and including first and second side walls opposite to each other in the first direction and first and second surfaces opposite to each other in a vertical direction, the first surface of the active pattern connected to the bit line, a word line on the first side wall of the active pattern and extending in a second direction, and a data storage pattern on the active pattern and connected to the second surface of the active pattern, wherein the word line includes first, second, third line patterns, and the second and third line patterns include conductive materials different from the first line pattern.

According to one embodiment, there is provided a semiconductor memory device including a first chip, a second chip and a third chip. In the first chip, plural first conductive layers are stacked via a first insulating layer. In the second chip, plural second conductive layers are stacked via a second insulating layer. A number of stack layers in the plural first conductive layers and a number of stack layers in the plural second conductive layers are different from each other.

A semiconductor memory device includes a physical region, a direct access region and a power manager. The direct access region interfaces with an external test device directly. The power manager generates an internal power supply voltage based on one of a first power supply voltage, a second power supply voltage and a power supply voltage, and provides the internal power supply voltage to the direct access region. The power manager provides the second power supply voltage to the physical region. The direct access region includes a test interface circuit and the test interface circuit, in a direct access mode, generates an internal clock signal based on an external clock signal, generates an internal test clock signal by latching a test control signal received from the external test device based on the internal clock signal and provides the internal test control signal to the physical region.

Disclosed is a semiconductor memory device including a lower structure and an upper structure on the lower structure. The upper structure includes a first substrate, an upper wiring line on the first substrate, a lower power line in a lower portion of the first substrate, and a first bonding pad between the lower power line and the lower structure. The lower power line and the first bonding pad are electrically connected to each other. The upper structure is electrically connected through the first bonding pad to the lower structure.

A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, first and second active patterns disposed on the bit line, a back-gate electrode, which is disposed between the first and second active patterns and is extended in a second direction to cross the bit line, a first word line, which is provided at a side of the first active pattern and is extended in the second direction, a second word line, which is provided at an opposite side of the second active pattern and is extended in the second direction, and contact patterns coupled to the first and second active patterns, respectively.

A semiconductor memory device includes a stacked body in which a plurality of conductive layers is stacked with being separated from each other, and a plate-like portion extending in the stacked body in a stacking direction of the stacked body and in a first direction intersecting with the stacking direction, and penetrating through conductive layers from an uppermost conductive layer to an N-th (N is an integer of 1 or more) conductive layer, among the plurality of conductive layers, in which the plate-like portion includes a wing portion protruding toward the N-th conductive layer, at least at a height position of the N-th conductive layer among the plurality of conductive layers.

A semiconductor memory apparatus may include: a data adjusting circuit configured to conditionally adjust a weight data value for a MAC (Multiplication and ACcumulation) operation based on comparing the weight data value to a reference data value, and generate flag information indicating whether the weight data value has been adjusted; a memory cell array circuit configured to store the adjusted weight data value outputted from the data adjusting circuit; and a data calculation circuit configured to recover, on the flag information, a result based on the weight data value from a result based on the adjusted weight data value to perform the MAC operation on an input data value and the weight data value.

Provided is a semiconductor memory device including a plurality of semiconductor chips stacked on each other and having a novel structure different from the prior art. The semiconductor storage device comprises memory chips 1-1 and 1-2 which are stacked with each other. The memory chips 1-1, 1-2 include circuit elements and wirings arranged in the same layout between the memory chips 1-1, 1-2. The memory chips (1-1, 1-2) each have a front surface and a back surface facing each other, and a plurality of first terminals disposed on the front surface. In each of the memory chips 1-1, 1-2, the plurality of first terminals are arranged in mirror symmetry with respect to a plane of symmetry orthogonal to the front surface and the back surface. The memory chips (1-1, 1-2) are stacked such that the surface of the memory chip (1-1) is in contact with the surface of the memory chip (1-2), and the plurality of first terminals of the memory chip (1-1) are connected to the plurality of first terminals of the memory chip (1-2).

According to one embodiment, a semiconductor memory device includes: a first chip including first conductive layers arranged at intervals in a first direction, a first semiconductor layer extending through an inside of the first conductive layers in the first direction, a first insulating film between the first semiconductor layer and the first conductive layers, a second semiconductor layer provided above the first conductive layers and in contact with the first semiconductor layer, and a first electrode provided in contact with an upper side of the second semiconductor layer; and a second chip including a second electrode in contact with the first electrode, and a second conductive layer in contact with the second electrode.

A 3D semiconductor device, the device including: a first level including first single crystal transistors; a second level including second transistors; memory periphery circuits; and memory cells, where the first level is overlaid by the second level, where the first level includes a transferred layer and a bonded layer, where the second level is bonded to the first level, where the bonded second level includes oxide to oxide bonds, where the bonded second level includes metal to metal bonds, where the first level includes a preponderance of the memory periphery circuits, where the second level includes a preponderance of the memory cells, where the preponderance of the memory periphery circuits are connected to the preponderance of the memory cells using a portion of the metal to metal bonds, and where the memory periphery circuits include at least one Look up Table (“LUT”) circuit.

There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a conductive gate contact penetrating a contact region of a stepped stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked.

A semiconductor memory device comprises a peripheral circuit structure including a peripheral circuit substrate and a peripheral circuit element on the peripheral circuit substrate, a source layer including a first surface facing the peripheral circuit structure and a second surface opposite to the first surface, a stack structure including a plurality of mold insulating films and a plurality of gate electrodes alternately stacked on the first surface of the source layer, and a channel structure extending through the stack structure and contacting the source layer. The source layer is in contact with an uppermost gate electrode that is closest to the source layer among the plurality of gate electrodes.

The invention belongs to the technical field of semiconductor memory testing, and particularly relates to a multi-block embedded flash memory testing circuit and a testing method thereof. Comprising an SPI main control module which communicates with external test equipment based on an SPI interface protocol to realize serial and parallel receiving and sending of data so as to generate commands and data required by test; the data conversion module is used for completing the adaptation of input and output data formats so as to ensure the correct transmission of the data between the test circuit and the Flash block; the time sequence control module is used for generating a control signal required by the Flash block according to a test requirement; and the Flash selection module is used for driving the selected Flash block to execute programming, erasing and reading operations according to the control signal output by the time sequence control module and the test command output by the data conversion module. The problems of low test efficiency, inaccurate time sequence control and the like in the prior art are solved.