1257 results about "Semiconductor memory" patented technology

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

Memory cell structures, semiconductor memory devices, and their fabrication methods are disclosed. In an embodiment, method for fabricating a semiconductor device includes: forming a lower interconnect over a base layer; forming a memory cell structure over the lower interconnect; and forming an upper interconnect over the memory cell structure, wherein the forming of the memory cell structure includes: forming an initial selection element material layer; performing a first doping process that provides first dopants into the initial selection element material layer to reform the initial selection element material layer into a first doped selection element material layer; performing a second doping process that provides second dopants into the first doped selection element material layer to reform the first doped selection element material layer into a second doped selection element material layer; and forming a selection element layer by patterning the second doped selection element material layer.

A semiconductor memory device includes an external resistor in a board, and a plurality of memory dies mounted on the board and that are designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation and outputs a first done signal indicating completion of the first impedance calibration operation to the slave dies through a first impedance pad. Each of the slave dies includes a second impedance pad, and receives the first done signal through the second impedance pad, generates an identification signal based on the first done signal, performs a second impedance calibration operation sequentially with respect to the other slave dies based on the identification signal, and outputs a second done signal indicating completion of the second impedance calibration operation through the second impedance pad.

There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.

A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

An IC structure includes a memory stack including a plurality of semiconductor die. The semiconductor memory dies horizontally separate with each other, wherein each semiconductor die includes a top surface, a bottom surface, four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions. The area of the bottom surface or the top surface is larger than that of any sidewall. A first part of the plurality of edge pads is located within an upper portion of the first sidewall of the semiconductor die, a second part of the plurality of edge pads is located within a lower portion of the first sidewall of the semiconductor die. One the semiconductor die includes at least one thermal edge portion exposed from the second sidewall.

A semiconductor memory device includes a physical region, a direct access region and a power manager. The direct access region interfaces with an external test device directly. The power manager generates an internal power supply voltage based on one of a first power supply voltage, a second power supply voltage and a power supply voltage, and provides the internal power supply voltage to the direct access region. The power manager provides the second power supply voltage to the physical region. The direct access region includes a test interface circuit and the test interface circuit, in a direct access mode, generates an internal clock signal based on an external clock signal, generates an internal test clock signal by latching a test control signal received from the external test device based on the internal clock signal and provides the internal test control signal to the physical region.

A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, first and second active patterns disposed on the bit line, a back-gate electrode, which is disposed between the first and second active patterns and is extended in a second direction to cross the bit line, a first word line, which is provided at a side of the first active pattern and is extended in the second direction, a second word line, which is provided at an opposite side of the second active pattern and is extended in the second direction, and contact patterns coupled to the first and second active patterns, respectively.

A 3D semiconductor device, the device including: a first level including first single crystal transistors; a second level including second transistors; memory periphery circuits; and memory cells, where the first level is overlaid by the second level, where the first level includes a transferred layer and a bonded layer, where the second level is bonded to the first level, where the bonded second level includes oxide to oxide bonds, where the bonded second level includes metal to metal bonds, where the first level includes a preponderance of the memory periphery circuits, where the second level includes a preponderance of the memory cells, where the preponderance of the memory periphery circuits are connected to the preponderance of the memory cells using a portion of the metal to metal bonds, and where the memory periphery circuits include at least one Look up Table (“LUT”) circuit.

There are provided a semiconductor memory device and a manufacturing method of a semiconductor memory device. The semiconductor memory device includes a conductive gate contact penetrating a contact region of a stepped stack structure including a plurality of interlayer insulating layers and a plurality of conductive patterns, which are alternately stacked.

The invention belongs to the technical field of semiconductor memory testing, and particularly relates to a multi-block embedded flash memory testing circuit and a testing method thereof. Comprising an SPI main control module which communicates with external test equipment based on an SPI interface protocol to realize serial and parallel receiving and sending of data so as to generate commands and data required by test; the data conversion module is used for completing the adaptation of input and output data formats so as to ensure the correct transmission of the data between the test circuit and the Flash block; the time sequence control module is used for generating a control signal required by the Flash block according to a test requirement; and the Flash selection module is used for driving the selected Flash block to execute programming, erasing and reading operations according to the control signal output by the time sequence control module and the test command output by the data conversion module. The problems of low test efficiency, inaccurate time sequence control and the like in the prior art are solved.

The disclosure discloses a memory cell structure, a semiconductor memory device, and methods of manufacturing the same. In one embodiment, a semiconductor device includes: a lower interconnect extending in a first horizontal direction; an upper interconnect extending in a second horizontal direction perpendicular to the first horizontal direction; and a memory cell structure arranged in a columnar shape between the lower interconnect and the upper interconnect, wherein the memory cell structure includes: a selection element layer; a memory element layer; and an intermediate electrode disposed between the selection element layer and the storage element layer, the selection element layer including: at least one of silicon oxide, silicon nitride, or silicon oxynitride; the first dopant comprises at least one of boron, aluminum, gallium, indium or thallium; and the second dopant includes at least one of arsenic, phosphorus, or germanium.

A semiconductor memory device includes active patterns spaced apart from each other in first and second directions intersecting each other, each active pattern having a central portion, a first end portion, and a second end portion, bit line contacts disposed on the central portions and spaced apart from each other in the first and second directions, separation insulating patterns, each of which is disposed between the bit line contacts adjacent to each other in the first and second directions, intermediate insulating patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the first direction, and connection patterns, each of which is disposed between the bit line contact and the separation insulating pattern which are adjacent to each other in the second direction.

Embodiments of the present invention provide a semiconductor memory device capable of improving processing power and a control method for the semiconductor memory device. The semiconductor memory device of the embodiment includes a plurality of first memory cells (MT), word lines (WL), and a control circuit (17). In the first programming cycle of the first mode, after performing the first programming by applying a first voltage (VSV) to the word line, the control circuit (17) boosts the second voltage (VCG_SV) applied to the word line (WL) while repeatedly performing the first verification until the number of disconnected cells of the first memory cells falls below a threshold. Based on the first voltage (VSV) and the number of times the first verification is repeated, a third voltage (VPGM_SV) is determined. In the first second programming cycle of the second mode, the third voltage (VPGM_SV) is applied to the word line (WL) to perform the second programming.

The present disclosure provides a semiconductor memory device and a method of fabricating the same, including a substrate, a plurality of bit lines, a bit line contact, a spacer, a liner layer, and a storage node contact. The bit lines are separately disposed on the substrate. The bit line contact is disposed below one of the bit lines to extend into one active area. The spacer is disposed on sidewalls of each of the bit lines and the bit line contact. The liner layer is disposed on the substrate along an outer periphery of the bit line contact, wherein the liner layer comprises a first portion embedded in the one of the bit line, between the bit line contact and the one of the bit lines in an extending direction of the bit lines. The storage node contact and the bit lines are alternately arranged with each other.

According to one embodiment, a semiconductor memory device includes an input and output pad group, a memory cell array including a plurality of memory cells, and an input and output circuit provided between the input and output pad group and the memory cell array. The input and output circuit includes a plurality of transistors, and a substrate bias voltage supply circuit that is controllable to supply one of a first voltage having the same value as a power supply voltage of the input and output circuit and a second voltage having a value different from the first voltage as a substrate bias voltage to the plurality of transistors.

An example semiconductor memory device may include a first conductive line extending in a first direction perpendicular to a substrate, a first gate electrode extending in a second direction, crossing the first direction, on the substrate, a first semiconductor pattern extending from the first conductive line to the first gate electrode, a second gate electrode spaced apart from the first gate electrode on the substrate and extending in the second direction, and a contact extending in the first direction and electrically connected with the first gate electrode and the second gate electrode.

The embodiment of the invention provides a three-dimensional semiconductor memory which comprises a substrate, a plurality of active layers located on the substrate and arranged on the substrate in an array mode, a plurality of bit lines connected to one ends of the active layers respectively, extending in the second direction and stacked on the substrate in the third direction, and a plurality of memory units arranged on the substrate in a stacked mode. The plurality of bit lines are respectively connected to the other end of the active layer, the shielding structure comprises a main body part and a plurality of shielding parts, the shielding parts extend along the second direction, the main body part and the shielding parts are made of conductive materials, the main body part is electrically connected with the shielding parts, and at least one shielding part is arranged between adjacent bit lines along the third direction. In the embodiment of the invention, the shielding part is formed between the stacked bit lines, the shielding part is electrically connected to the main body part, and the main body part is connected to the fixed potential end, so that the electrical isolation between the stacked bit lines is realized, the parasitic capacitance between the bit lines is reduced, and the electrical performance of the stacked device is improved.

A semiconductor memory device, and a method of manufacturing the semiconductor memory device, includes: a substrate including a peripheral circuit, a gate stack structure disposed over the substrate and including a cell array region and a stepped region that extends from the cell array region, a channel structure passing through the cell array region of the gate stack structure, a memory layer surrounding a sidewall of the channel structure, a first contact plug passing through the stepped region of the gate stack structure, and an insulating structure surrounding a sidewall of the first contact plug to insulate the first contact plug from the gate stack structure.

A semiconductor memory device includes a memory cell array including a first block and a second block, and a control circuit. The control circuit executes a first write operation of writing first data by applying a first voltage to a channel area of a first memory cell transistor of the first block through a bit line and then while the channel area of the first memory cell transistor is in a floating state, applying a program voltage to a first word line. The control circuit starts a second write operation of writing second data into a second memory cell transistor of the second block that is connected to the bit line while the program voltage is applied to the first word line.

A semiconductor memory device is disclosed. The semiconductor memory device may include a bit line extending in a first direction, a word line extending in a second direction perpendicular to the first direction, a channel pattern between the bit line and the word line, the channel pattern including a horizontal channel portion, which is connected to the bit line, and a vertical channel portion, which is extended from the horizontal channel portion in a third direction perpendicular to the first and second directions, and a gate insulating pattern between the word line and the channel pattern. The horizontal channel portion of the channel pattern may be disposed parallel to a fourth direction that is inclined to the first and second directions.

The application provides a semiconductor memory and a manufacturing method thereof and an electronic device, comprising: a substrate; a plurality of control gate stack structures and a plurality of array common source isolation layers alternately and separately arranged on one side surface of the substrate; an array common source connection layer on the side of the array common source isolation layer away from the substrate; an insulating filling layer covering the side of the array common source connection layer away from the substrate and filling into a groove between adjacent array common source connection layers, the insulating filling layer comprising a via hole corresponding to the array common source connection layer; and a bridge wire on the side of the insulating filling layer away from the substrate and connecting the adjacent two array common source connection layers through the via hole.

A semiconductor memory device and an initialization method thereof are provided that refresh initial data in memory cells during initialization and stabilize the charge amount of the memory cells. [Solution] A semiconductor memory device 100 includes a memory array, a refresh controller, and an initialization controller. The memory array has a plurality of equalization circuits and N memory cells. The plurality of equalization circuits are respectively connected to the N memory cells via a plurality of bit line pairs. The refresh controller sequentially refreshes initial data in the N memory cells in accordance with an auto-refresh command. The initialization controller performs an initialization operation in accordance with an initialization start command. During the initialization operation, the initialization controller enables the equalization circuit and periodically generates auto-refresh commands.

Control circuit (100) which outputs a first signal to discharge charges accumulated in a source line (SL) and a bit line (BL) according to the activation of a word line (WL) and outputs a second signal to put the source line and the bit line into a potential-free state until the start of writing or reading, with respect to a memory cell which has the source line (SL), the bit line (BL), a transistor (Tr5) which is provided between the source line (SL) and the bit line (BL) and is switched on and off by a potential of the word line (WL), and a storage element (R1) connected in series with the transistor (TR5), wherein the control circuit (100) has a first transistor (Tr3) connected to the source line (SL) and a second transistor (Tr4) connected to the bit line (BL), and the first transistor (Tr3) includes a first gate terminal and the second transistor (Tr4) includes a second gate terminal, wherein the first gate terminal is connected to a first NAND gate (69) and the second gate terminal is connected to a second NAND gate (70), and wherein both the source line (SL) and the bit line (BL) are short-circuited to a ground potential at a first time point in response to the first signal and transition from their respective first potential-free states to their respective non-potential-free states, and transition at a second time point in response to the second signal to their respective second potential-free states.

A method for fabricating a semiconductor memory device includes: forming word lines and bit lines; forming filling patterns between the bit lines and at ends of the bit lines, and forming first gaps surrounded by the filling patterns and the bit lines; depositing an insulating material, to fill up the first gaps surrounded by the filling patterns and the bit lines, and forming cavities surrounded by the insulating material in each of the first gaps respectively; etching the insulating material to form a strip-shaped isolation structure and columnar isolation structures, where the cavity of the strip-shaped isolation structure is exposed to form a seam; after etching the insulating material, removing a portion of the filling patterns to form second gaps, where the second gaps are surrounded by the columnar isolation structures and the bit lines; and depositing a conductive material to fill up the second gaps and the seam concurrently.

According to one embodiment, a semiconductor memory device includes: a first chip including a substrate having a first region and a second region; and a second chip which is in contact with the first chip in the Z direction and is electrically connected to the first chip via a plurality of connection pads provided in a boundary region with the first chip. The second chip includes: a memory cell array provided in the first region, the memory cell array having a source line, a plurality of word lines provided spaced apart from each other in the first direction below the source line, and a memory pillar having an upper end connected to the source line; a plurality of contacts provided in the second region, extending in the first direction, and each electrically connected to any one of the plurality of connection pads; a conductor pattern in contact with the upper ends of the plurality of contacts; and a first wiring layer extending above the conductor pattern and electrically connected to the conductor pattern.

A semiconductor memory device includes: a stacked body including conductive and insulating layers that are alternately stacked in a first direction; memory pillars extending in the first direction in the stacked body; and a structure body segmenting the memory pillars and extending in the first direction in the stacked body. The structure body includes a crystalline conductor extending in the first direction in the stacked body, a first insulating film between the stacked body and the crystalline conductor, a crystalline semiconductor film between the crystalline conductor and the first insulating film, and a second insulating film between the crystalline semiconductor film and a side surface of the crystalline conductor. The crystalline conductor includes a first crystal region in contact with the crystalline semiconductor film and containing germanium, and a second crystal region on the first crystal region and in contact with the second insulating film in a second direction.

The present application relates to a semiconductor device and a semiconductor memory device. The semiconductor device of an embodiment includes an oxide semiconductor layer; a gate electrode; a gate insulating layer; a first electrode and a second electrode electrically connected to the oxide semiconductor layer; a first conductive layer provided at at least one of a position between the oxide semiconductor layer and the first electrode and a position between the oxide semiconductor layer and the second electrode, containing at least one metal element selected from the group consisting of titanium (Ti), vanadium (V), zirconium (Zr), niobium (Nb), and chromium (Cr), aluminum (Al), and nitrogen (N), and including a first portion and a second portion, the first portion having a higher atomic concentration of the metal element than an atomic concentration of aluminum in the first portion, and the second portion having a higher atomic concentration of aluminum than an atomic concentration of the metal element in the second portion; and a second conductive layer provided between the oxide semiconductor layer and the first conductive layer.

To provide a semiconductor memory device with improved product reliability.SOLUTION: The semiconductor memory device includes a substrate, a plurality of semiconductor patterns disposed on the substrate to be spaced apart from each other in a first direction parallel to an upper surface of the substrate, a plurality of interlayer insulating patterns each disposed between the plurality of semiconductor patterns adjacent to each other in a third direction perpendicular to the substrate, and a plurality of data storage elements each electrically connected to the plurality of semiconductor patterns corresponding thereto, wherein the plurality of semiconductor patterns include at least one dummy pattern and a plurality of active patterns, and the at least one dummy pattern includes a first element having an atomic size smaller than an atomic size of silicon.SELECTED DRAWING: Figure 2

According to one embodiment, the array chip includes a three-dimensionally disposed plurality of memory cells and a memory-side interconnection layer connected to the memory cells. The circuit chip includes a substrate, a control circuit provided on the substrate, and a circuit-side interconnection layer provided on the control circuit and connected to the control circuit. The circuit chip is stuck to the array chip with the circuit-side interconnection layer facing to the memory-side interconnection layer. The bonding metal is provided between the memory-side interconnection layer and the circuit-side interconnection layer. The bonding metal is bonded to the memory-side interconnection layer and the circuit-side interconnection layer.