2611 results about "Semiconductor memory" patented technology

A ZQ calibration circuit included in a semiconductor memory device includes a reference voltage selector configured to output a reference voltage selected from among a first reference voltage and a second reference voltage generated based on a first supply voltage and a second supply voltage, in response to a selection signal, a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage, and a loop selector configured to output the selection signal according to whether each of the pull-up code and the pull-down code is toggled. Levels of the first and second reference voltages are different from each other, smaller than a level of the first supply voltage, and greater than a level of the second supply voltage.

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

A self-refresh method of a semiconductor memory device including: receiving a self-refresh entry command; performing a self-refresh cycle based on the self-refresh entry command; receiving a self-refresh exit command; based on receiving the self-refresh exit command, determining a refresh operation status; and based on determining that the refresh operation status indicating an idle state, executing a care refresh operation corresponding to row-hammer care.

A semiconductor memory device includes a first chip and a second chip. The first chip includes a first cell array mat and a second cell array mat adjacent to the first cell array mat. The second chip has a stacked structure with the first chip and includes a first sub-word line driver configured to generate a first drive signal applied to the first word lines from one side of each of the first and second cell array mats, and a second sub-word line driver configured to generate a second drive signal applied to the second word lines from an opposite side of each of the first and second cell array mats.

The method comprises the steps of dividing a production line logic group through a dynamic load balancing algorithm, allocating hardware resources, and constructing a fault prediction model based on an LSTM neural network to optimize test parameters. Binding the test result, the SPD serial number and the work station ID number, and uploading the test result, the SPD serial number and the work station ID number to an MES system through an asynchronous message queue; the system integrates a modularized test configuration unit, a multi-dimensional data analysis platform, an authority management module and a self-adaptive interface device. According to the invention, high automation and intelligentization of the test process are realized, the test efficiency, the data accuracy and the system safety are obviously improved, the manual intervention cost is effectively reduced, the fault prediction capability is improved, and a comprehensively optimized technical solution is provided for a semiconductor memory test production line.

Memory cell structures, semiconductor memory devices, and their fabrication methods are disclosed. In an embodiment, method for fabricating a semiconductor device includes: forming a lower interconnect over a base layer; forming a memory cell structure over the lower interconnect; and forming an upper interconnect over the memory cell structure, wherein the forming of the memory cell structure includes: forming an initial selection element material layer; performing a first doping process that provides first dopants into the initial selection element material layer to reform the initial selection element material layer into a first doped selection element material layer; performing a second doping process that provides second dopants into the first doped selection element material layer to reform the first doped selection element material layer into a second doped selection element material layer; and forming a selection element layer by patterning the second doped selection element material layer.

A semiconductor memory device is provided. The device includes a cell structure, a peripheral structure, and an interconnection structure sequentially stacked on a support substrate, in which the cell structure includes lower electrodes, a dielectric layer and an upper electrode with the dielectric layer and the upper electrode sequentially covering the lower electrodes, the peripheral structure includes a peripheral substrate and transistors disposed on a front surface of the peripheral substrate, and an upper surface of the upper electrode faces a back surface of the peripheral substrate.

A semiconductor memory device according to an embodiment, the device includes a first stacked body including a first stepped portion in which a plurality of first conductive layers are processed stepwise; a second stacked body disposed above the first stacked body, including a second stepped portion in which a plurality of second conductive layers are processed stepwise; a first insulating layer that covers the first and second stepped portions; a first layer that is interposed in the first insulating layer above the first stepped portion so as to be disposed at a height position between the first and second stacked bodies; and a first contact that extends downward from above the first stepped portion through the first insulating layer and the first layer and is connected to any one conductive layer of the plurality of first conductive layers processed stepwise.

A system includes a controller and a first memory chip associated with a first unique number and including a first set of pads coupled to the controller. The first memory chip is configured to receive a command from the controller through at least one pad of the first set of pads, the command including a target unique number and a target chip address, and the target chip address having a fewer number of bits than a number of bits of the target unique number, and to store the target chip address as a first chip address identifying the first memory chip, in response to the target unique number matching the first unique number.

A semiconductor memory device including a plurality of semiconductor patterns extending in a first horizontal direction on a substrate and having a first source / drain region, a channel region, and a second source / drain region, at least one interlayer separation insulating layer that separates the plurality of semiconductor patterns from each other in a vertical direction, a plurality of word lines each surrounding the channel region, a bit line connected to the first source / drain region and extending in the vertical direction, a plurality of first electrodes each on one side of the second source / drain region, a plurality of second electrodes each positioned inside respective ones of the plurality of first electrodes, a ferroelectric film positioned between the first electrode and the second electrode, a plate line that contacts the plurality of second electrodes, and a leaker configured to transfer charge between the first electrode and the second electrode.

A semiconductor memory device includes an external resistor in a board, and a plurality of memory dies mounted on the board and that are designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation and outputs a first done signal indicating completion of the first impedance calibration operation to the slave dies through a first impedance pad. Each of the slave dies includes a second impedance pad, and receives the first done signal through the second impedance pad, generates an identification signal based on the first done signal, performs a second impedance calibration operation sequentially with respect to the other slave dies based on the identification signal, and outputs a second done signal indicating completion of the second impedance calibration operation through the second impedance pad.

According to an embodiment, a semiconductor memory device includes a first pin, a first receiving circuit, and a first terminating circuit. The first pin receives a first signal and a second signal having a smaller amplitude than the first signal. The first receiving circuit is connected to the first pin and outputs, based on a comparison between the first signal and a first voltage, a third signal. The first receiving circuit also outputs, based on a comparison between the second signal and a second voltage, a fourth signal having a smaller amplitude than the third signal. The first terminating circuit is connected to the first pin. The first terminating circuit is disabled if the first pin receives the first signal, and enabled if the first pin receives the second signal.

A semiconductor memory device includes a bit line, a channel pattern including a horizontal channel portion on the bit line and a vertical channel portion vertically protruding from the horizontal channel portion, a word line on the horizontal channel portion and on a sidewall of the vertical channel portion, and a gate insulating pattern between the word line and the channel pattern. The channel pattern includes an oxide semiconductor and includes first, second, and third channel layers sequentially stacked. The first to third channel layers include a first metal, and the second channel layer further includes a second metal different from the first metal. At least a portion of the first channel layer contacts the bit line.

A 3D semiconductor memory device includes a peripheral circuit structure, an intermediate insulating layer and a cell array structure. The cell array structure includes a first substrate including a cell array region and a connection region; a stack structure comprising electrode layers and electrode interlayer insulating layers alternately stacked on the first substrate; a planarization insulating layer covering an end portion of the stack structure on the connection region; and a first through-via penetrating the planarization insulating layer, the first substrate and the intermediate insulating layer. The first through-via connects one of the electrode layers to the peripheral circuit structure. The first through-via includes a first and second via portion integrally connected to each other. The first via portion penetrates the planarization insulating layer and has a first width. The second via portion penetrates the intermediate insulating layer and has a second width greater than the first width.

Provided is a semiconductor memory device. The semiconductor memory device includes a plurality of trenches including a plurality of first trenches in a substrate and a plurality of second trenches between ones of the plurality of first trenches, and a plurality of device isolation layers. A first height of a lowermost surface of a direct contact in a vertical direction may be higher than a second height of a lowermost surface of a buried contact in the vertical direction, relative to a lower surface of the substrate.

A semiconductor device includes a cell substrate; a mold structure which includes gate electrodes and mold insulating films alternately stacked on the cell substrate; a channel layer that extends in a vertical direction intersecting an upper side of the cell substrate, inside the mold structure; an insertion layer which includes ferroelectrics and surrounds the channel layer; and a dielectric layer which is not interposed between the insertion layer and the gate electrodes, but is interposed between the insertion layer and the mold insulating films, wherein the gate electrodes are in contact with the insertion layer.

A semiconductor memory device includes: a memory cell array including a plurality of NAND strings, each of the plurality of NAND strings including a plurality of memory cell transistors connected to each other in series; a plurality of word lines commonly connected to the plurality of memory strings and connected to the plurality of memory cell transistors, respectively; and a row decoder configured to supply a predetermined voltage higher than a ground voltage to each of the plurality of word lines after a program operation for writing data to a selected word line is completed.

There are provided a semiconductor memory device and a manufacturing method of the same. The semiconductor memory device includes: a peripheral circuit structure with a page buffer group; a net-shaped first source pattern disposed on the peripheral circuit structure, the net-shaped first source pattern with a plurality of openings; a memory cell array disposed on the net-shaped first source pattern; a second source pattern disposed between the net-shaped first source pattern and the memory cell array; and a cell-array-side pad pattern, disposed between the net-shaped first source pattern and the second source pattern, extending toward the net-shaped first source pattern from the second source pattern, the cell-array-side pad pattern being bonded directly to the net-shaped first source pattern.

A p layer extending in a direction horizontal to a substrate is provided separately from the substrate. An n+ layer and an n layer are provided on respective sides of the layer. A gate insulating layer partially covers the layers. A gate conductor layer partially covers the layer. A gate insulating layer partially covering the layer is provided separately from the layer. A gate conductor layer partially covers the layer. An n+ layer is provided at part of the p layer between the layers. The layers are connected to a bit line, a control line, a word line, a plate line, and a source line, respectively. Memory operation of a dynamic flash memory cell is performed by manipulating voltage of each line.

A semiconductor memory device according to an embodiment includes a substrate, a source line, word lines, a pillar, and a first member. The first member is provided to penetrate the source line. The first member includes a first portion which is far from the substrate, and a second portion which is near the substrate. The first member includes a first contact and a first insulating film. The first contact is provided to extend from the first portion to the second portion. The first contact is electrically connected to the substrate. The first insulating film insulates the source line from the first contact. The first member includes a stepped portion at a boundary part between the first portion and the second portion.

Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

A semiconductor memory cell comprising six vertical-transport field-effect transistors (VTFET) on a wafer. The six VTFET are in a first layer. The six VTFET are in a first row.

A semiconductor memory device of an embodiment includes: a first stacked body in which a plurality of conductive layers is stacked apart from each other in a stacking direction; a plate-shaped portion that extends in the first stacked body in the stacking direction and in a first direction intersecting the stacking direction, the plate-shaped portion dividing the first stacked body in a second direction intersecting the stacking direction and the first direction; and a pillar that extends in the first stacked body in the stacking direction and in which a memory cell is formed at each of intersection portions with at least some of the plurality of conductive layers, wherein between each the plurality of conductive layers, a first layer and a first insulating layer are disposed, the first layer including at least one of a Si—C bond or a Si—Si bond, the first insulating layer including a Si—O bond, the first insulating layer covering upper and lower surfaces of the first layer in the stacking direction and an end surface of the first layer facing a side wall of the plate-shaped portion LI, the first layer includes Si—C bonds or Si—Si bonds more than the first insulating layer, and the first insulating layer includes Si—O bonds more than the first layer.

A semiconductor memory device includes a first channel structure which is adjacent to an insulating structure and penetrates a plurality of conductive layers, a second channel structure which is spaced apart from the insulating structure and penetrates the plurality of conductive layers, a first impurity region included in an end portion of the first channel structure, and a second impurity region included in an end portion of the second channel structure. A doping concentration of an impurity in the first impurity region is different from a doping concentration of an impurity in the second impurity region.

An encoder includes an encoding unit configured to receive 2n-bit read data and to generate 2m-bit read data, and an output driver configured to input m-bit first read data of the 2m-bit read data, to transmit voltage and / or current a first number of times corresponding to a number of first bits indicating a first state included in the m-bit first read data or to transmit current corresponding to the number of first bits during an activation period of a clock signal, and to transmit the voltage and / or the current a second number of times corresponding to a number of second bits indicating the first state included in m-bit second read data of the 2m-bit read data or to transmit current corresponding to the number of second bits during a deactivation period of the clock signal, wherein n is at least 2 and m is at least 3.

A charge pump circuit of a semiconductor memory device, which may include a first pumping stage that includes a first pumping capacitor and a second pumping capacitor, a first transfer stage that transfers a voltage of the first pumping capacitor when a clock signal is at a high level or transfers a voltage of the second pumping capacitor when a inverse clock signal is at the high level, a second pumping stage that includes a third pumping capacitor and a fourth pumping capacitor, and a second transfer stage that transfers a voltage of the third pumping capacitor when the clock signal is at the high level or transfers a voltage of the fourth pumping capacitor when the inverse clock signal is at the high level. The second transfer stage may output multiple times of the input voltage.

Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device may include a memory block including a plurality of memory cells, a voltage generation circuit configured to generate a read voltage and a pass voltage to be applied to word lines of the memory block during a read operation on the memory block, a temperature measurement circuit configured to measure a temperature before or after the read operation is performed, and output a temperature code corresponding to the measured temperature, and a block read counter configured to determine a read count increment of the memory block depending on the read operation based on the temperature code, and to update a read count value for the memory block by adjusting the read count value depending on the read count increment.

To provide a semiconductor storage device which enables high-speed operation.SOLUTION: A semiconductor storage device includes a substrate, a plurality of memory blocks, and a control circuit. The control circuit is configured to be able to consecutively execute a second program operation, after subsequently executing a first precharge operation and a first program operation in a first-mode write operation. In the first precharge operation, a predetermined voltage is supplied to a first word line. In the first program operation, a first voltage is supplied to a first selection gate line, a first program voltage is supplied to the first word line, and a write path voltage smaller than the first program voltage is supplied to a second word line. In the second program operation, the first voltage is supplied to a second selection gate line, a second program voltage larger than the write path voltage is supplied to the first word line, and the write path voltage is supplied to the second word line.SELECTED DRAWING: Figure 12

An impedance calibration circuit includes a code generation circuit and a code update control circuit. The code generation circuit generates a first impedance code set by performing an impedance adjustment operation within an activated period of a data output enable signal generated in response to a read command. The code update control circuit prevents updating a second impedance code set to the first impedance code set until deactivation of the data output enable signal, wherein the second impedance code set is used in impedance adjustment of a transmitting circuit.

An IC structure includes a memory stack including a plurality of semiconductor die. The semiconductor memory dies horizontally separate with each other, wherein each semiconductor die includes a top surface, a bottom surface, four sidewalls with a first sidewall, a second sidewall, a third sidewall and a fourth sidewall, and a plurality of edge pads located on the first sidewall and arranged in multiple rows or two dimensions. The area of the bottom surface or the top surface is larger than that of any sidewall. A first part of the plurality of edge pads is located within an upper portion of the first sidewall of the semiconductor die, a second part of the plurality of edge pads is located within a lower portion of the first sidewall of the semiconductor die. One the semiconductor die includes at least one thermal edge portion exposed from the second sidewall.