3893 results about "Semiconductor memory" patented technology

A ZQ calibration circuit included in a semiconductor memory device includes a reference voltage selector configured to output a reference voltage selected from among a first reference voltage and a second reference voltage generated based on a first supply voltage and a second supply voltage, in response to a selection signal, a ZQ engine configured to generate a pull-up code and a pull-down code based on the selected reference voltage, and a loop selector configured to output the selection signal according to whether each of the pull-up code and the pull-down code is toggled. Levels of the first and second reference voltages are different from each other, smaller than a level of the first supply voltage, and greater than a level of the second supply voltage.

An array of memory cells includes a scan chain with one or more chain segments of storage memory cells. Chain segments are separated by chain buffer memory cells. Memory cells of each chain segment are coupled with a sequence generator that generates a sequence of non-overlapping pulses from a pulse in a scan clock (SCLK) signal. The duration of the sequence equals at most a cycle of the SCLK signal. The scan chain applies the pulses to the memory cells backwards starting from the chain buffer memory cell. Memory cells may include a single latch. The array of memory cells may be included in a semiconductor memory subsystem. A scan chain that has a fault condition may be repaired by rerouting the scan chain to avoid the location of the fault condition and to add one or more redundant chain segments.

A high-density ferroelectric memory, and a preparation method therefor and an application thereof, belonging to the field of semiconductor memories. In the memory, multiple memory cells are arranged in an array, and the two sides of the array of the memory cells are connected to substantially orthogonal word lines and bit lines, the memory cell of the present invention adopts a stacked structure of a top electrode, a resistive switching dielectric layer, an intermediate metal layer, a ferroelectric dielectric layer, and a bottom electrode, which is electrically equivalent to a ferroelectric capacitor and a resistive switching selector connected in series; the voltage division of the distributed ferroelectric capacitor in the unselected cells is reduced by regulating the RC delay of the memory cell, so that its disturbance is reduced; and the capacitance value of the ferroelectric capacitor is stable, and the influence of the disturbance voltage can be effectively reduced by RC regulation. The storage window of the memory is improved and the bit error rate is reduced, without increasing additional area overhead.

The invention provides a semiconductor memory device and a manufacturing method thereof, relates to the technical field of semiconductors, and is used for solving the problem of poor anti-magnetic capability of the semiconductor memory device. The semiconductor memory device comprises a magnetic layer, a spin orbit moment layer and a magnetic tunnel junction unit which are stacked in sequence; the free layer in the magnetic tunnel junction unit is adjacent to the spin orbit moment layer; the long axis directions of the magnetic layer and the free layer are parallel to each other, the magnetization directions of the magnetic layer and the free layer in the long axis direction of the magnetic layer are opposite by applying a write current to the spin-orbit moment layer, and the stray field of the semiconductor memory device is adjusted, and the write current has a current component in the short axis direction of the magnetic layer. According to the embodiment of the invention, the magnetic layer can be used for counteracting the stray field weakening anti-magnetic capability and promoting the stray field enhancing anti-magnetic capability, so that the anti-magnetic capability of the semiconductor memory device is improved.

A self-refresh method of a semiconductor memory device including: receiving a self-refresh entry command; performing a self-refresh cycle based on the self-refresh entry command; receiving a self-refresh exit command; based on receiving the self-refresh exit command, determining a refresh operation status; and based on determining that the refresh operation status indicating an idle state, executing a care refresh operation corresponding to row-hammer care.

A semiconductor memory device includes a first chip and a second chip. The first chip includes a first cell array mat and a second cell array mat adjacent to the first cell array mat. The second chip has a stacked structure with the first chip and includes a first sub-word line driver configured to generate a first drive signal applied to the first word lines from one side of each of the first and second cell array mats, and a second sub-word line driver configured to generate a second drive signal applied to the second word lines from an opposite side of each of the first and second cell array mats.

The method comprises the steps of dividing a production line logic group through a dynamic load balancing algorithm, allocating hardware resources, and constructing a fault prediction model based on an LSTM neural network to optimize test parameters. Binding the test result, the SPD serial number and the work station ID number, and uploading the test result, the SPD serial number and the work station ID number to an MES system through an asynchronous message queue; the system integrates a modularized test configuration unit, a multi-dimensional data analysis platform, an authority management module and a self-adaptive interface device. According to the invention, high automation and intelligentization of the test process are realized, the test efficiency, the data accuracy and the system safety are obviously improved, the manual intervention cost is effectively reduced, the fault prediction capability is improved, and a comprehensively optimized technical solution is provided for a semiconductor memory test production line.

A memory system includes a semiconductor memory device including a plurality of memory cells each configured to store data in a non-volatile manner according to a threshold voltage thereof and connected to a word line, and a controller configured to perform an error correction based on hard bit data and soft bit data read from the plurality of memory cells, generate a first table based on corrected data, determine a voltage difference between a first voltage and a second voltage, the first voltage being a voltage applied to the word line when the data being corrected is read, and correct the first table based on the voltage difference.

A semiconductor memory device, and a semiconductor package and an electronic system including the same are provided. The semiconductor memory device includes a substrate including a plurality of mat regions and a mat separation region between ones of the mat regions, a peripheral circuit structure on the substrate and including peripheral circuits, a cell array structure on the peripheral circuit structure, a first through-via extending into the substrate in the mat separation region, and a second through-via extending into the cell array structure on the mat separation region and electrically connected to the first through-via, wherein the second through-via overlaps the first through-via.

A semiconductor memory device includes a semiconductor substrate that includes first, second, and third regions spaced apart from each other in a first direction on a well region; first and second conductive layers that are spaced apart in the first direction; a first contact connected to the first region and passing through a first opening through the first conductive layer; a second contact connected to the third region and passing through a second opening through the second conductive layer; and third and fourth conductive layers that are between the first and second conductive layers and are spaced apart from each other in the first direction. The first conductive layer and the first contact are connected to each other to be at substantially the same potential, and the second conductive layer and the second contact are connected to each other to be at substantially the same potential.

Memory cell structures, semiconductor memory devices, and their fabrication methods are disclosed. In an embodiment, method for fabricating a semiconductor device includes: forming a lower interconnect over a base layer; forming a memory cell structure over the lower interconnect; and forming an upper interconnect over the memory cell structure, wherein the forming of the memory cell structure includes: forming an initial selection element material layer; performing a first doping process that provides first dopants into the initial selection element material layer to reform the initial selection element material layer into a first doped selection element material layer; performing a second doping process that provides second dopants into the first doped selection element material layer to reform the first doped selection element material layer into a second doped selection element material layer; and forming a selection element layer by patterning the second doped selection element material layer.

A device includes a memory cell that randomly presents either a first logic state or a second logic state. The memory cell includes: a plurality of first nanostructures extending along a first lateral direction; a plurality of second nanostructures extending along the first lateral direction and disposed at a first side of the plurality of first nanostructures; a plurality of third nanostructures extending along the first lateral direction and disposed at a second side of the plurality of first nanostructures; a dielectric fin structure disposed immediately next to the plurality of first nanostructures along a second lateral direction, wherein a first sidewall of each of the plurality of first nanostructures facing toward or away from the second lateral direction is in contact with the dielectric fin structure; and a first gate structure wrapping around each of the plurality of first nanostructures except for the first sidewall.

The invention provides a testing device, a testing system and a testing method, and relates to the technical field of semiconductor memory device testing. The testing device comprises a testing needle card, a DC testing circuit, an AC testing circuit, a mode switching circuit and a main control circuit. Two functions of AC testing and DC testing are integrated, the system can execute the DC testing process, the storage Die with faults is selected out, and then the performance of the storage Die at high frequency or actual working speed is further verified through the AC testing process, so that the storage Die with potential problems is identified, and the testing accuracy is improved. Meanwhile, the mode switching circuit is arranged to switch the connection of the DC test circuit and the connection / disconnection between the AC test circuit and the test needle card, so that the possible interference of the DC part on the AC high-frequency test in the same test device is effectively avoided, and the risk of AC test failure is reduced.

A three-dimensional semiconductor memory device may include a stack including gate electrodes and insulating layers, which are alternatingly stacked on a substrate, vertical channel structures penetrating the stack, and data storage patterns between the stack and the vertical channel structures. The data storage patterns may be spaced apart from each other in a direction perpendicular to a top surface of the substrate, and each of the data storage patterns may include a ferroelectric pattern, an anti-ferroelectric pattern, and a first insulating pattern.

A semiconductor memory device is provided. The device includes a cell structure, a peripheral structure, and an interconnection structure sequentially stacked on a support substrate, in which the cell structure includes lower electrodes, a dielectric layer and an upper electrode with the dielectric layer and the upper electrode sequentially covering the lower electrodes, the peripheral structure includes a peripheral substrate and transistors disposed on a front surface of the peripheral substrate, and an upper surface of the upper electrode faces a back surface of the peripheral substrate.

There is provided a semiconductor memory device comprising: a first word line; a second word line spaced apart from the first word line, a back gate electrode between the first word line and the second word line; a first channel pattern between the first word line and the back gate electrode; a second channel pattern between the second word line and the back gate electrode; a first gate insulating film between the first word line and the first channel pattern; a second gate insulating film between the second word line and the second channel pattern; a first bit line on the first channel pattern and the second channel pattern, wherein the first bit line is connected to the first channel pattern; and a second bit line on the first channel pattern and the second channel pattern, wherein the second bit line is connected to the second channel pattern.

A semiconductor memory device according to an embodiment, the device includes a first stacked body including a first stepped portion in which a plurality of first conductive layers are processed stepwise; a second stacked body disposed above the first stacked body, including a second stepped portion in which a plurality of second conductive layers are processed stepwise; a first insulating layer that covers the first and second stepped portions; a first layer that is interposed in the first insulating layer above the first stepped portion so as to be disposed at a height position between the first and second stacked bodies; and a first contact that extends downward from above the first stepped portion through the first insulating layer and the first layer and is connected to any one conductive layer of the plurality of first conductive layers processed stepwise.

The present disclosure relates to semiconductor memory devices. An example semiconductor memory device comprises a substrate, a structure including word lines and interlayer insulating films alternately stacked on the substrate, a channel region disposed between two adjacent word lines in a vertical direction, a first source / drain region disposed on a first side of the channel region, a second source / drain region disposed on a second side of the channel region, a bit line which extends in the vertical direction on the substrate and is connected to the first source / drain region, a capping insulating film disposed between the bit line and the word lines, and a data storage connected to the second source / drain region. At least a part of the first source / drain region protrudes from a sidewall of the capping insulating film toward the bit line.

A semiconductor memory device includes a plurality of word lines, a first select gate line, a second select gate line, a first semiconductor layer, a third select gate line, a fourth select gate line, a second semiconductor layer, and a word line contact electrode. The first select gate line and the third select gate line are farther from the substrate than the plurality of word lines. The second select gate line and the fourth select gate line are closer to the substrate than the plurality of word lines. The first semiconductor layer is opposed to the plurality of word lines, the first select gate line, and the second select gate line. The second semiconductor layer is opposed to the plurality of word lines, the third select gate line, and the fourth select gate line. The word line contact electrode is connected to one of the plurality of word lines.

A system includes a controller and a first memory chip associated with a first unique number and including a first set of pads coupled to the controller. The first memory chip is configured to receive a command from the controller through at least one pad of the first set of pads, the command including a target unique number and a target chip address, and the target chip address having a fewer number of bits than a number of bits of the target unique number, and to store the target chip address as a first chip address identifying the first memory chip, in response to the target unique number matching the first unique number.

A semiconductor memory device includes a peripheral circuit structure including peripheral circuits; a stacked structure on the peripheral circuit structure and including first electrode layers and first inter-electrode insulating layers that are alternately stacked; a first vertical pattern that extends into the stacked structure; a first insulating layer on the stacked structure, a second electrode layer on the first insulating layer, and a second insulating layer on the second electrode layer; a line separation pattern that extends into the second insulating layer, the second electrode layer, and the first insulating layer; and a second vertical pattern that extends into the second insulating layer, the second electrode layer, and the first insulating layer, where the second vertical pattern is electrically connected to the first vertical pattern.

A semiconductor device is provided. The semiconductor device includes a stack structure that includes a plurality of dielectric layers spaced apart from each other on a substrate, a plurality of electrodes interposed between the plurality of dielectric layers, and a plurality of stopper layers interposed between the plurality of dielectric layers; and a vertical channel structure that penetrates the stack structure. Each of the plurality of electrodes and the plurality of stopper layers is disposed in a corresponding empty space interposed between the plurality of dielectric layers, the plurality of stopper layers includes a first stopper layer and a second stopper layer that is interposed between the first stopper layer and the substrate, and at least one of the plurality of electrodes is interposed between the first stopper layer and the second stopper layer.

According to one embodiment, a semiconductor memory device includes first and second conductor layers, a first pillar, a first contact, and a source line drive circuit. The first pillar is passing through the second conductor layers. The first pillar includes a first semiconductor layer and a second insulator layer. The first semiconductor layer includes a side surface partially in contact with the first conductor layer. The first contact is passing through the second conductor layers. The first contact includes a third conductor layer and a third insulator layer. The third conductor layer includes a side surface partially in contact with the first conductor layer. The source line drive circuit is electrically coupled to the first conductor layer via the first contact.

A semiconductor memory device including a plurality of semiconductor patterns extending in a first horizontal direction on a substrate and having a first source / drain region, a channel region, and a second source / drain region, at least one interlayer separation insulating layer that separates the plurality of semiconductor patterns from each other in a vertical direction, a plurality of word lines each surrounding the channel region, a bit line connected to the first source / drain region and extending in the vertical direction, a plurality of first electrodes each on one side of the second source / drain region, a plurality of second electrodes each positioned inside respective ones of the plurality of first electrodes, a ferroelectric film positioned between the first electrode and the second electrode, a plate line that contacts the plurality of second electrodes, and a leaker configured to transfer charge between the first electrode and the second electrode.

A memory includes a plurality of planes, a controller, and a source line. The controller is configured to erase data of each memory cell in an erase target block selected in each of the planes, by executing an erase sequence that repeats a plurality of loops, each of the loops including a set of an erase operation that erases the data of each memory cell in the erase target block and an erase verification operation that checks whether the data is erased. For each erase target block, the controller is configured to detect whether there is a current leak from the source line, determine validity of the erase sequence based on a detection result, and stop execution of the erase sequence for the erase target blocks that are determined not to be valid.

A semiconductor memory device includes an external resistor in a board, and a plurality of memory dies mounted on the board and that are designated as a master die and slave dies. The memory dies are commonly connected to the external resistor. The master die performs a first impedance calibration operation and outputs a first done signal indicating completion of the first impedance calibration operation to the slave dies through a first impedance pad. Each of the slave dies includes a second impedance pad, and receives the first done signal through the second impedance pad, generates an identification signal based on the first done signal, performs a second impedance calibration operation sequentially with respect to the other slave dies based on the identification signal, and outputs a second done signal indicating completion of the second impedance calibration operation through the second impedance pad.

The invention provides an amplifier, a buffer circuit and a semiconductor storage device, and belongs to the technical field of circuits. The amplifier comprises: an input circuit comprising an input transistor for receiving a differential input voltage signal and generating and outputting a differential input current signal; the amplifying circuit is used for receiving the differential input current signal and carrying out folding operational amplification so as to generate and output a control signal; the output circuit comprises a pull-up transistor and a pull-down transistor which are connected with the output end of the output circuit, and the control end of the pull-up transistor and the control end of the pull-down transistor are both connected with the output end of the amplifying circuit so as to receive the control signal; the output circuit further comprises at least one pull-up compensation current source connected with the pull-up transistor in parallel and at least one pull-down compensation current source connected with the pull-down transistor in parallel.

An embodiment relates to a semiconductor memory device. A memory according to an embodiment includes a cell array. The first wiring is connected to the memory cells arranged in the first direction. The second wiring is connected to the memory cells arranged in the second direction. The plurality of third wirings are provided corresponding to each of the plurality of second wirings arranged in the third direction. The first sensing circuit is connected to a first pair of the third wirings. The second sensing circuit is connected to a second pair of the third wirings. The switching circuit is connected to the first and second sensing circuits and selectively outputs signals of the first and second sensing circuits. The switching control circuit stores the addresses of the second and third wirings connected to the defective cell, and outputs a control signal for controlling the switching circuit on the basis of the addresses of the second and third wirings connected to the selected cell to be read.

The present invention discloses a semiconductor memory test system and test method, which relates to the field of memory test technology. The system includes: a test board for directly inserting at least one semiconductor memory to be tested; a microclimate chamber placed on the test board for regulating the temperature environment of the test board; an offline software / test converter for writing a long vector test mode and downloading it to a vector tester to perform the test; the vector tester includes a controller and a multiplexer, a comparison logic device and a pin electronic device connected in sequence, which are used to generate a test signal according to the downloaded long vector test mode, send the test signal to the corresponding at least one semiconductor memory to be tested, and perform a logical comparison judgment according to the test feedback signal fed back by the semiconductor memory to be tested, so as to obtain the final test result. The present invention can realize semiconductor memory testing with lower cost and higher precision.

A semiconductor memory device includes a substrate including a cell region, a core region, and a boundary region between the cell region and the core region, a boundary element isolation layer in the boundary region, the boundary element isolation layer being in a boundary element isolation recess and including first and second boundary liner layers extending along a profile of the boundary element isolation recess and a first gate structure on the core region and at least a part of the boundary element isolation layer, wherein the first gate structure includes a first high dielectric layer, and a first gate insulating pattern below the first high dielectric layer, with a top surface of the substrate being a base reference level, the first gate insulating pattern does not overlap a top surface of the first boundary liner layer, and wherein the first gate insulating pattern includes a first_1 gate insulating pattern between a top surface of the second boundary liner layer and a bottom surface of the first high dielectric layer, and a first_2 gate insulating pattern disposed a top surface of the core region and a bottom surface of the first high dielectric layer.