9966 results about "Single chip" patented technology

A solid-state disk (SSD) has a smart storage switch with a smart storage transaction manager that re-orders host commands for accessing downstream single-chip flash-memory devices. Each single-chip flash-memory device has a lower-level controller that converts logical block addresses (LBA) to physical block addresses (PBA) that access flash memory blocks in the single-chip flash-memory device. Wear-leveling and bad block remapping are preformed by each single-chip flash-memory device, and at a higher level by a virtual storage processor in the smart storage switch. Virtual storage bridges between the smart storage transaction manager and the single-chip flash-memory devices bridge LBA transactions over LBA buses to the single-chip flash-memory devices. Data striping and interleaving among multiple channels of the single-chip flash-memory device is controlled at a high level by the smart storage transaction manager, while further interleaving and remapping may be performed within each single-chip flash-memory device.

A semiconductor storage employs a base substrate (101) having a command/address external terminal group (CA), a data input/output external terminal group (DQ), and a single chip select external terminal (CS), and also comprises a plurality of memory chips (110) to (113) mounted on a base substrate (101), each of which can individually carry out read and write operations. The terminals (CA), (DQ), and (CS) are connected to an interface chip (120). The interface chip (120) has a chip select signal generation circuit that can individually activate a plurality of memory chips (110) to (113) on the basis of an address signal fed by way of the terminal (CA) and on the basis of a chip select signal fed by way of the terminal (CS).

A single chip protocol converter integrated circuit (IC) capable of receiving packets generating according to a first protocol type and processing said packets to implement protocol conversion and generating converted packets of a second protocol type for output thereof, the process of protocol conversion being performed entirely within the single integrated circuit chip. The single chip protocol converter can be further implemented as a macro core in a system-on-chip (SoC) implementation, wherein the process of protocol conversion is contained within a SoC protocol conversion macro core without requiring the processing resources of a host system. Packet conversion may additionally entail converting packets generated according to a first protocol version level and processing the said packets to implement protocol conversion for generating converted packets according to a second protocol version level, but within the same protocol family type. The single chip protocol converter integrated circuit and SoC protocol conversion macro implementation include multiprocessing capability including processor devices that are configurable to adapt and modify the operating functionality of the chip.

In producing complementary sets of metal-oxide-semiconductor (CMOS) field effect transistors, including nMOS and pMOS transistors), carrier mobility is enhanced or otherwise regulated through the use of layering various stressed films over either the nMOS or pMOS transistor (or both), depending on the properties of the layer and isolating stressed layers from each other and other structures with an additional layer in a selected location. Thus both types of transistors on a single chip or substrate can achieve an enhanced carrier mobility, thereby improving the performance of CMOS devices and integrated circuits.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

External Cavity Laser An external cavity laser comprising first and second feedback means with an optical gain medium (2) therebetween, one of the feedback means is provided by a grating (4) formed in a silicon waveguide and the other feedback means is provided by a reflective back facet (2B) of the optical gain medium (2). The output wavelength of the laser, at a given temperature, can thus be determined during its manufacture and the laser can be made by mass production techniques. The grating (4) may be thermally isolated to obviate the need for temperature control means (6) to control the temperature of the grating (4). An array of lasers may be provided on a single chip.

A method and system for a single chip integrated Bluetooth and FM transceiver and baseband processor are provided. The single chip may comprise a Bluetooth radio, an FM radio, a processor system, and a peripheral transport unit (PTU). FM data may be received and/or transmitted via the FM radio and Bluetooth data may be received and/or transmitted via the Bluetooth radio. The FM radio may receive radio data system (RDS) data. The PTU may support digital and analog interfaces. A processor in the processor system may time-multiplex processing of FM data and processing of Bluetooth data. The single chip may operate in an FM-only, a Bluetooth-only, and an FM-Bluetooth mode. The single chip may reduce power consumption by disabling portions of the Bluetooth radio during FM-only mode and/or disabling analog circuitry when performing digital processing. Communication between Bluetooth and FM channels may be enabled via the single chip.

A single integrated circuit is provided to enable the distribution of voice, video, and/or data services throughout a multimedia distribution network, such as a cable communications network. The single integrated circuit supports both digital and analog television services (e.g., PVR, pay-for-view, EPG, e-commerce, etc.) and computer data services (e.g., telephony, Internet browsing, facsimile, messaging, videoconferencing, etc.). In an embodiment, the single integrated circuit includes three components that constitute a DOCSIS™ compliant cable modem, namely an inband demodulator, an upstream burst modulator, a media access controller, and a microprocessor. In an embodiment, a digital out-of-band demodulator is also included. In another embodiment, the single integrated circuit integrates front-end and backend set-top box functionality in addition to DOCSIS™ cable modem functionality.

A method of processing first and second record packets of real-time information includes computing for each packet a deadline interval and ordering processing of the packets according to the respective deadline intervals. A single-chip integrated circuit has a processor circuit and embedded electronic instructions forming an egress packet control establishing an egress scheduling list structure and operations in the processor circuit that extract a packet deadline intervals, place packets in the egress scheduling list according to deadline intervals; and embed a decoder that decodes the packets according to a priority depending to their deadline intervals.

A single integrated sensing chip with multi-functions for tire pressure monitor system (TPMS) comprises: a pressure sensor, an accelerometer, a temperature sensor, and an ASIC (Applied Specific Integrated Circuit) that implements signal conditioning and digitalizes pressure output. The accelerometer incorporated for vehicle motion is used to determine centrifugal acceleration or three-axial acceleration of the rotating wheel, and used for the TPMS sensor wake-up from “power down” mode, or when the velocity of the vehicle is higher than certain speed threshold, which is more robust and lower in cost than the mechanical vibration switch and is naturally integrated with the electronic control unit. The accelerometer can be used for regular motion sensing to monitor the dynamic stability. The integrated sensor system can be packaged into one plastic package first, and then surface mounted to the printed circuit board, or the multi-function single chip can be wafer bonded on the wafer level first and diced into many individual chips, with each chip being directly attached on to the printed circuit board by wire bonding or flip-chip assembly.

Aspects of the invention for managing power in a single chip device may comprise, an internal finite state machine that, while in a communicating state, determines from within the single chip device whether a power management status is set and/or whether a first power management event is received. If the power management status is set, the finite state machine may transition from the communicating state to a power management event sent state. If the first power management event is received, the finite state machine may transition from the communicating state to a non-communicating state. The first power management event may be a turn off power management event. Furthermore, in instances where the power management status is set, it may be cleared, thereby causing the finite state machine to transition back to the communicating state. One or more power management control registers may be utilized for indicating power management status.

A programmable analog system architecture and method thereof are described. The analog system architecture and method introduce a single chip solution that contains a set of tailored analog blocks and elements that can be configured and reconfigured in different ways to implement a variety of different analog functions. The architecture includes an array of analog blocks, including continuous time blocks and different types of switched capacitor blocks. The analog blocks can be electrically coupled to each other in different combinations to perform different analog functions. Each analog block includes analog elements that have changeable characteristics that can be specified according to the function to be performed. The architecture thereby facilitates the design of customized chips at less time and expense.

An access control system, has at least one door to a secured area, each door having a strike plate, a host computer, at least one door control module coupled to the host computer, one door control module for every door; and at least one door reader coupled to the at least one door reader coupled to the door control module to activate the strike plate to release the door. The access control system further has at least one electro-mechanical key to independently actuate a lock that corresponds to the door(s). A master keying device to rekey the lock that corresponds to door(s). The host system records information selected from the group consisting of time of entry, place of entry, identification of entered party, and/or any combination thereof. In addition, a door knob and mechanical locking mechanism selectively latches and unlatches the locking mechanism and can be actuated with a mechanical key; and circuitry to actuate the locking mechanism to selectively latch so that the door can open, the circuitry actuated by an electrical signal transmitted by an electrical key, the electrical signal communicated by an electrical contact extending through the mechanical locking mechanism. The circuitry is powered by a battery, which can be removed without disturbing or actuating unlocking mechanism. The contact is an insulated electrical wire that extends through the locking mechanism to the circuitry. All of the circuitry discussed can be integrated onto a single, monolithic piece of silicon in a multi-chip or single-chip format. A master rekeying device has input/output circuitry to receive and transmit electrical signals, circuitry coupled to the input/output circuitry to record a list of security passwords in order to check passwords against the list and a memory to store data; and the input/output circuitry also receives and transmits electrical signals to a host computer.

A single chip microcomputer comprises a central processing unit (CPU) 2, a on-chip RAM 3, a on-chip ROM 5, a first bus DBUS for connecting the CPU, RAM, and ROM with one another and transferring data between them, a second bus ABUS for passing address data corresponding to the data passed through the first bus, a third bus SDBUS for connecting the CPU 2 with the RAM 3 and transferring data between them, the number of bits of the third bus SDBUS being larger than that of the first bus DBUS, and a fourth bus BABUS for connecting the CPU 2 with the RAM 3 and passing address data corresponding to the data passed through the third bus SDBUS. The CPU 2 has a data memory RF serving as general purpose registers for providing internal data to the third bus SDBUS, and a bank specifying register BP for holding positional data of a mapping region in the RAM 3 where the contents of the data memory RF are mapped and providing the positional data to the fourth bus BABUS. The RAM 3 has a memory cell array 31, a bank address control circuit 35 connected to the fourth bus BABUS, for generating a real address according to the contents of the bank specifying register BP (BP0, BP1), and a selection circuit 37 for selecting the real address generated by the bank address control circuit 35, or the address provided through the second bus ABUS.

The present invention provides a method for dealing with the carrier conflict between the main card and subordinate card of a single-chip dual-card-dual-standby mobile phone, which includes a set one set of antenna, RF module and baseband processing chip and further comprises a radio resource adapter layer provided between the RRC layer and the physical layer. The RRC module calculates the position of the carriers of the main card and the subordinate card. The radio resource adapter layer determines the relative position between the carriers of main card and subordinate card so as to determine the type of the conflict, set priority levels to the services of the main card and subordinate card, and process the services according to the priority levels so as to avoid the conflict.

A battery-powered miniature wireless headset is worn as a single earring or as a pair of earrings. The headset communicates with a phone or other host over a bidirectional wireless communication link allowing hands-free operation. The wireless earring headset is comprised of an electronics module (18), a speaker assembly (17), a microphone assembly (16), an antenna (68), a battery (62), user interface devices such as a switch (28) and LED (30), and an attachment means employing either a clamp or a pierced earring post (24) with clutch (26). The electronics module, which may be a single chip, comprises a wireless transceiver, a processor with associated memory, an audio codec, power supply electronics, and other components. In use the device is attached to the pinna of the wearer's ear (99) using either a clamp or a post inserted through a pinna piercing and secured by a clutch or nut. The clamp or post may be permanently attached to the device or removably attached using a magnetic or mechanical attachment means. The user positions the speaker inside of, or at the entrance to, the ear canal. The microphone is mounted in such a way that it points toward the user's mouth and may be positioned on a boom (22) to move it closer to the mouth.

The invention relates to GaN-based Single chip white light emitting diode epitaxial material comprising a substrate and also comprising an initial growth layer, an intrinsic GaN buffer layer, an n-type GaN layer, a stress relaxation layer, an InGaN multiple quantum well structure light emitting layer, a p-type AlGaN sandwich layer and a p-type GaN layer which grow in sequence on the substrate. Thestress relaxation layer is an InGaN/GaN superlattice stress modulation layer which comprises InGaN layers and GaN layers, which are grown alternatively; the InGaN layers and GaN layers have the growth cycle of 6-500 and the corresponding thickness of 10 nm to 3 Mum; and the In components in the InGaN layers are in the range of 1-35 percent. Because the stress-relaxed InGaN/GaN superlattice stressmodulation layer is added between the n-type GaN layer and a multiple quantum light emitting layer, the In segregation effect is strengthened, InGaN quantum dots with different components are formed,and the mixing of different-wave light emitted by the InGaN quantum dots realizes the white light emitting. The cost of the white light emitting diode is reduced radically, the light emitting efficiency and the light using efficiency are increased and the integral performance of the white light emitting diode is improved.

A smart flash drive has one or more levels of smart storage switches and a lower level of single-chip flash devices (SCFD's). A SCFD contains flash memory and controllers that perform low-level bad-block mapping and wear-leveling and logical-to-physical block mapping. The SCFD report their capacity, arrangement, and maximum wear-level count (WLC) and bad block number (BBN) to the upstream smart storage switch, which stores this information in a structure register. The smart storage switch selects the SCFD with the maximum BBN as the target and the SCFD with the lowest maximum WLC as the source of a swap for wear leveling when a WLC exceeds a threshold that rises over time. A top-level smart storage switch receives consolidated capacity, arrangement, WLC, and BBN information from lower-level smart storage switch. Data is striped and optionally scrambled by Redundant Array of Individual Disks (RAID) controllers in all levels of smart storage switches.

[Object] An object of the present invention is to mount both a RF circuit including an inductor formed therein and a digital circuit on a single chip.

[Means for Solving Problems] MOSFETs are formed on a semiconductor substrate 1 in regions isolated by an element isolation film 2. A plurality of low-permittivity insulator rods including a low-permittivity insulator embedded therein and penetrating a first interlevel dielectric film 4 to reach the internal of the silicon substrate are disposed in the RF circuit area 100. An inductor 40 is formed on the interlevel dielectric film in the RF circuit area by using multi-layered interconnects. A high-permeability isolation region in which a composite material including a mixture of high-permeability material and a low-permittivity material is formed in the region of the core of the inductor and periphery thereof.

The invention provides a test system and method for a single event effect of an SRAM (System Random Access Memory) type FPGA (Field Programmable Gate Array). The test system comprises a single chip microcomputer processor, an RS232 interface circuit, a USB (Universal Serial Bus) interface circuit, a test FPGA and a storage unit. The test system and method can be used for fault injection tests of a configuration memory and a BRAM (Battery Random Access Memory) of the SRAM type FPGA, and single event function interrupting detection, single event locking detection and single event turning detection including single event turning detection for a configuration storage region, the BRAM and a trigger of the SRAM type FPGA are realized. The invention has the advantages of simplicity in operation, entirety in detection, high accuracy, good real-time property and strong universality.

An RGB-Z sensor is implementable on a single IC chip. A beam splitter such as a hot mirror receives and separates incoming first and second spectral band optical energy from a target object into preferably RGB image components and preferably NIR Z components. The RGB image and Z components are detected by respective RGB and NIR pixel detector array regions, which output respective image data and Z data. The pixel size and array resolutions of these regions need not be equal, and both array regions may be formed on a common IC chip. A display using the image data can be augmented with Z data to help recognize a target object. The resultant structure combines optical efficiency of beam splitting with the simplicity of a single IC chip implementation. A method of using the single chip red, green, blue, distance (RGB-Z) sensor is also disclosed.

A printed wiring board includes a mounting portion on which a dual core processor including two processor cores in a single chip can be mounted, power supply lines, ground lines, and a first layered capacitor and a second layered capacitor that are independently provided for each of the processor cores, respectively. Accordingly, even when the electric potentials of the processor cores instantaneously drop, an instantaneous drop of the electric potential can be suppressed by action of the layered capacitors corresponding to the processor cores, respectively. In addition, even when the voltage of one of the processor cores varies, the variation in the voltage does not affect the other processor core, and thus malfunctioning does not occur.

An optical device includes, a first Mach-Zehnder modulator that produces a first output, and a second Mach-Zehnder modulator which produces a second output. A splitter couples the first and second Mach-Zehnder modulators. A combiner combines the first and second outputs. A phase shifter is coupled to the first and second Mach-Zehnder modulators. The first Mach-Zehnder modulator, second Mach-Zehnder modulator, splitter, combiner and the phase shifter are each formed as part of a single chip made of electro-optical material. Such two similar optical device integrated together with polarization combiner provide a two-polarization performance.

Motion/Saturation detection system and method for synthesizing high dynamic range motion blur free images from multiple captures, the system and method utilizing photocurrent estimation to reduce read noise and enhance dynamic range at the low illumination end, saturation detection to enhance dynamic range at the high illumination end, and motion blur detection to ensure the photocurrent estimation is not corrupted by motion. Motion blur detection also makes it possible to extend exposure time and to capture more images, which can be used to further enhance dynamic range at the low illumination end. The present invention operates completely locally, making it well suited for single chip digital camera implementations.

In an RF communication system, aspects for supporting cellular or wireless network and broadcast utilizing an integrated single chip cellular and broadcast silicon solution may comprise receiving in a mobile terminal, a plurality of cellular frequency band communications services and VHF/UHF band broadcast services in a single baseband processor IC within a mobile terminal. Cellular information associated with the cellular frequency band communications service, and VHF/UHF broadcast information associated with the VHF/UHF broadcast service may be processed by a cellular processing module and a VHF/UHF broadcast processing module, respectively, integrated within a single integrated circuit within the mobile terminal. The cellular processing module and the VHF/UHF broadcast processing module within the mobile terminal may operate independently of each other to separately process the cellular information and the VHF/UHF broadcast information without exchanging related information.

A media processor for performing audio, video, and system layer tasks on a fully programmable single-chip integrated processor chip. The present invention performs video compression/decompression, audio compression/decompression, video input and output scaling, video input and output processing for enhancement, and system layer functions. The media processor is a single IC semiconductor chip that is coupled to one or more memory chips, audio front-end chip, and optional I/O interface chips. The media processor is compromised of the following integrated on a single IC semiconductor: Video processor with a SIMD vector engine, audio processor, stream processor, system (host) processor, and video scalers, LUTs and hardware blender.

A Dynamic Digital Pre-Distortion (DDPD) system is disclosed to rapidly correct power amplifier (PA) non-linearity and memory effects. To perform pre-distortion, a DDPD engine predistorts an input signal in order to cancel PA nonlinearities as the signal is amplified by the PA. The DDPD engine is implemented as a composite of one linear filter and N-1 high order term linear filters. The bank of linear filters have programmable complex coefficients. To compute the coefficients, samples from the transmit path and a feedback path are captured, and covariance matrices A and B are computed using optimized hardware. After the covariance matrices are computed, Gaussian elimination processing may be employed to compute the coefficients. Mathematical and hardware optimizations may be employed to simplify and reduce the number of multiplication operands and other operations, which can enable the DDPD system to fit within a single chip.

Flash ROMs operate at a speed slower than that of a CPU. In order to raise the operating speed of a single-chip microcomputer, therefore, interleaving is adopted and a plurality of flash ROMs are operated alternately to obtain an apparent operating speed equivalent to that of a CPU. Read clock generating circuits are placed in close proximity to clock input pins of respective ones of the flash ROMs and supply the flash ROMs with read clocks obtained by dividing down the frequency of a system clock. Delay ascribable to wiring is eliminated from the read clocks as a result.

An image processing apparatus according to the present invention includes: a color and polarization obtaining section 101 including a single-chip color image capture element with a color mosaic filter and a patterned polarizer in which a number of polarizer units, of which the polarization transmission planes define mutually different angles, are arranged adjacent to each other within each single color pixel; a color information processing section 102 for getting average color intensity information by averaging the intensities of the light rays that have been transmitted through the polarizer units within each said single color pixel; and a polarization information processing section 103 for approximating, as a sinusoidal function, a relation between the intensity of light rays that have been transmitted through the polarizer units within each said single color pixel and the angles of the polarization transmission planes of the polarizer units.

A millimeter wave radio transceiver having all or substantially all of its components fabricated on a single chip or chipset of a small number of semiconductor chips. The chip or chipsets when mass produced is expected to make the price of millimeter wave radios comparable to many of the lower-priced microwave radios available today from low-cost foreign suppliers. Transceivers of the present invention operate in the range of about 1 Gbps to more than 10 Gbps. The transceiver of a preferred embodiment is designed to receive binary input data at an input data rate in 10.3125 Gbps and to transmit at a transmit data rate in of 10.3125 Gbps utilizing encoded three-bit data symbols on a millimeter carrier wave at a millimeter wave nominal carrier frequency in excess of 70 GHz.