428 results about "Logical block addressing" patented technology

A method for reducing write latency in a distributed file system. A write request that includes a volume identifier is received at a data management subsystem deployed on a node within a distributed storage system. The data management subsystem maps the volume identifier to a file system volume and maps the file system volume to a set of logical block addresses in a logical block device in a storage management subsystem deployed on the node. The storage management subsystem maps the logical block device to a metadata object for the logical block device on the node that is used to process the write request. The mapping of the file system volume to the set of logical block addresses in the logical block device enables co-locating the metadata object with the file system volume on the node, which reduces the write latency associated with processing the write request.

The invention relates to the technical field of data compression, and particularly discloses a method for realizing data compression in an RAID card and an RAID control chip, and the method comprises the following steps: S1, receiving a plurality of IO writing commands issued by a host, and obtaining the logic block address and length of each IO; s2, executing a merging operation on the plurality of IOs to generate a merged IO block; s3, performing a data compression operation on the merged IO block through a data compression engine to obtain compressed data; s4, establishing a mapping relation from a logic block address to a physical block address of the compressed data, and storing the mapping relation in a logic-to-physical mapping table; s5, the compressed data are written into a solid state disk through an RAID engine, and meanwhile, logic-to-physical mapping table metadata are stored persistently; s6, sending a recovery command or a zero-writing command to the solid state disk recovery space for the address space which is not used after compression; the problem that an existing SSD compression scheme is high in power consumption is solved, reliability is better, original user data content is closer, and the obtained compression effect is better.

The disclosure herein describes deduplicating data chunks using chunk objects. A batch of data chunks is obtained from an original data object and a hash value is calculated for each data chunk. A first duplicate data chunk is identified using the hash value and a hash map. A chunk logical block address (LBA) of a chunk object is assigned to the duplicate data chunk. Payload data of the duplicate data chunk is migrated from the original data object to the chunk object, and a chunk map is updated to map the chunk LBA to a physical sector address (PSA) of the migrated payload data on the chunk object. A hash entry is updated to map to the chunk object and the chunk LBA. An address map of the original data object is updated to map an LBA of the duplicate data chunk to the chunk object and the chunk LBA.

A storage node maintains storage objects that contain decoy datasets that are used to detect cyber-attacks. The decoy datasets may be deployed at logical block addresses (LBAs) including the first and last LBAs of the LBA range of the storage object. Real active data may be stored on the storage object with the decoy datasets. A cyber-attack is detected based on receipt of a suspicious IO command that accesses decoy data. Access to the decoy data may be detected by maintaining an IO access bitmap, calculating digital signatures of decoy datasets, or monitoring for decoy data that is marked for remote replication.

A method for use in a storage processor, comprising: receiving an I / O request that is associated with a logical block address; allocating a cache slot that corresponds to the logical block address, wherein allocating the cache slot includes: identifying a type of memory that is required to host the cache slot by using one or more configuration settings that are associated with the cache slot, identifying a cache slot that is both available and hosted in the identified type of memory, and assigning the identified cache slot to the logical block address; and executing the I / O request by using the allocated cache slot, wherein using the allocated cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command that is associated with the allocated cache slot.

The present application discloses methods of operating a memory system, memory systems, hosts, and memory controllers. An example method includes receiving a read command, the read command including a first logical block address (LBA); based on a first attribute identifier corresponding to a first mapping table block in a compressed mapping table, determining a first physical address corresponding to the first LBA in the first mapping table block, the compressed mapping table including a plurality of attribute identifiers, the plurality of attribute identifiers corresponding to different mapping table blocks in a logical-to-physical (L2P) mapping table, an attribute identifier indicating whether physical addresses in a corresponding mapping table block are continuous, and the first mapping table block being the mapping table block in which the first LBA is located; and performing a read operation on a memory device based on the first physical address.

The invention discloses a server and a hard disk medium error processing method, and relates to the technical field of servers, the server comprises a controller and a redundant array of independent disks connected with the controller, the redundant array of independent disks comprises a plurality of hard disks, and different data in the same strip is stored in the same sector of each hard disk. If the controller detects that the at least two hard disks have medium errors in the same target sector, the controller obtains a target logic block address corresponding to the target sector in the at least two hard disks, and for any one of the at least two hard disks, a new sector is redistributed for the target logic block address corresponding to the hard disk in a standby sector preset by the hard disk, and reconstructing the new sectors allocated to the at least two hard disks so as to enable the redundant array of independent disks to work normally. According to the method and the device, the waste of storage resources in the redundant array of independent disks caused by direct replacement of a new redundant array of independent disks is reduced, and the user experience is improved.

A storage device includes a memory storage region and a controller having a processor. The processor retrieves user data from the memory storage region using a physical block address corresponding to a logical block address (LBA), in response to a read command. The retrieved user data includes a first hash received through a host interface in a prior host data transmission. The processor further performs error correction on the user data to generate error-corrected user data. The processor further causes a cryptographic engine to produce a second hash of the error-corrected user data. The first hash is compared to the second hash associated with the error-corrected user data to determine a match result. A notification is generated in response to the match result.

A system and method for status reporting for a storage device. In some embodiments, the method includes: receiving, by a persistent storage device, a command, the command requesting a status associated with a first logical block address; determining the status; and sending a response to the command, the response including the status.

Embodiments of the present application provide a method, an apparatus, and a system for processing access to object storage, where the method includes: establishing, by a user host, a first mapping relationship between first attribute information and second attribute information in advance; in response to reception of a first data read request, determining a data management unit corresponding to an object to be read by the first data read request according to the first mapping relationship; determining a logical block address of the data management unit; and accessing the server-side cache or the local cache of the user host to acquire data of the logical block address based on an access protocol of block storage and the logical block address.

Provided is a method for writing data to a Solid State Disk (SSD), an apparatus and the SSD. According to the method, a Logical Block Address (LBA) of each of a plurality of pieces of written data stored into a target cache module is acquired to obtain a plurality of Logical Block Addresses (LBAs); the plurality of pieces of written data in the buffer is stored into a solid-state storage unit of the SSD; whether the plurality of LBAs are consecutive is determined to obtain a determination result. In a case where the determination result indicates that the plurality of LBAs are consecutive, a Physics Block Address (PBA) of each of the plurality of pieces of written data in the solid-state storage unit is acquired to obtain a plurality of PBAs and a target mapping table according to the plurality of LBAs and the plurality of PBAs is generated.

Embodiments of the present invention provide a data processing method, a device, and a storage medium. The method comprises: acquiring first access log information of a block device in a first time period, wherein the block device corresponds to a plurality of logical block addresses; determining a target grouping length on the basis of the first access log information so as to group the plurality of logical block addresses on the basis of the target grouping length to obtain a plurality of groups, wherein the logical block addresses in a same group have similar access behaviors; determining access feature values respectively corresponding to the plurality of groups; and on the basis of the access feature values respectively corresponding to the plurality of groups, determining cold and hot data categories respectively corresponding to the plurality of groups.

Non-sequential write commands in a shingled magnetic recording (SMR) drive are efficiently executed using a skip-bypass mode. When certain conditions are detected in the command history of the drive, the drive changes to the skip-bypass mode. In skip-bypass mode, data associated with the write commands are received into memory of the drive and written directly to a new SMR band in a sequential write operation, thereby bypassing storage in a media cache of the SMR drive. Prior to the sequential write operation, data associated with logical block addresses (LBAs) disposed between the LBAs referenced by the non-sequential write commands are read into the memory by a sequential read operation. The data associated with the non-sequential write commands can then be written, along with the data read in the sequential read operation, in a single sequential write operation to the new SMR band.

Methods, systems, and devices for zoned random write operations are described. A memory system may receive a set of write commands associated with respective logical block addresses (LBAs) that may be in a sequential order, where the respective LBAs may be associated with a zone. The memory system may write first data to a first physical block address (PBA), where the first data may be associated with a first LBA of the respective LBAs. The memory system may determine whether a second LBA associated with second data is sequential relative to a write pointer associated with the zone. The memory system may write the second data to a second PBA that may be sequential to the first PBA in response to determining that the second logical block address is non-sequential relative to the write pointer and on a value of a bitmap corresponding to the second LBA.

Methods, systems, and devices for compressed logical-to-physical mapping for sequentially stored data are described. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block address generated by a host device to physical addresses of the memory device. The memory device may determine whether all of the entries of a terminal logical-to-physical mapping table are consecutive physical addresses. In response to determining that all of the entries contain consecutive physical addresses, the memory device may store a starting physical address of the consecutive physical addresses as an entry in a higher-level table along with a flag indicating that the entry points directly to data in the memory device rather than pointing to a terminal logical-to-physical mapping table. The memory device may, for subsequent reads of data stored in one or more of the consecutive physical addresses, bypass the terminal table to read the data.

The invention relates to a memory access method and device, computer equipment and a storage medium. The method comprises the following steps: determining a plurality of non-uniform memory access nodes, and allocating resources for the non-uniform memory access nodes; dividing a storage object in the storage system to obtain a plurality of data segments; binding the plurality of data segments with the plurality of non-uniform memory access nodes in sequence; and in response to a received data access request, obtaining a logic block address of the data access request, and determining a target data segment corresponding to the data access request according to the logic block address, so as to perform memory access through a target non-uniform memory access node corresponding to the target data segment. By adopting the method, cross-node access to the memory can be avoided, and meanwhile, the problem that computing resources and memory resources cannot be fully used or a wooden barrel effect exists in the performance of a storage system in an existing scheme is solved.

A storage device provides thin provisioning by presenting more logical capacity than available physical capacity. The storage device uses a dynamic random-access memory (DRAM) having a size that is proportional to the available physical capacity of the storage device. The storage device includes a memory device with a physical capacity and the DRAM. A controller on the storage device creates segments including logical block address (LBA) sets in an LBA space. The LBA sets include an LBA from each segment that are linked to enable the LBAs in a LBA set to share a mapping space in the DRAM. The controller also creates an L2P table including a LBA set entry per LBA set, with each LBA set entry including sub-entries to store physical locations on the memory device that are associated with the LBAs in the LBA set. The controller also stores the L2P table in the DRAM.

A shingled magnetic recording (SMR) hard disk drive (HDD) receives a read command for data associated with a range of logical block addresses (LBAs). In situations where a first portion of valid data associated with the range of LBAs is stored in an SMR region of the HDD and a second portion of valid data associated with the range of LBAs is stored in a non-SMR region of the HDD, the first portion is read from the SMR region in a single disk access and copied to a first buffer of the HDD, and the second portion is read from the non-SMR region in one or more disk accesses and copied to a second buffer of the HDD. The valid data associated with the range of LBAs stored in the second buffer are copied to the first buffer to be combined with valid data associated with the range of LBAs stored in the first buffer, and the combined valid data is then transferred to the host to complete execution of the read command.

The invention relates to a compressed logic-to-physical mapping for sequentially stored data. A memory device may use a hierarchical set of logical-to-physical mapping tables for mapping logical block addresses generated by a host device to physical addresses of the memory device. The memory device may determine whether all entries of a terminal logical-to-physical mapping table are contiguous physical addresses. In response to determining that all entries contain contiguous physical addresses, a memory device may store a starting physical address of the contiguous physical addresses as an entry in a higher level table along with a flag indicating that the entry directly points to data in the memory device rather than a terminal logic-to-physical mapping table. For a subsequent read of data stored in one or more of the contiguous physical addresses, the memory device may read the data across a terminal table.

A method is described. The method includes constructing a bitmap having a first dimension organized into bins of logical block addresses (LBA bins) and a second dimension organized into bins of physical block addresses (PBA bins). Coordinates of the bitmap indicate whether respective physical blocks of non volatile memory within one or more SSDs that fall within a particular PBA bin are being mapped to by an LBA that falls within a particular one of the LBA bins. The method includes using the bitmap during a rebuild of an LBA bin of an LBA / PBA table to avoid reading meta data for physical blocks that are not mapped to by an LBA that falls within the LBA bin.

The invention discloses a storage control method and storage equipment, relates to the technical field of storage, and aims to solve the problem of how to improve data processing efficiency. The storage control method comprises the steps that in response to a control instruction, a source physical block address corresponding to a source logic block address contained in the control instruction is obtained by querying a mapping table; the mapping table stores a mapping relationship between each logical block address and each physical block address. And modifying a target physical block address corresponding to the target logic block address in the mapping table into a source physical block address corresponding to the source logic block address. Therefore, on the host side, the to-be-processed data corresponding to the source physical block address is migrated to the target physical block address. The to-be-processed data is not transmitted between the host and the storage device, so that the data processing efficiency is improved.

Methods for recording commands in memory and providing the recorded commands. In one embodiment, a data storage controller includes a memory interface configured to interface with a memory, a controller memory including a storage firmware and a record mapping table, and a processor. The processor, when executing the storage firmware, is configured to receive a record identifier, receive a command including data to be stored in the memory, and create an entry in the record mapping table associating the record identifier with a logical block address of the command. The command is received after the record identifier. The processor may receive a playback identifier that includes the record identifier and determine, using the record mapping table, a location of the associated command in the memory. The command is provided to an external device.

The application provides a monitoring method, device and equipment for a ufs test case and a storage medium, which are applied to a ufs verification platform, the ufs verification platform is connected to a to-be-tested device installed with ufs, the method comprises the following steps: the ufs verification platform generates at least one target instruction based on the ufs test case, sends all the target instructions to the to-be-tested device in sequence, and the to-be-tested device performs target testing based on the target instruction; the ufs verification platform writes all the target instructions and related information into a record file, wherein the related information comprises a logical unit number, a logical block address and a block number of the target instruction; the ufs verification platform generates an end signal and sends the end signal to the to-be-tested device and the record file respectively, the to-be-tested device terminates the target testing, the ufs test case is terminated, and the record file terminates writing. According to the technical scheme of the embodiment of the application, all the target instructions and related information can be recorded, so that the troubleshooting speed and efficiency of the ufs test result are improved.

In some implementations, a memory apparatus may receive a command indicating a logical block address (LBA) that is associated with a logical-to-physical (L2P) table. The memory apparatus may perform a lookup operation associated with a compressed version of an address range of the L2P table to identify a physical address in non-volatile memory associated with the LBA, wherein the compressed version is stored in a volatile memory of the memory apparatus, wherein the compressed version is associated with an exception list that indicates physical addresses for respective LBAs, included in the address range, that are associated with non-sequential physical addresses, and wherein the compressed version is associated with a binary tree that indicates locations in the exception list associated with the respective LBAs. The memory apparatus may perform, based on the command, an action associated with the physical address.

The invention discloses a quick-positioning storage pressure test method and a storage medium thereof.The method comprises the steps that a write-in command is received, a test data packet is obtained, and the test data packet is provided with an initial logic block address, a write-in block number, a logic unit and a check value; the control unit performs verification operation according to the initial logic block address and the verification value in combination with a preset verification level and the verification level determined by the logic unit to obtain a verification result; when the verification result is successful, executing a write operation according to the initial logic block address and the write block number; and when the verification result is failure, storing a state log of the write-in operation, stopping executing the write-in operation, and outputting positioning information according to the logic unit, the verification result and the state log. Through the verification operation combining the initial logic block address and the verification value, data verification can be rapidly carried out, rapid positioning can be carried out under the condition of data errors and abnormities, and the accuracy and the test efficiency of the storage pressure test are improved.

The invention relates to the technical field of solid state disks, and discloses a data downswiping management method and device, equipment and a storage medium. The data downwriting management method comprises the following steps: receiving a write request of a logic partition supporting random writing; applying for a data buffer area and a cache basic management unit; receiving write request data corresponding to the write request, and writing the write request data into the data buffer area based on the cache basic management unit; judging whether the write request triggers implicit lower refreshing or not; if the implicit down-brushing is triggered, writing the write request data information in the down-brushing range in the pre-down-brushing area into the down-brushing area according to the size sequence of the logic block addresses; and if the implicit down-brushing is not triggered, writing the write request data information into the pre-down-brushing area. According to the method and the device, the write request of the ZRWA region can be quickly responded, so that the random write performance of the ZRWA region is equivalent to the sequential write performance of the ZNS, and the write performance of the ZRWA region is prevented from being reduced.

A memory control unit of a memory device includes at least one hardware processor; and memory storing instructions that cause the at least one hardware processor to perform operations comprising: generating a scrambler seed and a logical block address (LBA) for a block of write data received by the memory control unit from a host device; generating a flash translation layer (FTL) to map the LBA to a physical address (PA); scrambling the block of data using the scrambler seed; encrypting the scrambler seed, the LBA, and the PA in the FTL using an encryption key; initiating writing a scrambled block of data and encrypted LBA and scrambler seed to a memory array; and decrypting the FTL using an incorrect encryption key in response to an erase command received by the memory control unit from the host device.

An input / output (I / O) erase request directed at memory devices is received by a processing device. The erase request includes logical block address that is associated with a data object. The memory devices include groups of zones corresponding to sequential logical addresses. The plurality of zones are associated with a compound data object that includes a plurality of data objects, including the data object. One or more zones associated with the data object are identified. A data set counter associated with each of the one or more zones is decremented. The data set counter represents a number of sets of data associated with the zone. Responsive to determining that the data set counter associated with one of the one or more ones satisfies a criterion, the one of the one or more zones is a caused to be erased.

A processing device includes a plurality of cores coupled to a memory device that stores data. The cores execute a plurality of service applications that implement at least a portion of a flash translation layer (FTL) to direct operations to be performed by the memory device with reference to the data while tracking translations between a logical block address space to a physical address space. The cores also execute an FTL service framework that includes a plurality of application programming interfaces (APIs), wherein the plurality of APIs are configured to standardize communication between the plurality of service applications across the plurality of cores during runtime operation of the plurality of cores.

A method, performed by pointer fetch circuitry, includes buffering, in a pointer buffer of host interface circuitry, pointers associated with chop commands of a logical block address read command residing in a submission queue of a host system. The method includes sending address translation requests to an address translation circuit for respective translation units of respective chop commands, each translation unit includes a subset of the pointers. The method includes detecting an address translation request miss at a cache of the address translation circuit for a translation unit of a chop command. The method includes sending a translation miss message to a page request interface (PRI) handler. The translation miss message contains a virtual address of the translation unit and a restart point for the chop command, the translation miss message to trigger the PRI handler to send a page miss request to a translation agent of the host system.