243 results about "Flash memory controller" patented technology

The invention relates to the technical field of cores, and discloses a method and a system for realizing USB flash disk equipment interaction based on a flash memory encryption technology, which comprises the following steps of: dividing an encryptable data block of a flash memory controller, and determining a dynamic entropy weight of the encryptable data block by utilizing an equipment interaction instruction and a random noise characteristic signal; generating a self-adaptive key generation sequence capable of encrypting data blocks through an address allocation mode and a dynamic entropy weight of a flash memory controller; calculating a side channel leakage risk index of the flash memory controller, and setting a security level label of an encryptable data block in combination with a self-adaptive key generation sequence; the method comprises the following steps: setting a differentiated security protection mechanism of an encipherable data block by constructing an access control matrix of the encipherable data block and an encryption risk area of a flash memory controller; and generating a secure interaction scheme of the USB flash disk equipment based on the self-adaptive key generation sequence in combination with the differential security protection mechanism and the access control matrix. According to the invention, the interaction safety and reliability of the USB flash disk equipment can be improved.

The invention relates to the field of equipment safety verification, in particular to a wifi router on-line upgrading safety verification method and a wifi router on-line upgrading safety verification system. A wifi router online upgrade security verification system comprises a firmware package construction module, a firmware package verification module and a guarantee activation module. According to the method, a firmware packet header protection logic closed loop is formed through an innovatively designed multi-order composite verification structural body and an anti-offset signature positioning framework; the system can detect the nanoscale tampering of an attacker to the length identification field in real time, cuts off the power supply of the flash memory controller and erases the data buffer area at the hardware fusing level response speed when verification fails, and compared with a traditional scheme, the response efficiency is improved.

The present invention provides a control method of a flash memory controller. The control method includes: after the flash memory controller is powered on, determining whether the flash memory controller encountered an abnormal power failure; if the flash memory controller encounters the abnormal power failure, determining a first block of a flash memory module having an open state; moving a portion of valid data within the first block to a specific block; setting the first block to have a close state; determining if a number of blank blocks within the flash memory module is less than a threshold value; and if the number of blank blocks within the flash memory module is less than the threshold value, selecting a second block having the close state and a lowest number of valid pages, and moving all valid data of the second block into the specific block.

A control method of a memory device includes: controlling a flash memory controller to transmit a command to a flash memory module; determining whether the flash memory controller is in an idle state; in response to the flash memory controller being in the idle state, determining whether an idle time of the idle state exceeds a threshold value, wherein the threshold value is less than a time required for the flash memory module to complete executing a write command or an erase command; and in response to the idle time exceeding the threshold value, controlling the flash memory controller to enter a power saving mode to turn off a part of components in the flash memory controller.

The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read a first logical page of a physical page of the flash memory module to obtain first readout information, second readout information and third readout information, respectively; decoding the first readout information, the second readout information and the third readout information to generate decoded data of the first logical page; and generating a LLR mapping table according to the decode data of the first logical page, the first readout information, the second readout information and the third readout information, for use when reading and decoding other logical pages.

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention provides a method and device for testing the randomization effect of a flash memory controller, equipment and a medium, and relates to the technical field of storage. The method for testing the randomization effect of the flash memory controller comprises the following steps of: randomizing different original data, writing the randomized data into different types of data pages of a flash memory device, and reading and caching the data from the different types of data pages to obtain cached data of the different types of data pages; according to a preset state data generation rule and a bit reading sequence, performing combination processing on different cache data to obtain multiple types of state data; performing statistical calculation on the quantity of the state data of each type to obtain a quantity ratio of the state data of each type; and finally, calculating and comparing the quantity ratio, and judging the randomization effect of the flash memory controller. According to the method, reliable reference can be provided for evaluating the randomization effect of the flash memory controller by directly counting the quantity ratio of each type of state data in the flash memory device.

The invention provides a storage device, an electronic device, a data storage method and a storage medium, and relates to the technical field of data processing, the storage device comprises a CXL interface module, a dynamic memory module, a flash memory module and a flash memory controller module; wherein the dynamic memory module comprises a plurality of device side periodic regions, the flash memory module comprises a plurality of data placement units, and the device side periodic regions are in one-to-one correspondence with the data placement units; the CXL interface module is used for receiving host data from the host side periodic region and temporarily storing the host data in the equipment side periodic region corresponding to the host side periodic region in the dynamic memory module; the dynamic memory module is used for packaging the host data in the equipment side periodic region after preset time; and the flash memory controller module is used for storing the encapsulated host data into a data placement unit corresponding to the equipment side periodic region in the flash memory module. The storage device effectively improves the write amplification phenomenon.

The invention provides a flash memory controller and a control method of the flash memory controller, after the flash memory controller completes power-on reset, a host side controller issues configuration information and an instruction of a register to the flash memory controller, and the instruction is written into an instruction cache; reading the instruction from the instruction cache, and decoding an operation code, an instruction weight and a command index corresponding to the instruction according to an instruction format; the weighted arbiter arbitrates and outputs instruction indexes from the instruction queues of all the states according to the weights, and the instruction indexes are stored in a command index buffer in the flash memory controller; and reading the instruction index from the instruction index buffer, and completing the reading of the command word according to the instruction index in the instruction corresponding to the instruction index. By customizing the instruction format, the weighted scheduling of different operations of the flash memory controller can be realized, the response sequence of each instruction of the arbiter can be dynamically adjusted by changing the weight value in the instruction code, and the quick response and dynamic scheduling of high-priority instructions can be realized.

The present invention provides a method for controlling a flash memory module. The flash memory module includes a plurality of dies, each die includes a plurality of blocks, each block includes a plurality of pages, and the method includes the steps of: selecting a super block, wherein the super block includes a plurality of first blocks respectively located in the plurality of dies; for each first block in the super block, determining whether the first block is a full block or a blank block; and if the first block is not the full block or the blank block, writing dummy data to the first block so that the first block becomes the full block; and erasing the plurality of first blocks in the super block, so that the plurality of first blocks become a plurality of blank blocks.

The invention discloses a pointer-based data filling dynamic control method and system, the number of times of calling a preset interface by a flash memory controller is reduced through a flash memory cache built-in mapping table, in addition, the setting of writing a small data volume into a first flash memory storage area cache and then writing a large data volume into a second flash memory storage area is adopted, and the data filling dynamic control efficiency is improved. Therefore, the quantity of the filling data required to be filled in the data filling operation link of the single write operation is greatly reduced, so that the data volume of the data written into the storage interval of the flash memory by the host cache is reduced, the utilization rate of the bandwidth resource of the preset interface is improved, and the problem of write amplification is effectively controlled.

The invention discloses a high-efficiency solid state disk master control chip, which relates to the technical field of solid state disk master control chips, and comprises a central processing unit and a flash memory controller, the flash memory controller comprises a communication module, a flash memory control circuit and a comparison circuit; in the invention, in performance, data bus and instruction processing are optimized, read-write is accelerated, delay is reduced, and high-speed storage requirements are met; in the aspect of data, the flash memory control circuit accurately reads and writes, the comparison circuit corrects errors in real time, data reliability is guaranteed, and the problem of flash memory management is avoided; during bad block detection, factory leaving and newly-added bad blocks are accurately judged by means of multiple means such as specific verification data after all pieces are erased, and the central processing unit intelligently judges, saves time and improves efficiency; in hardware collaboration, a data selector intelligently switches paths, static random access and a memory guarantee data stability, a main state machine accurately controls a time sequence, stability is enhanced, and a high-quality storage scheme is provided for the solid state disk.

A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.

A flash memory controller, to be coupled between a host device and a flash memory module, includes an error correction code (ECC) circuit. The ECC circuit performs a wordline-dimensional ECC operation upon specific data, sent from the host device to form a super block stored within the flash memory module, to generate wordline-dimensional parity data and performs a finger-dimensional ECC operation upon the specific data generate finger-dimensional parity data. The ECC circuit corrects an error of the superblock by using the wordline-dimensional parity data and the finger-dimensional parity data so as to obtain correct data content of the specific data.

The invention provides an MCU controller. The MCU controller comprises a kernel, a read-only memory, a read-write memory, a register, a flash memory controller and a flash memory, the read-only memory and the read-write memory store different data types and different mapping addresses; the kernel is respectively connected with the read-only memory, the read-write memory and the register through a plurality of buses, and the plurality of buses are separated and parallel; the flash memory controller is connected with the read-only memory and the read-write memory, and the flash memory controller is switched between the bus master device and the bus slave device; when the flash memory controller is switched to the bus master device, the flash memory controller transmits the data to be transmitted from the flash memory to the read-write memory; when the flash memory controller is switched to a bus slave device, the kernel performs read-write operation on the register; parallel access of instructions, data and external data is achieved through separated bus interfaces, and the system efficiency is improved; the dynamic master-slave switching of the flash memory controller optimizes the starting efficiency and the flexibility during operation.

A decoding method includes: receiving and storing input data as a channel value in a channel value memory in a form of codeword; generating a posterior probability and a variable-to-check message according to a specific chunk of the channel value; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; using a check node unit to generate a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; determining whether to flip at least one bit of the specific chunk according to the posterior probability; and, determining whether to ignore and skip execution of decoding calculation for the specific chunk in a next iterative decoding operation according to whether a decoding calculation result in a current iterative decoding operation matches with a specific condition.

The invention discloses a solid state disk pre-reading method and a solid state disk. The method is applied to a solid state disk controller, and comprises the following steps: receiving a first read instruction sent by a host; determining a pre-read data volume of the first read instruction according to the state information of the solid state disk; determining a first pre-read address interval based on a first read address interval in the first read instruction and a pre-read data volume, generating a pre-read instruction according to the first pre-read address interval, sending the pre-read instruction to a flash memory controller to read first pre-read data, and storing the first pre-read data in an internal cache; receiving a second read instruction sent by the host, wherein an address intersection exists between a second read address interval in the second read instruction and the first pre-read address interval; and responding to the second read instruction according to the first pre-read data and the address intersection. Through the scheme provided by the embodiment, the host read delay of the SSD can be reduced, and the influence of the pre-read operation on the effective bandwidth of the SSD is reduced.

The invention relates to the technical field of cross of storage controllers and artificial intelligence acceleration, and discloses a large model reasoning system and method based on combination of a flash memory controller and an NPU (Network Processing Unit), and the large model reasoning system comprises the flash memory controller, the NPU and a flash memory array, the flash memory controller integrates a host interface module, a flash memory interface module, an independent AI acceleration interface module and an AI management engine, and the AI management engine autonomously completes NPU initialization, model weight direct loading, KV Cache hierarchical management, RAG knowledge base retrieval and model switching; the flash memory array is divided into a firmware partition, an AI special partition and a user storage partition, and different data storage requirements are met. According to the method, large model reasoning with low delay and low CPU dependence can be realized, and the model loading delay is reduced from 5-30 seconds to lt; after 500 milliseconds, the CPU occupancy rate of the host is reduced from 15-25% to lt; 2%, and concurrent operation of 4-8 models is supported. According to the invention, integration of storage and calculation is realized, and edge end, data center and mobile equipment scenes are adapted.

The invention discloses a flash memory controller and a flash memory access method. The flash memory controller includes a decoder that performs a decoding operation based on received information obtained by the flash memory and a parity check matrix of a quasi-cyclic low-density parity check code. The decoder comprises a variable node module, a V2C shift module and a check node module which are coupled in series. The decoder further comprises a state data shifting module which is used for circularly shifting the state data of the check node module and then feeding back the state data to the check node module, and the state data shifting module is coupled with the check node module in parallel. The serial coupling only has three stages, so that the decoding iteration convergence speed is improved, and the flash memory access efficiency is further improved.

The invention provides an intelligent interactive display control method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining preset boot animation data stored in a flash memory after a vehicle is powered on; sending the preset boot animation data and a first playing instruction to a lamp panel; wherein when the lamp panel receives the first playing instruction, a pre-stored animation corresponding to the preset boot animation data is played. The preset startup animation data stored in the flash memory controller is transmitted to the lamp panel, so that the time for waiting for the vehicle body controller to work is avoided, the lamp panel can be quickly started to play animations, and the response speed is increased.

The invention provides a method for accessing a flash memory module, wherein the method includes the steps of: classifying multiple read retry tables into at least a first group and a second group to establish a classifying and sorting table, wherein each of the multiple read retry tables records at least one reading voltage, and any two read retry tables do not have exactly the same reading voltage; selecting a first read retry table from the first group to read a page of a block of the flash memory module to generate first read data; and when a decoder fails to decode the first read data, selecting a second read retry table from the first group to read the page of the block of the flash memory module to generate second read data for the decoder to decode.

The present invention provides a fractional frequency divider, wherein the fractional frequency divider includes a plurality of registers, a counter, a control signal generator and a clock gating circuit. Regarding the plurality of registers, at least a portion of the registers are set to have values The counter is configured to sequentially generate a plurality of counter values, wherein the plurality of counter values correspond to the at least a portion of the registers, respectively, and the plurality of counter values are generated repeatedly The control signal generator is configured to generate a control signal based on the received counter value and the value of the corresponding register. The clock gating circuit is configured to refer to the control signal to mask or not mask an input clock signal to generate an output clock signal.

The present invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency divider includes a plurality of registers, a counter, a control signal generator, and a clock gating circuit. With respect to the plurality of registers, at least a portion of the plurality of registers is set to have a value. The counter is configured to sequentially generate a plurality of count values, wherein the plurality of count values ​​respectively correspond to the at least a portion of the registers, and the plurality of count values ​​are repeatedly generated. The control signal generator is configured to generate a control signal based on the received count value and the corresponding register value. The clock gating circuit is configured to mask or unmask an input clock signal based on the control signal to generate an output clock signal.

A flash controller of an information processing device regularly implements data read for each of block groups corresponding to ellipses 150, 152, and 154 across channels ch0 to ch3 of a flash memory. Read is tried at varied read voltages until data with an error rate which is equal to or lower than a threshold can be read, and a read voltage that is obtained in the end is stored in the memory. At the time of normal data read, data is read by using a read voltage associated with a target block.

The application discloses a NorFlash memory controller supporting AHB protocol, an FPGA module and a NorFlash memory. The FPGA module is composed of an AHB bus protocol conversion module AHB_MUX, an AHB slave device configuration module AHB_SLAVE, a NorFlash memory top layer control module AHB_FLASH_TOP, a NorFlash memory page write control module AHB_PAGE_WRITE, a NorFlash memory data read control module FLASH_READ and an SPI driving module SPI_MASTER. The NorFlash memory controller supporting AHB protocol has high reliability and is fully compatible with the information storage requirements of current mainstream embedded CPUs.

The present invention relates to a computer-readable storage medium, a method and an apparatus for writing data into a flash memory. The method for writing data into the flash memory is executed by a main processing unit of a flash memory controller and includes: generating a front-end parameter set, a middle-end parameter set, and a back-end parameter set for each item of data writing; transmitting the front-end parameter set of each item to a routing engine so that the routing engine drives a host interface according to the content of the front-end parameter set; transmitting the middle-end parameter set of each item to an accelerator so that the accelerator drives a redundant array of independent disks (RAID) engine according to the content of the middle-end parameter set; and transmitting the back-end parameter set of each item to the accelerator so that the accelerator drives a data access engine according to the content of the back-end parameter set. Through the setting of an exclusive routing engine and accelerator, the main processing unit does not need to supervise the operation of the entire data writing data stream, improving the overall performance of the system.

The invention relates to a decoder circuit, a decoding method and a flash memory controller. The decoding method comprises: generating or updating a variable-check message and generating a log likelihood ratio according to a channel value; generating a converted variable-check message according to the variable-check message; generating a check-variable message according to the converted variable-check message; generating a converted check-variable message according to the check-variable message, and updating the variable-check message and updating the log likelihood ratio based on the converted check-variable message; performing a hard decision operation according to the logarithmic likelihood ratio to determine whether to flip within a particular codeword to generate an output codeword; providing a memory circuit to store the generated output code word; and comparing the reference value with the hard decision result to generate a difference value, and selectively writing the hard decision result value into the memory circuit according to the difference value, thereby reducing the read-write times.

An embodiment of the present application provides a descriptor scheduling method, a flash memory controller, and a storage medium for a flash memory controller, belonging to the technical field of memory. The method includes generating task scheduling codes corresponding one by one to the initial descriptors according to power consumption indicators, performance indicators, and each initial descriptor; combining the task scheduling codes and the corresponding initial descriptors to obtain cache descriptors and storing them in a preset descriptor queue; within a task scheduling cycle, traversing each cache descriptor in the descriptor queue and respectively comparing the task scheduling codes in the traversed cache descriptors with the task scheduling codes of each execution descriptor in a preset task scheduling queue; when the result of the comparison indicates that the traversed cache descriptor and the execution descriptor in the task scheduling queue can both be processed in parallel, pushing it into the task scheduling queue. The embodiment of the present application can improve the operation efficiency of the flash memory while taking into account both the power consumption indicator and the performance indicator of the flash memory.

The invention discloses a memory device, a flash memory controller and a control method of the flash memory controller. The method comprises the following steps of: receiving a plurality of data from a main device; encoding the plurality of data to respectively generate a plurality of code words, wherein each code word comprises corresponding data and a check code; writing the plurality of code words into a data page of a block of a flash memory module; receiving a read command from the master device, wherein the read command requires to read the plurality of codewords stored in the data page; reading the plurality of code words from the data page; sequentially decoding the plurality of code words to generate a decoding result; and if the decoding result indicates that at least one of the code words cannot be successfully decoded, decoding the code words which are not successfully decoded by using the information of the code words which are successfully decoded.