87 results about "Flash memory controller" patented technology

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention relates to the technical field of cross of storage controllers and artificial intelligence acceleration, and discloses a large model reasoning system and method based on combination of a flash memory controller and an NPU (Network Processing Unit), and the large model reasoning system comprises the flash memory controller, the NPU and a flash memory array, the flash memory controller integrates a host interface module, a flash memory interface module, an independent AI acceleration interface module and an AI management engine, and the AI management engine autonomously completes NPU initialization, model weight direct loading, KV Cache hierarchical management, RAG knowledge base retrieval and model switching; the flash memory array is divided into a firmware partition, an AI special partition and a user storage partition, and different data storage requirements are met. According to the method, large model reasoning with low delay and low CPU dependence can be realized, and the model loading delay is reduced from 5-30 seconds to lt; after 500 milliseconds, the CPU occupancy rate of the host is reduced from 15-25% to lt; 2%, and concurrent operation of 4-8 models is supported. According to the invention, integration of storage and calculation is realized, and edge end, data center and mobile equipment scenes are adapted.

A flash controller of an information processing device regularly implements data read for each of block groups corresponding to ellipses 150, 152, and 154 across channels ch0 to ch3 of a flash memory. Read is tried at varied read voltages until data with an error rate which is equal to or lower than a threshold can be read, and a read voltage that is obtained in the end is stored in the memory. At the time of normal data read, data is read by using a read voltage associated with a target block.

The application discloses a NorFlash memory controller supporting AHB protocol, an FPGA module and a NorFlash memory. The FPGA module is composed of an AHB bus protocol conversion module AHB_MUX, an AHB slave device configuration module AHB_SLAVE, a NorFlash memory top layer control module AHB_FLASH_TOP, a NorFlash memory page write control module AHB_PAGE_WRITE, a NorFlash memory data read control module FLASH_READ and an SPI driving module SPI_MASTER. The NorFlash memory controller supporting AHB protocol has high reliability and is fully compatible with the information storage requirements of current mainstream embedded CPUs.

The invention discloses a memory device, a flash memory controller and a control method of the flash memory controller. The method comprises the following steps of: receiving a plurality of data from a main device; encoding the plurality of data to respectively generate a plurality of code words, wherein each code word comprises corresponding data and a check code; writing the plurality of code words into a data page of a block of a flash memory module; receiving a read command from the master device, wherein the read command requires to read the plurality of codewords stored in the data page; reading the plurality of code words from the data page; sequentially decoding the plurality of code words to generate a decoding result; and if the decoding result indicates that at least one of the code words cannot be successfully decoded, decoding the code words which are not successfully decoded by using the information of the code words which are successfully decoded.

A buffer management control device for use in a flash memory controller includes: a flag table and a flag management engine. The flag table is configured track availability status of a plurality of allocation units within a shared memory of the flash memory controller. The flag management engine is configured to assign one or more allocation units from the plurality of allocation units for buffering read data related to a host read command, and update the flag table according to the one or more assigned allocation units, thereby indicating that the one or more assigned allocation units are occupied.

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the flash memory module includes a plurality of blocks. The control method includes the steps of: obtaining a read count of a specific block; obtaining a time stamp of the specific block, wherein the time stamp is a write time of the specific block; calculating a time difference between a current system time and the time stamp of the specific block; and using the read count of the specific block and the time difference, and referring to a read count and threshold time mapping table to determine whether to arrange the specific block in a garbage collection pool.

Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller receives, from a submission queue, commands configured with a predefined field, wherein the predefined field includes a command identifier. The SSD is re-configured so that the controller receives, in a shared work queue, commands from processes executing on a host system. Each command is configured with the same predefined field (e.g., at the same Dword location according to the NVMe 2.0 specification), but the predefined field is repurposed so that its content includes at least a portion of an identifier for an address space (e.g., PASID) of the host system used by the process. Each command also may include a completion address and a phase bit.

The present disclosure relates to a method and device for enhancing read performance of an eMMC. The method is executed by a processing unit of a flash memory controller and comprises the following steps: (a) receiving an open-ended read command from a host device, wherein the parameters of the open-ended read command include a data address; (b) reading a first batch of data from a flash memory device according to the data address, storing it in a buffer, and during this process, monitoring the amount of data to identify when it reaches a threshold amount, at which point the amount of data is sent to the host device; (c) reading a second batch of data from the flash memory device and storing it in the buffer; and (d) checking if a stop command has been received, and if the check result is YES, terminating the execution of the open-ended read command.

The present invention provides a method for controlling a flash memory module. The method includes the steps of: after the flash memory module is powered on, determining whether the flash memory module encountered an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters the abnormal power failure before the flash memory module is powered on, determining a last super block written by the flash memory module before powering on, where the super block includes multiple first blocks; determining a last rewritten page of the super block; determining a check range of the super block according to the last written page of the super block; determining a data weak region of the super block by reading the pages of the check range; and moving data in the weak data region to other regions of the super block or to another super block.

A flash memory controller and a flash memory access method are provided. The flash memory controller comprises a decoder. The decoder is configured to perform a decoding operation based on a N×M base matrix of a LDPC code to decode the read information from a flash memory. The decoder comprises a controller, a variable node (VN) unit, and a check node (CN) unit. The controller is configured to transform the base matrix into a compressed matrix of size N×S, where S is smaller than M. The VN unit and the CN unit are configured to perform message updates between variable nodes and check nodes to generate decoding results that converge to a codeword. During each decoding cycle, the VN unit performs calculations on each column of the compressed matrix.

A flash memory controller and a method of performing a cache erase operation are disclosed. The flash memory controller includes a first interface circuit and a processor. The first interface circuit is coupled to a flash memory to transmit data and commands. The processor is coupled to the first interface circuit to access the flash memory. The processor controls the first interface circuit to transmit a first command sequence and a second command sequence to the flash memory. The first command sequence includes a first command and a second command. In response to the transmission of the second command, the flash memory performs an erase operation and transmits the second command sequence to the flash memory when an array ready bit is in a non-ready state. The present application can perform related operations that use a bus while performing an erase operation to improve transmission efficiency.

The invention discloses a flash memory controller which is used for accessing a flash memory module. The flash memory controller comprises a buffer memory, a microprocessor and a counter. A partial area of the buffer memory is used for temporarily storing write-read command program codes associated with processing write-in or read-out in system internal program codes. The counter generates a count value in response to the number of times the microprocessor continuously receives write or read commands. Wherein the microprocessor sets a partial area of the buffer memory as a non-holding memory, and after a sleep command is received and when a count value is greater than or equal to a pre-designed value, the microprocessor sets the partial area of the buffer memory as a holding memory, then the flash memory controller enters a power-saving mode, and the non-holding memory is closed. The invention further discloses a control method of the flash memory controller and an electronic device applying the control method.

The present invention relates to a control method of a flash memory controller, a flash memory controller and a storage device. In the control method of the flash memory controller, by establishing an active page count table, a detailed active page count table and / or a region active page count table according to a deallocation command from a host device, the flash memory controller can effectively and quickly determine whether any region does not have any active data, so that the flash memory controller can suggest the host device to transmit a reset command to reset the region, and in addition, after receiving the reset command from the host device, the flash memory controller can use a garbage collection operation or directly put the blocks corresponding to the erased region into a spare block pool for further use.

The invention discloses a hybrid flash memory reading optimization method based on reliability perception, which is characterized in that the reading performance optimization of a high-density flash memory is realized by adopting a method of migrating data on data pages with different characteristics to flash memory pages with different reliability for reading. According to the method, a heat classifier, an original bit error rate calculator and a read-reread counter of data pages are arranged in a flash memory controller to judge the characteristics of the data pages, and corresponding migration mechanisms are designed for data on the data pages with different characteristics, so that resource allocation of different reliability pages in a flash memory is adjusted; and the overall reading performance of the flash memory equipment is optimized. Compared with the prior art, the method has the advantages that the reading performance of the high-density flash memory is improved through the reading method capable of sensing the reliability of the data pages, the operation of repeated rereading in the reading process of the high-density flash memory is optimized, the delay overhead caused by a read retry mechanism is effectively reduced, and the method is simple and convenient, good in use effect and has a certain application prospect.

The invention discloses a method and a device for improving reading efficiency of an embedded multimedia card, the method is executed by a processing unit of a flash memory controller, and the method comprises the following steps: (a) receiving an open end reading command from a host device, and parameters of the open end reading command comprise a data address; (b) reading a first batch of data from a flash memory device in batches according to the data address, storing the first batch of data in a buffer memory, and transmitting the data with a threshold data volume to the host device when detecting that the data volume stored in the buffer memory reaches the threshold data volume every time in the process, wherein the threshold data volume is smaller than a batch of read data volume; (c) reading a second batch of data from the flash memory device and storing the second batch of data to the buffer memory; and (d) detecting whether a stop command of the host device is received, and if so, ending the execution of the open-end read command.

An operating method of a semiconductor device including a NOR type flash memory and a NAND type flash memory is improved. A flash memory includes a NOR type flash memory, a NAND type flash memory, a controller, and an internal bus connecting the NOR type flash memory and the NAND type flash memory to the controller. The controller controls the NOR type flash memory, or the NOR type flash memory and the NAND type flash memory based on a command received from an outside.

The invention discloses a flash memory controller, a solid state disk controller and electronic equipment, and belongs to the technical field of storage. The flash memory controller comprises a queue manager and a flash memory processor; the queue manager is coupled with the flash memory processor; the queue manager is used for managing a command queue aiming at a flash memory crystal grain, the command queue comprises a flash memory operation command to be executed, and the flash memory operation command comprises at least one of a cache reading command and a cache programming command; and the flash memory processor is used for executing the flash memory operation command.

The application provides a solid state storage device temperature control method, including a solid state disk master control chip of a multi-CPU core architecture, a front-end core Core0 periodically sampling solid state disk disc each part sensor temperature value, and calculating a composite temperature, sending the composite temperature to an auxiliary core mCore4; a back-end core Core2, Core3 real-time collecting respective working logical unit number quantity, and feeding back to the auxiliary core mCore4; the auxiliary core mCore4 accumulates and averages the sampling data, and detects whether the composite temperature exceeds a conditional threshold value, if exceeding the threshold value, then according to the actual load level and temperature grade adjustment logical unit number maximum concurrent number limit value; the back-end core Core2, Core3 gets the concurrent number limit value from the auxiliary core mCore4, and adjusts the flash memory controller. The application saves computing power and improves input and output performance, ensures that the solid state disk temperature and power consumption are limited without losing too much performance, and guarantees the accuracy and real-time of the maximum logical unit number concurrent number calculation result.

The invention discloses a memory device, a flash memory controller and a control method thereof, the flash memory controller is coupled to a main device and a flash memory module, and the flash memory controller is used for receiving a command from the main device to access the flash memory module; the control method comprises the following steps of: setting a first bandwidth for communicating with the main device; determining a reference data rate according to configuration information of the flash memory module; judging whether the first bandwidth far exceeds a required bandwidth according to the reference data rate; and setting a second bandwidth lower than the first bandwidth for communicating with the main device if it is determined that the first bandwidth is far beyond the required bandwidth.

A method and apparatus for reading from a flash memory device are disclosed. A regressive neural network (RNN) inference model is stored on a flash memory controller. The RNN inference model is configured to identify at least one threshold voltage offset read error (TVS-RE) curve, which identifies the number of errors dependent on a threshold voltage offset compensation (TVSO) value. Operation of the flash memory device is monitored to identify usage characteristic values. A neural network operation of the RNN inference model is performed to generate a TVS-RE curve corresponding to the usage characteristic value. The inputs to the neural network operation include the usage characteristic value. The minimum value corresponding to the TVS-RE curve is used to identify the TVSO value. A read from the flash memory device is performed using a threshold voltage offset read at the TVSO value.

Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller receives, from a submission queue, commands configured with a predefined field, wherein the predefined field includes a command identifier. The SSD is reconfigured so that the controller receives, in a shared work queue, commands from processes executing on a host system. Each command is configured with the same predefined field (e.g., at the same Dword location according to the NVMe 2.0 specification), but the predefined field is repurposed so that its content includes at least a portion of an identifier for an address space (e.g., PASID) of the host system used by the process. Each command also may include a completion address and a phase bit.

The present invention provides a method for controlling a flash memory module. The method includes the steps of: after the flash memory module is powered on, determining whether the flash memory module encountered an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters the abnormal power failure before the flash memory module is powered on, determining a last super block written by the flash memory module before powering on, where the super block includes multiple first blocks; determining a last rewritten page of the super block; determining a check range of the super block according to the last written page of the super block; determining a data weak region of the super block by reading the pages of the check range; and moving data in the weak data region to other regions of the super block or to another super block.

The application provides a timing calibration method and system for a serial flash memory device, comprising: a central processing unit controlling a flash memory controller to read first data from the serial flash memory device at a current operating frequency of the serial flash memory device according to a first sampling parameter saved by the central processing unit; then controlling the flash memory controller to adjust the current operating frequency of the serial flash memory device to a desired operating frequency input from outside; further controlling the flash memory controller to read second data from the serial flash memory device according to a second sampling parameter, and when the second data is inconsistent with the first data, continuously adjusting the second sampling parameter according to the desired operating frequency to delay the sampling time of the flash memory controller until the second data is consistent with the first data, and then saving the corresponding second sampling parameter. The beneficial effect is that the flash memory controller can support a higher upper limit of the clock frequency of the serial flash memory device, a wider clock frequency range, and more memory models.

The invention provides an embedded flash memory controller, a chip system and a computer readable storage medium, and belongs to the technical field of semiconductors. In the embedded flash memory controller, a cache module can continuously read and cache startup data with a fixed length in a first-in first-out cache mode under the control of a quick startup instruction, namely in a quick startup mode; and under the control of a non-quick start instruction, namely in a normal mode, reading and caching non-start data in a cache mode. Therefore, adaptive caching modes can be flexibly selected according to different scenes, the reading speed of the starting data is improved to ensure quick starting, and the reading speed of conventional non-starting data is optimized to ensure efficient operation. Therefore, the upper limit of the reading speed can be broken through, and the high-speed reading requirement of the chip is met.

This application discloses a computing device, system, and method based on memory expansion, relating to the field of computer technology. The device includes: flash memory, a flash memory controller, a data stream processing module, a sub-protocol multiplexing and arbitration module, a protocol controller, memory, and a memory controller. The flash memory stores file data, enabling direct file loading into memory within the computing device. The flash memory controller is connected to the data stream processing module via a data path. The flash memory controller acquires file read or write tasks sent by the host processor and initiates file read or write operations via a memory-mapped bus. The data stream processing module accesses the flash memory through the flash memory controller and / or accesses the memory through the memory controller according to the computing task. This shortens the data exchange path, improves the flexibility of computing tasks on memory data, avoids latency caused by frequent file loading, and improves computing efficiency.

This application discloses a flash memory controller and its data processing method. The method includes: acquiring input data; encoding the input data into a pulse sequence based on a preset pulse interval modulation strategy; wherein the width and duty cycle of the pulse sequence are within preset ranges; performing preset operations on a preset memory array based on the pulse sequence and outputting the operation results; wherein the preset operations are matrix multiplication-addition or convolution operations; and performing error correction processing on the operation results based on a preset error prediction model and outputting the target calculation result. Therefore, by encoding the input data into a pulse sequence that conforms to preset parameters and directly performing preset operations such as matrix multiplication-addition or convolution on a preset memory array, in-situ data computation is achieved, effectively reducing the frequent data transfer between storage units and computing units in traditional architectures, thereby significantly reducing energy consumption caused by data transmission.

The invention relates to a flash memory controller and a compensation method of the flash memory controller. The method includes: providing a first input / output interface for coupling between a host device and an internal bus; providing a second input / output interface for coupling between a flash memory device and the internal bus; providing a central processing unit to manage a plurality of flash memory operations; and when a preset value of a specific read reference voltage is applied, generating an offset value of the specific read reference voltage in response to at least one of a data retention time and a memory cell count of the flash memory device according to at least one feature model, and compensating the preset value of the specific read reference voltage as an actual optimal value.

A storage device may perform high-speed read data capture. The storage device includes a memory device to send parallel data (DQ) aligned with a burst of differential clock strobes (DQS). The memory device may support warm-up cycles. The storage device also includes a controller including a DQS receiver to receive the DQS and data clocked comparators to receive the DQ. At the beginning of a data output burst, the DQS receiver receives warm-up DQS cycles and forwards the DQS it receives during the warm-up DQS cycles to the data clocked comparators. Following a configured number of warm-up cycles, the data clocked comparators may receive the DQ that are aligned with the DQS received by the DQS receiver after the configured number of warm-up cycles. The data clocked comparators may capture the DQ and the aligned DQS to capture read data at a high speed.

The present invention provides a method for accessing a flash memory module, wherein the method includes the steps of: using a first set of threshold voltages, a positively adjusted first set of threshold voltages and a negatively adjusted first set of threshold voltages to read a first logical page of a physical page of the flash memory module to obtain first readout information, second readout information and third readout information, respectively; decoding the first readout information, the second readout information and the third readout information to generate decoded data of the first logical page; and generating a LLR mapping table according to the decode data of the first logical page, the first readout information, the second readout information and the third readout information, for use when reading and decoding other logical pages.