143 results about "Flash memory controller" patented technology

The invention relates to the technical field of cores, and discloses a method and a system for realizing USB flash disk equipment interaction based on a flash memory encryption technology, which comprises the following steps of: dividing an encryptable data block of a flash memory controller, and determining a dynamic entropy weight of the encryptable data block by utilizing an equipment interaction instruction and a random noise characteristic signal; generating a self-adaptive key generation sequence capable of encrypting data blocks through an address allocation mode and a dynamic entropy weight of a flash memory controller; calculating a side channel leakage risk index of the flash memory controller, and setting a security level label of an encryptable data block in combination with a self-adaptive key generation sequence; the method comprises the following steps: setting a differentiated security protection mechanism of an encipherable data block by constructing an access control matrix of the encipherable data block and an encryption risk area of a flash memory controller; and generating a secure interaction scheme of the USB flash disk equipment based on the self-adaptive key generation sequence in combination with the differential security protection mechanism and the access control matrix. According to the invention, the interaction safety and reliability of the USB flash disk equipment can be improved.

The invention relates to the field of equipment safety verification, in particular to a wifi router on-line upgrading safety verification method and a wifi router on-line upgrading safety verification system. A wifi router online upgrade security verification system comprises a firmware package construction module, a firmware package verification module and a guarantee activation module. According to the method, a firmware packet header protection logic closed loop is formed through an innovatively designed multi-order composite verification structural body and an anti-offset signature positioning framework; the system can detect the nanoscale tampering of an attacker to the length identification field in real time, cuts off the power supply of the flash memory controller and erases the data buffer area at the hardware fusing level response speed when verification fails, and compared with a traditional scheme, the response efficiency is improved.

The present invention provides a control method of a flash memory controller. The control method includes: after the flash memory controller is powered on, determining whether the flash memory controller encountered an abnormal power failure; if the flash memory controller encounters the abnormal power failure, determining a first block of a flash memory module having an open state; moving a portion of valid data within the first block to a specific block; setting the first block to have a close state; determining if a number of blank blocks within the flash memory module is less than a threshold value; and if the number of blank blocks within the flash memory module is less than the threshold value, selecting a second block having the close state and a lowest number of valid pages, and moving all valid data of the second block into the specific block.

The invention discloses a fast data protection method and device for SSD abnormal power failure, equipment and a medium, and relates to the field of SSDs, and the method comprises the steps: monitoring a power supply voltage, and generating an interrupt signal when the power supply voltage is lower than a preset threshold value; in response to the interrupt signal, turning off a power supply of a preset non-data path hardware module through the SSD controller; stopping scheduling all operation commands for the NAND flash memory through the SSD firmware, and emptying a data path in an NAND flash memory controller; writing the user data in the host write cache and the command information corresponding to the user data into a special physical address block reserved in the SSD in advance; after the SSD is powered on again, the address mapping table is recovered by scanning the write-in point in the NAND flash memory, the backup data and the command information in the special physical address block are read, and the backup data are written into the user data area according to the command information. According to the method, the key data backup time during abnormal power failure is shortened, the capacity requirement for the standby capacitor is reduced, and the problem that the cost is increased due to the fact that the backup time is too long is effectively solved.

The invention provides a storage device, an electronic device, a data storage method and a storage medium, and relates to the technical field of data processing, the storage device comprises a CXL interface module, a dynamic memory module, a flash memory module and a flash memory controller module; wherein the dynamic memory module comprises a plurality of device side periodic regions, the flash memory module comprises a plurality of data placement units, and the device side periodic regions are in one-to-one correspondence with the data placement units; the CXL interface module is used for receiving host data from the host side periodic region and temporarily storing the host data in the equipment side periodic region corresponding to the host side periodic region in the dynamic memory module; the dynamic memory module is used for packaging the host data in the equipment side periodic region after preset time; and the flash memory controller module is used for storing the encapsulated host data into a data placement unit corresponding to the equipment side periodic region in the flash memory module. The storage device effectively improves the write amplification phenomenon.

A decoding method includes: receiving and storing input data as a channel value in a channel value memory in a form of codeword; generating a posterior probability and a variable-to-check message according to a specific chunk of the channel value; converting the variable-to-check message from variable node domain into check node domain to generate a converted variable-to-check message; using a check node unit to generate a check-to-variable message according to the converted variable-to-check message; converting the check-to-variable message from check node domain into variable node domain to generate a converted check-to-variable message; determining whether to flip at least one bit of the specific chunk according to the posterior probability; and, determining whether to ignore and skip execution of decoding calculation for the specific chunk in a next iterative decoding operation according to whether a decoding calculation result in a current iterative decoding operation matches with a specific condition.

The invention discloses a solid state disk pre-reading method and a solid state disk. The method is applied to a solid state disk controller, and comprises the following steps: receiving a first read instruction sent by a host; determining a pre-read data volume of the first read instruction according to the state information of the solid state disk; determining a first pre-read address interval based on a first read address interval in the first read instruction and a pre-read data volume, generating a pre-read instruction according to the first pre-read address interval, sending the pre-read instruction to a flash memory controller to read first pre-read data, and storing the first pre-read data in an internal cache; receiving a second read instruction sent by the host, wherein an address intersection exists between a second read address interval in the second read instruction and the first pre-read address interval; and responding to the second read instruction according to the first pre-read data and the address intersection. Through the scheme provided by the embodiment, the host read delay of the SSD can be reduced, and the influence of the pre-read operation on the effective bandwidth of the SSD is reduced.

The invention relates to the technical field of cross of storage controllers and artificial intelligence acceleration, and discloses a large model reasoning system and method based on combination of a flash memory controller and an NPU (Network Processing Unit), and the large model reasoning system comprises the flash memory controller, the NPU and a flash memory array, the flash memory controller integrates a host interface module, a flash memory interface module, an independent AI acceleration interface module and an AI management engine, and the AI management engine autonomously completes NPU initialization, model weight direct loading, KV Cache hierarchical management, RAG knowledge base retrieval and model switching; the flash memory array is divided into a firmware partition, an AI special partition and a user storage partition, and different data storage requirements are met. According to the method, large model reasoning with low delay and low CPU dependence can be realized, and the model loading delay is reduced from 5-30 seconds to lt; after 500 milliseconds, the CPU occupancy rate of the host is reduced from 15-25% to lt; 2%, and concurrent operation of 4-8 models is supported. According to the invention, integration of storage and calculation is realized, and edge end, data center and mobile equipment scenes are adapted.

The invention discloses a flash memory controller and a flash memory access method. The flash memory controller includes a decoder that performs a decoding operation based on received information obtained by the flash memory and a parity check matrix of a quasi-cyclic low-density parity check code. The decoder comprises a variable node module, a V2C shift module and a check node module which are coupled in series. The decoder further comprises a state data shifting module which is used for circularly shifting the state data of the check node module and then feeding back the state data to the check node module, and the state data shifting module is coupled with the check node module in parallel. The serial coupling only has three stages, so that the decoding iteration convergence speed is improved, and the flash memory access efficiency is further improved.

The invention provides an intelligent interactive display control method and device, electronic equipment and a storage medium, and the method comprises the steps: obtaining preset boot animation data stored in a flash memory after a vehicle is powered on; sending the preset boot animation data and a first playing instruction to a lamp panel; wherein when the lamp panel receives the first playing instruction, a pre-stored animation corresponding to the preset boot animation data is played. The preset startup animation data stored in the flash memory controller is transmitted to the lamp panel, so that the time for waiting for the vehicle body controller to work is avoided, the lamp panel can be quickly started to play animations, and the response speed is increased.

The present invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency divider includes a plurality of registers, a counter, a control signal generator, and a clock gating circuit. With respect to the plurality of registers, at least a portion of the plurality of registers is set to have a value. The counter is configured to sequentially generate a plurality of count values, wherein the plurality of count values ​​respectively correspond to the at least a portion of the registers, and the plurality of count values ​​are repeatedly generated. The control signal generator is configured to generate a control signal based on the received count value and the corresponding register value. The clock gating circuit is configured to mask or unmask an input clock signal based on the control signal to generate an output clock signal.

A flash controller of an information processing device regularly implements data read for each of block groups corresponding to ellipses 150, 152, and 154 across channels ch0 to ch3 of a flash memory. Read is tried at varied read voltages until data with an error rate which is equal to or lower than a threshold can be read, and a read voltage that is obtained in the end is stored in the memory. At the time of normal data read, data is read by using a read voltage associated with a target block.

The application discloses a NorFlash memory controller supporting AHB protocol, an FPGA module and a NorFlash memory. The FPGA module is composed of an AHB bus protocol conversion module AHB_MUX, an AHB slave device configuration module AHB_SLAVE, a NorFlash memory top layer control module AHB_FLASH_TOP, a NorFlash memory page write control module AHB_PAGE_WRITE, a NorFlash memory data read control module FLASH_READ and an SPI driving module SPI_MASTER. The NorFlash memory controller supporting AHB protocol has high reliability and is fully compatible with the information storage requirements of current mainstream embedded CPUs.

The invention discloses a memory device, a flash memory controller and a control method of the flash memory controller. The method comprises the following steps of: receiving a plurality of data from a main device; encoding the plurality of data to respectively generate a plurality of code words, wherein each code word comprises corresponding data and a check code; writing the plurality of code words into a data page of a block of a flash memory module; receiving a read command from the master device, wherein the read command requires to read the plurality of codewords stored in the data page; reading the plurality of code words from the data page; sequentially decoding the plurality of code words to generate a decoding result; and if the decoding result indicates that at least one of the code words cannot be successfully decoded, decoding the code words which are not successfully decoded by using the information of the code words which are successfully decoded.

A buffer management control device for use in a flash memory controller includes: a flag table and a flag management engine. The flag table is configured track availability status of a plurality of allocation units within a shared memory of the flash memory controller. The flag management engine is configured to assign one or more allocation units from the plurality of allocation units for buffering read data related to a host read command, and update the flag table according to the one or more assigned allocation units, thereby indicating that the one or more assigned allocation units are occupied.

The invention relates to a non-integer frequency divider and a flash memory controller. The non-integer frequency eliminator comprises a plurality of temporary memories, a counter, a control signal generator and a clock pulse gating circuit. At least a portion of the plurality of registers is set to have a value with respect to the plurality of registers. The counter is used for sequentially generating a plurality of count values, the plurality of count values respectively correspond to the at least one part of the temporary register, and the plurality of count values are repeatedly generated. The control signal generator is used for generating a control signal according to the received count value and the value of the corresponding register. The clock gating circuit is used for referring to the control signal to shield or not shield an input clock signal so as to generate an output clock signal.

An encoding circuit applied in a flash memory controller includes an auxiliary data generating circuit and an encoder. In operation of the encoding circuit, the auxiliary data generating circuit receives a plurality of data blocks to generate auxiliary data of the plurality of data blocks, and the encoder encodes the plurality of data blocks according to a check code check matrix to generate a check code, and replaces a part of the check code with the auxiliary data to generate an adjusted check code, wherein the plurality of data blocks and the adjusted check code are written into a flash memory. The present application replaces dependent bits in the check code originally generated by the encoding circuit with auxiliary data having actual functions, so as to make full use of memory space to avoid waste of space, and further adds auxiliary data in the check code, so that the accuracy of the correctness / integrity check in the decoding process is higher.

The present invention provides a control method of a flash memory controller, wherein the flash memory controller is configured to access a flash memory module, and the flash memory module includes a plurality of blocks. The control method includes the steps of: obtaining a read count of a specific block; obtaining a time stamp of the specific block, wherein the time stamp is a write time of the specific block; calculating a time difference between a current system time and the time stamp of the specific block; and using the read count of the specific block and the time difference, and referring to a read count and threshold time mapping table to determine whether to arrange the specific block in a garbage collection pool.

Systems, methods, and apparatus related to shared work queue interfaces for memory devices. In one approach, an NVMe solid-state drive (SSD) includes flash memory. A controller receives, from a submission queue, commands configured with a predefined field, wherein the predefined field includes a command identifier. The SSD is re-configured so that the controller receives, in a shared work queue, commands from processes executing on a host system. Each command is configured with the same predefined field (e.g., at the same Dword location according to the NVMe 2.0 specification), but the predefined field is repurposed so that its content includes at least a portion of an identifier for an address space (e.g., PASID) of the host system used by the process. Each command also may include a completion address and a phase bit.

The invention provides a method for controlling a data storage device and a related flash memory controller. The present application relates to a method for controlling a data storage device (100). The data storage device (100) comprises a flash memory controller (11) and a flash memory module (12). The flash memory controller (11) has a first buffer memory (113) and a second buffer memory (114). The memory module (12) has at least a first memory portion (122) and a second memory portion (123). The method comprises: receiving first data from a host device (50); storing the first data in a first buffer memory (113); transferring the first data from the first buffer memory (113) to a first memory portion (122) of the flash memory module (12); and transferring the first data from the first buffer memory (113) to a host memory buffer (52) in the host device (50). The first data corresponds to at least a portion of second data to be written to the second memory portion (123).

The present disclosure relates to a method and device for enhancing read performance of an eMMC. The method is executed by a processing unit of a flash memory controller and comprises the following steps: (a) receiving an open-ended read command from a host device, wherein the parameters of the open-ended read command include a data address; (b) reading a first batch of data from a flash memory device according to the data address, storing it in a buffer, and during this process, monitoring the amount of data to identify when it reaches a threshold amount, at which point the amount of data is sent to the host device; (c) reading a second batch of data from the flash memory device and storing it in the buffer; and (d) checking if a stop command has been received, and if the check result is YES, terminating the execution of the open-ended read command.

The present invention provides a method for controlling a flash memory module. The method includes the steps of: after the flash memory module is powered on, determining whether the flash memory module encountered an abnormal power failure before the flash memory module is powered on; if the flash memory module encounters the abnormal power failure before the flash memory module is powered on, determining a last super block written by the flash memory module before powering on, where the super block includes multiple first blocks; determining a last rewritten page of the super block; determining a check range of the super block according to the last written page of the super block; determining a data weak region of the super block by reading the pages of the check range; and moving data in the weak data region to other regions of the super block or to another super block.

A flash memory controller and a flash memory access method are provided. The flash memory controller comprises a decoder. The decoder is configured to perform a decoding operation based on a N×M base matrix of a LDPC code to decode the read information from a flash memory. The decoder comprises a controller, a variable node (VN) unit, and a check node (CN) unit. The controller is configured to transform the base matrix into a compressed matrix of size N×S, where S is smaller than M. The VN unit and the CN unit are configured to perform message updates between variable nodes and check nodes to generate decoding results that converge to a codeword. During each decoding cycle, the VN unit performs calculations on each column of the compressed matrix.

The application discloses a storage test board firmware online upgrading method and device and a storage medium. The method dynamically intercepts the disc writing operation at the system call entry layer through the filter deployed in the kernel space to capture the physical erase operation boundary of the target flash memory controller and extract the starting time stamp. When the boundary is captured, the hardware performance monitoring unit is activated to poll the counter data to roll over the dynamic estimated execution delay of the current operation. If the delay is greater than or equal to the preset delay threshold, the control system is switched to the protection state. After entering the protection state, the target processor topology is reconfigured to migrate the test thread to the non-preferred kernel to release the preferred kernel, and the bandwidth suppression instruction is written to the memory controller to compress the physical bus bandwidth of the test thread and provide the on-chip physical channel for the flash memory writing. When the write-on-disk success signal is intercepted at the system call exit, the protection state is exited and the restriction is restored. The application can effectively reduce the influence of the test load on the firmware upgrading.

The invention discloses a command address transmission method and device of an NAND flash memory, a controller and a solid state disk, and relates to the technical field of data storage, the method is applied to the NAND flash memory controller, and the method comprises the steps that when the NAND flash memory controller is in an SCA mode, a first preset signal in a microcode to be executed is detected; if the first preset signal is a head identifier, executing a head shift operation by using an RTL circuit, and transmitting head information corresponding to the microcode to be executed to NAND flash memory particles through a CA bus; if the first preset signal is a command address identifier, executing a command address shift operation by using an RTL circuit, and transmitting command address information corresponding to the microcode to be executed to NAND flash memory particles through a CA bus; according to the invention, the conversion operation of the CA bus in the SCA mode is transferred to the RTL circuit from the microcode, so that the number of microcodes required for transmitting each command or address is greatly reduced, the loading speed of the microcodes is improved, and the working efficiency of the NAND flash memory controller is improved.

A flash memory device of a flash-based storage device includes a plurality of flash buses and a plurality of flash memory chips, and each flash bus is connected to two or more flash memory chips among the flash memory chips. A front-end includes a processing core, and a plurality of flash controllers are respectively connected to the flash buses. Each flash controller includes a flash controller logic configured to perform a read operation or a write operation in a flash memory chip connected to a corresponding flash bus among the flash buses, and a router configured to perform communication with another flash controller among the flash controllers.

The invention introduces a method for improving performance based on an artificial intelligence (AI) engine, performed by a processing unit, which includes: generating a value of a first-category parameter according to a command and an argument that a host side interacts with a flash controller; generating a value of a second-category parameter according to a software status and a firmware status of the flash controller; generating a value of a third-category parameter according to a status of the flash module, thereby enabling a prediction model running in the AI engine to generate prediction results in classes according to the values of the first-category, the second-category and the third-category parameter; and adjusting a setting of a process being performed in the flash controller according to the prediction results in the classes.

A flash memory controller and a method of performing a cache erase operation are disclosed. The flash memory controller includes a first interface circuit and a processor. The first interface circuit is coupled to a flash memory to transmit data and commands. The processor is coupled to the first interface circuit to access the flash memory. The processor controls the first interface circuit to transmit a first command sequence and a second command sequence to the flash memory. The first command sequence includes a first command and a second command. In response to the transmission of the second command, the flash memory performs an erase operation and transmits the second command sequence to the flash memory when an array ready bit is in a non-ready state. The present application can perform related operations that use a bus while performing an erase operation to improve transmission efficiency.

The present invention proposes a solid-state hard drive error injection testing method, which is applied to a flash memory controller in a solid-state hard drive, including: obtaining data to be written into the flash memory; after triggering the error injection test according to a preset error injection triggering method, performing multiple error injection tests on the data to be written into the flash memory during the verification and error correction process; obtaining test results of the multiple error injection tests. The present invention also proposes a solid-state hard drive error injection testing device, equipment and medium, which realizes active verification testing of the error correction and recovery functions of the solid-state hard drive, can effectively verify the completeness of all error correction and recovery functions of the solid-state hard drive, can effectively eliminate unknown bugs in the software code, and effectively improve the qualification rate of solid-state hard drive products.

The application relates to the technical field of storage, in particular to a flash memory controller configuration method and device for a solid state disk, equipment and a medium. The method comprises the following steps: according to the use information of the solid state disk, a target stage in which the solid state disk currently belongs in a life cycle is matched from a starting stage, an intermediate stage and an ending stage; in response to the target stage being the starting stage, the interleaving function of the flash memory controller is closed; in response to the target stage being the intermediate stage, the bit error rate of the solid state disk is periodically acquired, and the bit error rate is compared with a preset bit error rate to determine whether to open the interleaving function of the flash memory controller; and in response to the target stage being the ending stage, the interleaving function of the flash memory controller is opened. The application scheme flexibly opens or closes the interleaving function according to the stage of the solid state disk in the life cycle, improves the decoding success probability, and significantly improves the reliability of the solid state disk.