16 results about "Internal RAM" patented technology

A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

A storage device optimizes performance and operates at a predefined power upper limit. The storage device determines its power usage, and when the power usage is below a power upper threshold, the storage device operates according to a first random access memory (RAM) usage policy, and uses an internal RAM when processing host data. When the power usage is above the power upper limit threshold, the storage device operates according to a second RAM usage policy, and uses an external RAM or portions of the external RAM and the internal RAM when processing the host data. When the storage device determines that the host device is operating in a high performance mode, a cache hit on the external RAM has a drop, or a congestion level on a link between the host device and the storage device is above a congestion threshold, the storage device switches to the first RAM usage policy.

A method includes, in one non-limiting embodiment, sending a request from a mass memory storage device to a host device, the request being one to allocate memory in the host device; writing data from the mass memory storage device to allocated memory of the host device; and subsequently reading the data from the allocated memory to the mass memory storage device. The memory may be embodied as flash memory, and the data may be related to a file system stored in the flash memory. The method enables the mass memory storage device to extend its internal volatile RAM to include RAM of the host device, enabling the internal RAM to be powered off while preserving data and context stored in the internal RAM.

The invention relates to a remote traceless program loading method and system for a high-voltage frequency converter and a terminal, and relates to the field of high-voltage frequency conversion device.According to the method, a 5G router is adopted to receive data from a cloud end, the 5G router analyzes the data and temporarily stores the data in an RAM of an ARM chip, the ARM chip flashes a program file to a flash1 and flashes the program to a flash2 after backward reading and verification are successful, and the program file is stored in the RAM of the ARM chip; the flash 1 and the flash 2 refer to two Nand-flashes serving as program memories of the DSP, after the system is powered on, the ARM chip detects data integrity in the two Nand-flashes, then the digital switch is controlled to switch on chip selection signals of the Nand-flashes with complete data, the FPGA relieves resetting of the DSP, the DSP loads a program from the gated Nand-flash to an internal RAM and operates according to program logic, and the FPGA is controlled to switch on the chip selection signals of the Nand-flashes with complete data. According to the invention, the multi-core ARM is adopted to realize complete traceless downloading of the program, and the program can be modified without shutdown for large-scale equipment which cannot stop running. The application has the effects of improving the use convenience of the high-voltage frequency converter and remotely and seamlessly downloading the program.

The present invention belongs to the technical field of embedded systems, and particularly relates to a dual-redundancy protection circuit and method for automatically switching boot programs in a single-chip microcomputer. The circuit comprises: a single-chip microcomputer, including an internal program storage area, internal RAM, a BOOT pin, and a RESET pin; the internal program storage area stores a boot program, and the boot program is loaded into the internal RAM for execution; the boot program is switched from the internal program storage area to an external program storage area for execution by judging the state of the BOOT pin; a peripheral functional circuit comprises an external program storage area, a watchdog reset circuit, and a D-type flip-flop circuit; the external program storage area stores a boot program, and the single-chip microcomputer outputs a watchdog reset signal to the watchdog reset circuit, causing the watchdog reset circuit to generate a trigger signal. The present invention automatically switches the boot program startup storage area to another boot program startup storage area, thereby achieving the purpose of detecting boot program anomalies and automatically switching.

The application discloses a blowout preventer internal gate stroke position real-time monitoring and calibration method, comprising the following steps: synchronously collecting hydraulic pressure sequence, hydraulic flow sequence, valve control instruction sequence, action time sequence and acoustic emission event stream when the gate opening and closing action is triggered; performing pretreatment on the collected data; constructing pressure-flow-instruction response trajectory; extracting segmented slope feature, hysteresis shape feature, response time delay feature and inter-segment transition feature, and performing position inversion processing to obtain gate stroke position preliminary estimation sequence; identifying true-to-position endpoint moment, generating stroke zero point anchor point and stroke range endpoint anchor point; performing event parameterization processing on the pretreated acoustic emission event stream; and performing stroke calibration processing. The stroke inversion calibration method of the application utilizes multi-source standardized sequence and acoustic emission anchor point constraint, realizes gate position real-time monitoring and true-to-position determination, and has the advantages of strong anti-interference, low misjudgment rate and traceable calibration.

The invention discloses a hanging debugging method and debugging system for an embedded system, and relates to the technical field of embedded systems. According to the method, a Debugbus module and a Debugscan module are configured in an SOC chip of the embedded system, and an upper receiver is configured outside the chip; the Debugbus module is independent of a system bus and is used for collecting register information needing to be observed when the system bus is suspended; the Debugscan module is used for sending the register information collected by the Debugscan module to the upper receiver; the Debugscan module only needs to be opened and closed, and when the Debugscan module is opened, register information is obtained from the Debugbus module and transmitted to an upper receiver to be analyzed; and information is not transmitted during closing. According to the invention, the system information can be dumped when the bus is hung, so that the requirement on an internal RAM (Random Access Memory) of the embedded system is reduced, and the system cost is saved while a debugging function is provided.

The invention discloses a CPLD (Complex Programmable Logic Device) upgrading method and system based on an I2C private communication protocol. The method comprises the following steps: writing at least one page of program data into a first on-chip RAM (Random Access Memory) of an FPGA through an SPI (Serial Peripheral Interface); generating a first trigger instruction, controlling a host engine of an I2CMASTER module of the FPGA to start according to the first trigger instruction, extracting at least one page of program data from the first on-chip RAM according to the I2CMASTER, and placing the at least one page of program data on the I2C interface; obtaining an analysis instruction, and writing at least one page of program data into a second on-chip RAM (Random Access Memory) of the CPLD by adopting an I2CSlave module of the CPLD according to the analysis instruction; and generating a second trigger instruction, controlling a host engine of an SPIMASTER module of the CPLD to start according to the second trigger instruction, extracting at least one page of program data from the second on-chip RAM according to the SPIMASTER, burning an internal inherent flash program storage area through an SPI interface until program updating is completed, and transmitting the data to the slave device according to protocol requirements. And the slave device performs data communication with the Flash after caching, and after the Flash is configured, the whole CPLD upgrading process is completed.

The invention discloses a security-critical software spatial visualization method and system. The method comprises the steps of analyzing and compiling a mapping file to obtain information, mapping a storage area, carrying out spatial statistics and classification, and carrying out visualization and output. The system comprises an analysis module, a storage module, a statistics module and a visualization module. According to the method, high-precision spatial distribution is achieved, and overall and subdivision statistics of the Flash, the internal RAM and the external RAM are covered with the obvious space; the multi-level display can refine space occupation analysis to a three-level structure of storage area-file-segment, supports accurate positioning of an optimization target, supports mapping file formats of various compilers, and improves reliability and safety of software.

The invention discloses a real-time monitoring and calibrating method for the stroke position of a flashboard in a blowout preventer. The real-time monitoring and calibrating method comprises the following steps that when the opening and closing action of the flashboard is triggered, a hydraulic pressure sequence, a hydraulic flow sequence, a valve control instruction sequence, an action time sequence sequence and an acoustic emission event flow are synchronously collected; executing preprocessing on the collected data; constructing a pressure-flow-instruction response track; extracting segmented slope features, hysteretic morphological features, response time delay features and inter-segment transition features, and executing position inversion processing to obtain a gate stroke position preliminary estimation sequence; identifying a true in-place end point moment, and generating a stroke zero point anchor point and a stroke range end point anchor point; performing event parameterization processing on the preprocessed acoustic emission event stream; and executing travel calibration processing. According to the invention, a multi-source standardized sequence and acoustic emission anchor point constrained stroke inversion calibration method is utilized, real-time monitoring and true in-place judgment of the position of the flashboard are realized, and the method has the advantages of high interference resistance, low misjudgment rate and traceable calibration.

The invention provides a single-chip microcomputer upgrading method and device, and the method comprises the steps: controlling an external Flash memory to receive a data package sent by a sending device connected with a target single-chip microcomputer when the target single-chip microcomputer is in a bare computer working mode, and determining whether a preset application program is correct or not according to a crc value of the preset application program; if yes, writing the data packet into an external Flash memory; a program updating instruction is received, according to the program updating instruction, the BOOT package is called into an internal RAM of the target single-chip microcomputer from an external Flash memory, and a bootstrap program is run and started; and controlling the starting guide program to write the preset application program into the internal Flash memory of the target single-chip microcomputer from the external Flash memory so as to upgrade the single-chip microcomputer after the target single-chip microcomputer is reset. According to the invention, the external Flash memory detects the data packet, and after the preset application program in the external Flash memory is stored in the internal Flash memory, the correctness of the preset application program in the internal Flash memory is ensured, so that the firmware upgrading of the target single-chip microcomputer is ensured.

The invention provides a controller initialization method and device and related equipment, and the method comprises the steps: transmitting a simulated EEPROM data sector from an external storage medium to an internal RAM of a controller, so as to achieve the RAM mirroring of the external storage medium in the controller; effective data supporting initialization are searched for in the RAM mirror image through an NVM initialization module of the controller, and the NVM initialization module is a functional component, used for storing nonvolatile data, in the controller; and when the controller is electrified and initialized, reading effective data from the RAM mirror image to initialize and start the controller. According to the scheme, the data needing to be read from the external storage medium when the controller is initialized is changed into the data directly read from the interior of the controller in a mode of RAM mirroring in the controller, so that effective data supporting initialization can be quickly acquired when the controller is initialized, and the complexity of controller initialization and a data reading link are greatly reduced; and the time required for initialization of the controller is effectively reduced.

The invention provides a method and device for testing multi-level memory and performance of a DSP embedded system, and the method comprises the steps: setting an address region of a protected region and an address region of a security test region according to preset memory layout information in an initialization stage of the DSP embedded system; analyzing a test instruction set sent by the upper computer to obtain an internal RAM test instruction and an external communication chip RAM test instruction; responding to the internal RAM test instruction, adopting dynamic memory mapping management, identifying and avoiding a protected area necessary for program operation, and executing a memory test algorithm only in the security test area to obtain a first test result; in response to the RAM test instruction of the external communication chip, backing up data of a to-be-tested block of the external communication chip to a temporary buffer area, and testing the to-be-tested block to obtain a second test result; and returning the first test result and the second test result to the upper computer. The security and coverage rate of the system test can be improved.

In an embodiment of the present invention, a waveform output method based on dual-RAM reading of FPGA and SDRAM is provided. By utilizing the non-self-refresh characteristic of the internal RAM resources of the FPGA, this method first reads out a part of the previous data and gives it to the DAC, and at the same time caches the data of the SDRAM into the FIFO inside the FPGA, and then reads the subsequent data from the FIFO and splices it to the DAC output; thus, waveform instant output can be achieved. At the same time, since the number of data points cached in the FIFO is always greater than the number of data points interrupted by the self-refresh of the SDRAM, the waveform can be guaranteed to be continuous, and it can meet the high synchronization and low latency requirements of Qubit manipulation.

The application relates to the field of chip design, in particular to a video data processing debugging system and method based on FPGA prototype verification. The system comprises a DDR memory for storing data; a data generation module for generating original video data to be tested; a compression module for compressing the original video data to be tested to generate compressed data, and for providing an internal bus interface for accessing the DDR memory; a bus interface debugging module for providing an external bus interface for accessing the DDR memory; when the compression module generates the compressed data, a bus arbitration module is enabled to connect the internal bus interface with the DDR memory to store the compressed data into the DDR memory; when it is needed to verify the video data processing function, the bus arbitration module is enabled to connect the external bus interface to enable an external device to read the compressed data from the DDR memory. The scheme of the application avoids wasting internal RAM resources and realizes convenient and fast acquisition of debugging data.

The invention belongs to the technical field of embedded systems, and particularly relates to a dual-redundancy guarantee circuit and method for automatically switching bootstrap programs of a single-chip microcomputer. Comprising a single-chip microcomputer which comprises an internal program storage area, an internal RAM, a BOOT pin and a RESET pin; a bootstrap program is stored in the internal program storage area, and the bootstrap program is loaded to the internal RAM to be executed; by judging the state of the BOOT pin, the bootstrap program is switched from the internal program storage area to the external program storage area to be executed; the peripheral function circuit comprises an external program storage area, a watchdog reset circuit and a D flip-flop circuit; a bootstrap program is stored in the external program storage area, and a dog feeding signal is output to the watchdog reset circuit through the single chip microcomputer, so that the watchdog reset circuit generates a trigger signal. According to the method, the bootstrap program starting storage area is automatically switched to another bootstrap program starting storage area, so that the aims of detecting the abnormality of the bootstrap program and automatically switching the bootstrap program are fulfilled.