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Algorithm processing module for block chain

A processing module, block chain technology, applied in the field of network security

Active Publication Date: 2017-08-29
BEIJING INST OF COMP TECH & APPL
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In blockchain technology, it is necessary to use a large number of iterative hash algorithms to obtain random numbers (Nonce) as proof of work (POW) and use algorithms such as signature verification (ECDSA) and asymmetric encryption and decryption (ECIES) to interact with blocks. The speed of calculation has become a key bottleneck restricting the development and popularization of blockchain technology.

Method used

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  • Algorithm processing module for block chain
  • Algorithm processing module for block chain
  • Algorithm processing module for block chain

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Embodiment Construction

[0018] In order to make the purpose, content, and advantages of the present invention clearer, the specific embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and embodiments.

[0019] figure 1 Shown is the block diagram of the algorithm processing module used in the blockchain of the present invention, such as figure 1 As shown, the algorithm processing module for the blockchain includes: FPGA1, algorithm chip 2, PCIE interface chip 4, USB control chip 3, USB interface 6, PCIE interface 5, clock chip, power supply (not shown), and other components. Iterative hashing and hashing algorithms are implemented through the IP core of FPGA1, and ECC operations (signature verification, asymmetric encryption and decryption) are implemented through the cooperation of FPGA1 and algorithm chip 2.

[0020] Such as figure 1 As shown, the algorithm processing board obtains data from the PC 7 (host) through the communication in...

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PUM

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Abstract

The invention discloses an algorithm processing module for a block chain, and the module comprises a PCIE interface chip which is used for communication with a PCIE interface of an outer main unit; a USB control chip which is used for communication with a USB interface of the outer main unit; an algorithm chip which is used for cooperating with an FPGA for ECC calculation, wherein the FPGA comprises a Microblaze module which is used for controlling the operation of each submodule of the FPGA; an FIFO-RAM interface module which is used for achieving the transformation from the USB interface to an internal RAM interface, reading data from the USB chip and storing the data in the RAM module; a Local Bus-RAM interface module which is used for the transformation from the Local Bus interface to the internal RAM module interface; the internal RAM module which is used for storing the downloaded data of a user and the data to be uploaded to the user; an ECC control module which is used for carrying out the transformation from an APB bus to an ECC chip asynchronous interface, and carrying out the call of the algorithm chip to carry out the dot multiplying and modular multiplication calculation; a noise chip control module which is used for the transformation from the ABP bus to the noise chip interface; and an iterative Hash calculation module which is used for carrying out the iterative Hash calculation and carrying out the parallel processing of the algorithm module.

Description

Technical field [0001] The invention belongs to the technical field of network security, and designs a method for quantifying security breach threats based on multi-level influence factors. Background technique [0002] A blockchain is a distributed database based on the Bitcoin protocol that does not require permission. It maintains a continuously growing list of data records that cannot be tampered with or modified, even for the operators of the database nodes. In blockchain technology, it is necessary to use a large number of iterative hashing algorithms to obtain random numbers (Nonce) as proof of work (POW) and use signature verification (ECDSA), asymmetric encryption and decryption (ECIES) and other algorithms to interact with blocks. The speed of calculation has become a key bottleneck restricting the development and popularization of blockchain technology. Due to the inherent disadvantages of current computer CPUs in calculating iterative hashes, it is necessary to desig...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06Q20/38
CPCG06Q20/3825G06Q20/3827G06Q20/3829
Inventor 赵暾徐浩然许静雯邓超
Owner BEIJING INST OF COMP TECH & APPL
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