2817 results about "Computation process" patented technology

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch & decode (2000), a geometry unit (3000), a mode extraction (4000) and polygon memory (5000), a sort unit (6000) and sort memory (7000), a setup unit (8000), a cull unit (9000), a mode injection (10000), a fragment unit (11000), a texture (12000) and texture memory (13000) a phong shading (14000), a pixel unit (15000), a backend unit (1600) coupled to a frame buffer (17000). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

A method for monitoring performance of an advanced process control system for at least one process output includes calculating a variance of a prediction error for a processing performance and / or a probability for violating specification limits of the processing performance of the at least one process output. If the variance of the prediction error is calculated, the method also includes calculating a model health index. If the probability for violating specification limits is calculated, the method further includes calculating a process health index.

A matrix multiplication module and matrix multiplication method are provided that use a variable number of multiplier-accumulator units based on the amount of data elements of the matrices are available or needed for processing at a particular point or stage in the computation process. As more data elements become available or are needed, more multiplier-accumulator units are used to perform the necessary multiplication and addition operations. To multiply an N×M matrix by an M×N matrix, the total (maximum) number of used MAC units is “2*N−1”. The number of MAC units used starts with one (1) and increases by two at each computation stage, that is, at the beginning of reading of data elements for each new row of the first matrix. The sequence of the number of MAC units is {1, 3, 5, . . . , 2*N−1} for computation stages each of which corresponds to reading of data elements for each new row of the left hand matrix, also called the first matrix. For the multiplication of two 8×8 matrices, the performance is 16 floating point operations per clock cycle. For an FPGA running at 100 MHz, the performance is 1.6 Giga floating point operations per second. The performance increases with the increase of the clock frequency and the use of larger matrices when FPGA resources permit. Very large matrices are partitioned into smaller blocks to fit in the FPGA resources. Results from the multiplication of sub-matrices are combined to form the final result of the large matrices.

Computing process with a computational expression is executed using seed information including at least one of destination information and source information associated with a received packet. It is preferable to select a physical port for transmission of the received packet based on the result of the computation. It is also preferable to select a port group for transmission of the received packet based on the result of the computation. Here, the computational expression is capable of being modified. Meanwhile, the physical port for transmission of the received packet is selected from a plurality of candidate ports among the plurality of physical ports. The port group for transmission of the received packet is selected from among a plurality of port groups including a mutually different candidate port.