482 results about "Host processor" patented technology

A heterogeneous processing system including a host processor, a first processor with a first memory and a first data transfer resource, a second processor with a second memory, and switch and bus circuitry that communicatively couples the processors and the data transfer resource. The host processor is programmed to map virtual addresses of the second memory to physical addresses of the switch and bus circuitry and to configure the first processor to perform one memory to memory transfer operation between the first and second memories using the data transfer resource. The first processor may be configured to program the first data transfer resource. A method including mapping virtual addresses of the second memory to physical addresses of the switch and bus circuitry, and configuring the first processor to perform one memory to memory transfer operation between the first and second memories using the first data transfer resource.

An apparatus and method for creating less computationally intensive nodes for a neural network. An integrated circuit includes a host processor and multiple memory channels, each with multiple memory array banks. Each of the memory array banks includes components of a processing-in-memory (PIM) accelerator and a scatter and gather circuit used to dynamically perform quantization operations and dequantization operations that offload these operations from the host processor. The host processor executes a data model that represents a neural network. The memory array banks store a single copy of a particular data value in a single precision. Therefore, the memory array banks avoid storing replications of the same data value with different precisions to be used by a neural network node. The memory array banks dynamically perform quantization operations and dequantization operations on one or more of the weight values, input data values, and activation output values of the neural network.

Systems and methods for Message Queuing Telemetry Transport (MQTT) for Out-of-Band (OOB) manageability in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform comprising a plurality of devices, and an OOB Microcontroller Unit (MCU), an Embedded Controller (EC), or a network device integrated into or coupled to the heterogeneous computing platform and distinct from any host processor of the heterogeneous computing platform, wherein the OOB MCU, EC, or network device is configured to: establish an OOB connection with a cloud service via a light communication protocol while every host processor of the heterogeneous computing platform is in a low-power state, and retrieve one or more OOB packets from the cloud service via the OOB connection.

Systems and methods for enabling Out-of-Band (OOB) management of heterogeneous computing platforms in low-power states. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform and an Embedded Controller (EC) integrated into or coupled to the heterogeneous computing platform, where the EC is configured to: wake up from a low-power state while a host processor of the heterogeneous computing platform remains in the low-power state, and wake up a network device configured to access a cloud service through an OOB channel to check a status of an OOB command buffer while the host processor remains in the low-power state.

Systems and methods for Out-of-Band (OOB) networking for heterogeneous computing platforms in low-power states. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform and a network device integrated into or coupled to the heterogeneous computing platform, and the network device may be configured to: wake up from a low-power state while a host processor of the heterogeneous computing platform remains in the low-power state, and access a cloud service through an OOB channel to check a status of an OOB command buffer while the host processor remains in the low-power state.

A decentralized mesh-network platform provides real-time governance, supervision, and audit of large-language-model persona agents in regulated environments such as healthcare. Each computing node hosts processor circuitry, memory, a network interface, and an integrated suite comprising a User-Prompt Interface, Metadata Filter & Enrichment Engine, Persona Role Constructor, Policy Constraint Engine, gating logic module, Supervisor Review Interface, Session Memory Governance Module, Audit Logging Subsystem, cryptographically linked audit ledger, and Fallback Control Module. Devices communicate over a peer-to-peer channel, exchange role-switch tokens, and merge local ledgers into a composite audit graph when connectivity returns. The architecture supports continuous compliance and resilient operation across institutional boundaries, network partitions, and device failures, enabling conversational interaction with heterogeneous medical data while maintaining rigorous credential lineage, policy oversight, and forensic traceability.

Mechanisms for unordered input / output direct memory access operations are provided, including: issuing using a hardware processor a back invalidate snoop request to a cache coherency control unit of a host processor; and issuing an unordered input / output direct memory access operation request to a Compute Express Link memory device. In some of these mechanisms, the unordered input / output direct memory access operation request is for a read operation. In some of these mechanisms, the mechanisms further comprise receiving a response to the unordered input / output direct memory access operation request including data from the Compute Express Link memory device. In some of these mechanisms, the data was updated in response to the back invalidate snoop request. In some of these mechanisms, the unordered input / output direct memory access operation request is for a write operation.

The invention relates to the technical field of image processing, and further relates to a video decoding and unreal engine rendering method based on GPU full-link zero copy, which comprises the following steps of: 1, performing hardware decoding on an input video code stream on a GPU, and constructing a motion vector description buffer region for storing compressed domain motion vector information according to a macro block sequence; step 2, reading the motion vector description buffer area on the GPU through a calculation shader, and generating dynamic special effect control buffer areas in one-to-one correspondence with the macro blocks; and step 3, in a post-processing material of the unreal engine rendering module, taking the shared video texture resource as an input texture, and outputting a video picture. On the premise of not depending on a host processor and not excessively occupying video memory bandwidth, unified management of pixel data and motion data is achieved, delay is remarkably reduced, and special effect stability and direction consistency are improved.

Systems and methods for an interconnect architecture for Out-of-Band (OOB) manageability in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform having a plurality of devices and an OOB Microcontroller Unit (MCU) integrated into the heterogeneous computing platform, where the OOB MCU is configured to: receive a command; and transmit the command or an indication of the command to a selected one of the plurality of devices via an interconnect while a host processor is in a low-power state.

A multi-function device is disclosed. A first port may be used to communicate with a host processor. A second port may be used to communicate with a storage device. A third port may be used to communicate with a computational storage unit. Circuit may be used to route a message from the host processor to at least one of the storage device or the computational storage unit.

Systems and methods for Unified Extensible Firmware Interface (UEFI)-level processing of Out-of-Band (OOB) commands in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include: a heterogeneous computing platform having a plurality of devices, and an OOB Microcontroller Unit (MCU), Embedded Controller (EC), or networking device integrated into or coupled to the heterogeneous computing platform and distinct from a host processor of the heterogeneous computing platform, where the OOB MCU, EC, or networking device is configured to: receive an OOB packet while the host processor is in a low-power state, and execute an OOB command contained in the OOB packet, by the host processor, at least in part through initialization of UEFI without initialization of any video device.

A method of controlling a display panel for a display driver circuit includes steps of: starting counting time in a time period for receiving a first frame of display data, to generate a timing result; determining whether a timeout occurs according to the timing result; and outputting a control signal to instruct a host processor to transmit a second frame of display data at a time when the timeout occurs.

Multiple roots of trust are described under a super Root of trust (SROT). One embodiment includes: cores of a host processor; a host processor memory subsystem to provide access to a host processor memory; a home agent to provide access by the cores to the host processor memory subsystem and an expansion memory subsystem, a source address decoder to decode memory requests generated from the plurality of cores to determine whether the memory requests are to be directed to the host processor memory subsystem or the expansion memory subsystem. Host-based security circuitry encrypts and decrypts memory requests directed to the expansion memory subsystem, the host-based security circuitry to perform the encryption and decryption based on a second key stored in a cache maintained by the host-based security circuitry.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

A computer implemented method manages execution of jobs on virtual machines. Processor units identify a job for scheduling. The processor units identify host machines with free cores on which the virtual machines are allocated. The processor units determine a number of free cores on the host machines. The processor units determine whether a host machine in the host machines having a number of host attributes needed by the job has free cores and idle cores available for backfilling the job based on a predicted core usage for the job in response to an absence of a sufficient number of free cores being available to meet predicted core usage. The processor units dispatch the job to a virtual machine on the host machine in response to the host machine having the number of host attributes and the free cores and idle cores available for backfilling the job.

Systems and methods for booting an alternate Operating System (OS) by Out-of-Band (OOB) processors in heterogeneous computing platforms. In some embodiments, a heterogeneous computing platform may include an OOB Microcontroller Unit (MCU) and a memory coupled to the OOB MCU, the memory having program instructions stored thereon that, upon execution by the OOB MCU, cause the OOB MCU to, in response to an OOB command, enable a host processor to load an alternate OS boot image, where the alternate OS boot image is stored in a storage device external to the heterogeneous computing platform.

A DataCenter Secure Control Module (DC-SCM) as-a-service system includes a DataCenter Modular Hardware System (DC-MHS) computing device having a Host Processor Module (HPM) and a networking device that is coupled to the HPM and a network, and a DC-SCM provisioning system that is coupled to the networking device via the network. The DC-SCM provisioning system provides a networking device service instance for the networking device, receives a networking device DC-SCM functionality configuration for the networking device through the network via the networking device service instance, and configures at least one image to provide networking device DC-SCM functionality defined by the networking device DC-SCM functionality configuration. The networking device receives the at least one image via the network, and executes the at least one image to perform the networking device DC-SCM functionality with the HPM.

Systems and methods provide an Information Handling System (IHS) comprising one or more host processor modules configured to host pluggable hardware devices and a secure control module configured to host a baseboard management controller. The baseboard management controller obtain an SPDM alias certificate from at least one pluggable hardware device, and retrieve an extended reality content link from the SPDM alias certificate and an error code database from the SPDM alias certificate. The extended reality content link may include one or more of a virtual reality content link, an augmented reality content link, and a mixed reality content link. The extended reality content link comprises a URL or address where virtual, augmented, or mixed reality content associated with the at least one pluggable hardware device is available. The error code database identifies error states associated with the at least one pluggable hardware device.

Data processing systems, methods, computer program products, devices, and graphics processors are provided that substantially remove, or reduce, latencies introduced or incurred by a (host) processor e.g. a central processing unit (CPU), during virtualisation, in which virtual machines that are operable to execute on the (host) processor are scheduled or assigned to the graphics processor in a time-slice manner.

Systems and methods for enabling Out-of-Band (OOB) management of heterogeneous computing platforms in low-power states. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform and an Embedded Controller (EC) integrated into or coupled to the heterogeneous computing platform, where the EC is configured to: wake up from a low-power state while a host processor of the heterogeneous computing platform remains in the low-power state, and wake up a network device configured to access a cloud service through an OOB channel to check a status of an OOB command buffer while the host processor remains in the low-power state.

In one embodiment, a system comprises a host processor and a storage system. The storage system comprises one or more storage devices, and each storage device comprises a non-volatile memory and a compute offload controller. The non-volatile memory stores data, and the compute offload controller performs compute tasks on the data based on compute offload commands from the host processor.

Systems and methods for a memory architecture for Out-of-Band (OOB) manageability in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include: a heterogeneous computing platform having a plurality of devices, and an OOB Microcontroller Unit (MCU) integrated into the heterogeneous computing platform, where the OOB MCU is configured to: identify a command in an OOB packet received while a host processor is in a low-power state, and determine, based at least in part upon the command, whether to wake up an external memory device coupled to the heterogeneous computing platform.

A DataCenter Secure Control Module (DC-SCM) as-a-service system includes a DataCenter Modular Hardware System (DC-MHS) computing device having a Host Processor Module (HPM) and a networking device that is coupled to the HPM and a network, and a DC-SCM provisioning system that is coupled to the networking device via the network. The DC-SCM provisioning system provides a networking device service instance for the networking device, receives a networking device DC-SCM functionality configuration for the networking device through the network via the networking device service instance, and configures at least one image to provide networking device DC-SCM functionality defined by the networking device DC-SCM functionality configuration. The networking device receives the at least one image via the network, and executes the at least one image to perform the networking device DC-SCM functionality with the HPM.

Systems and methods for wireless interface sharing for Out-of-Band (OOB) processors in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include an OOB Microcontroller Unit (MCU) integrated into a heterogeneous computing platform and a network traffic routing controller integrated into the heterogeneous computing platform, where the network traffic routing controller is coupled to the OOB MCU and to a host processor, and where the network traffic routing controller is configured to determine whether to route a packet to the OOB MCU or to the host processor.

Systems and methods for location-based IHS functionality limiting in an Information Handling System (IHS) are described. In an embodiment, an IHS may include: a host processor; a security processor coupled to the host processor; and a memory coupled to the security processor, the memory having program instructions stored thereon that, upon execution, cause the security processor to: detect a location where the IHS is currently disposed; determine one or more restrictions associated with the detected location, each of the restrictions specifying a limitation to be imparted on a resource of the IHS; and communicate with the IHS to apply the determined restrictions.

Systems and methods for location-based IHS disablement in an Information Handling System (IHS) are described. In an embodiment, an IHS may include: a host processor; a security processor coupled to the host processor; and a memory coupled to the security processor, the memory having program instructions stored thereon that, upon execution, cause the security processor to: detect a location where the IHS is currently disposed; determine one or more restrictions associated with the detected location, each of the restrictions specifying a limitation to be imparted on a resource of the IHS; and communicate with the IHS to apply the determined restrictions.

The disclosed embodiments relate to securing operations accessing a non-volatile storage area of a memory device. In one embodiment, a method is disclosed comprising generating, by firmware of a memory device, a cryptographic key using a value of a physically unclonable function (PUF); writing, by the firmware, the cryptographic key to a volatile storage area; receiving, by the firmware, a command accessing a non-volatile storage area from a host processor; and processing, by the firmware, the command using the cryptographic key.

A cabinet x-ray system incorporates a voice command module and a gamma probe system for obtaining x-ray images and gamma probe measurements of a specimen. The system includes a cabinet; a display; and a microphone connected to the base unit. The x-ray system includes an x-ray source and detector; a specimen platform; and a controller to collect a projection x-ray image of the specimen when the x-ray source is energized and display the x-ray image on the display. The gamma probe system includes a gamma probe to receive signals from external sources and transmit signals corresponding to the signals received to the gamma probe base unit; and a gamma probe base unit in communication with the gamma probe and including a processor. The processor receives signals from the gamma probe and presents a visual numerical readout on the displays and generates a sound output.

The invention discloses a data search processing method and a host. A host processor obtains a query vector and a centroid of each to-be-searched graph; the to-be-searched graph is constructed for the query scene, so that the number of candidate vectors of the corresponding to-be-searched graph is determined according to the query vector and the centroid; a query request is sent to the hardware accelerator, the query request comprises query vectors and the number of candidate vectors, the hardware accelerator distributes the query request to different search units, and candidate vector search is conducted on the corresponding graphs to be searched in the external storage through the different search units.

Apparatuses, systems, and techniques to assign a processing resource to an inference request directed to a neural network based on an amount of information to be inferenced indicated by said request. In at least one embodiment, an AI application is deployed with a software wrapper that intercepts inference requests and dynamically distributes such requests among available processing resources such as host processor(s) and / or AI accelerator(s) to improve execution performance of said AI application.