254 results about "Host processor" patented technology

A decentralized mesh-network platform provides real-time governance, supervision, and audit of large-language-model persona agents in regulated environments such as healthcare. Each computing node hosts processor circuitry, memory, a network interface, and an integrated suite comprising a User-Prompt Interface, Metadata Filter & Enrichment Engine, Persona Role Constructor, Policy Constraint Engine, gating logic module, Supervisor Review Interface, Session Memory Governance Module, Audit Logging Subsystem, cryptographically linked audit ledger, and Fallback Control Module. Devices communicate over a peer-to-peer channel, exchange role-switch tokens, and merge local ledgers into a composite audit graph when connectivity returns. The architecture supports continuous compliance and resilient operation across institutional boundaries, network partitions, and device failures, enabling conversational interaction with heterogeneous medical data while maintaining rigorous credential lineage, policy oversight, and forensic traceability.

The invention relates to the technical field of image processing, and further relates to a video decoding and unreal engine rendering method based on GPU full-link zero copy, which comprises the following steps of: 1, performing hardware decoding on an input video code stream on a GPU, and constructing a motion vector description buffer region for storing compressed domain motion vector information according to a macro block sequence; step 2, reading the motion vector description buffer area on the GPU through a calculation shader, and generating dynamic special effect control buffer areas in one-to-one correspondence with the macro blocks; and step 3, in a post-processing material of the unreal engine rendering module, taking the shared video texture resource as an input texture, and outputting a video picture. On the premise of not depending on a host processor and not excessively occupying video memory bandwidth, unified management of pixel data and motion data is achieved, delay is remarkably reduced, and special effect stability and direction consistency are improved.

Multiple roots of trust are described under a super Root of trust (SROT). One embodiment includes: cores of a host processor; a host processor memory subsystem to provide access to a host processor memory; a home agent to provide access by the cores to the host processor memory subsystem and an expansion memory subsystem, a source address decoder to decode memory requests generated from the plurality of cores to determine whether the memory requests are to be directed to the host processor memory subsystem or the expansion memory subsystem. Host-based security circuitry encrypts and decrypts memory requests directed to the expansion memory subsystem, the host-based security circuitry to perform the encryption and decryption based on a second key stored in a cache maintained by the host-based security circuitry.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

In one embodiment, a system comprises a host processor and a storage system. The storage system comprises one or more storage devices, and each storage device comprises a non-volatile memory and a compute offload controller. The non-volatile memory stores data, and the compute offload controller performs compute tasks on the data based on compute offload commands from the host processor.

A DataCenter Secure Control Module (DC-SCM) as-a-service system includes a DataCenter Modular Hardware System (DC-MHS) computing device having a Host Processor Module (HPM) and a networking device that is coupled to the HPM and a network, and a DC-SCM provisioning system that is coupled to the networking device via the network. The DC-SCM provisioning system provides a networking device service instance for the networking device, receives a networking device DC-SCM functionality configuration for the networking device through the network via the networking device service instance, and configures at least one image to provide networking device DC-SCM functionality defined by the networking device DC-SCM functionality configuration. The networking device receives the at least one image via the network, and executes the at least one image to perform the networking device DC-SCM functionality with the HPM.

Apparatuses, systems, and techniques to assign a processing resource to an inference request directed to a neural network based on an amount of information to be inferenced indicated by said request. In at least one embodiment, an AI application is deployed with a software wrapper that intercepts inference requests and dynamically distributes such requests among available processing resources such as host processor(s) and / or AI accelerator(s) to improve execution performance of said AI application.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

Systems and methods for routing manageability data in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform comprising a plurality of devices and an Out-of-Band (OOB) Microcontroller Unit (MCU), an Embedded Controller (EC), or a network device integrated into or coupled to the heterogeneous computing platform and distinct from any host processor of the heterogeneous computing platform, where the OOB MCU, EC, or network device is configured to receive a packet or command from a cloud service, and send the packet or command to a selected one of the plurality of devices.

Provided are methods, systems, and devices for financial risk assessment and digital security enhancement. This includes receiving, at the host processor via the computing network, a plurality of input signals from a plurality of primary systems, the input signals corresponding to a client identifier to generate a corresponding first record; analyzing the corresponding first record, to extract a corresponding second record by implementing a plurality of predefined tags and generating a categorized record; receiving physical asset signals, associated to the client identifier, from an external asset system; generating a qualifier score based on a predictive algorithm applied to the categorized record and the physical asset signals, the predictive algorithm assigning weights to the plurality of data categories in the categorized record; and determining whether the qualifier score meets a one or more threshold range.

In accordance with the described techniques for host accesses to processing-in-memory oriented data structures, a computing device includes a memory, a host processing unit, and multiple processing-in-memory units each configured to access one or more banks of the memory. The host processor receives an access request to access an element of a data structure stored in the memory. In particular, the access request includes input parameters indicating a processing-in-memory unit of the multiple processing-in-memory units by which the element is accessible, and an offset of the element relative to other elements of the data structure. The host processor generates a memory address based on the processing-in-memory unit and the offset, and the element of the data structure is accessed based on the memory address.

Systems and methods for Out-of-Band (OOB) networking for heterogeneous computing platforms in low-power states. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform and a network device integrated into or coupled to the heterogeneous computing platform, and the network device may be configured to: wake up from a low-power state while a host processor of the heterogeneous computing platform remains in the low-power state, and access a cloud service through an OOB channel to check a status of an OOB command buffer while the host processor remains in the low-power state.

The invention discloses a data processing system, method and equipment, a medium and a program product in the technical field of computers. In the invention, a cache coherence root port of a computing device is connected with a cache coherence sub-port of a memory processing device through a cache coherence protocol, so that the computing device is used for synchronizing a query matrix of a model processing task and a first result output in a key value matrix calculation stage to the memory processing device through the cache coherence protocol; meanwhile, the memory processing device can synchronize the second result to the computing device through the cache coherence protocol, so that rapid data transmission between the computing device and the memory processing device is realized, the memory space of the computing device is saved, the overhead of a host processor in the execution process of the model processing task is reduced, and the performance of the model processing task is improved. And the task processing efficiency of the hardware computing equipment can be improved to a certain extent.

Systems and methods for booting an alternate Operating System (OS) by Out-of-Band (OOB) processors in heterogeneous computing platforms. In some embodiments, a heterogeneous computing platform may include an OOB Microcontroller Unit (MCU) and a memory coupled to the OOB MCU, the memory having program instructions stored thereon that, upon execution by the OOB MCU, cause the OOB MCU to, in response to an OOB command, enable a host processor to load an alternate OS boot image, where the alternate OS boot image is stored in a storage device external to the heterogeneous computing platform.

A computer system executes a machine learning model having multiple layers, and includes host and work accelerator processors. A window size representing a number of layers to be loaded into accelerator memory is determined. Model data associated with a subset of layers the same size as the window is loaded to the accelerator. The model is iteratively executed by processing a current layer to provide output data and storing this in accelerator memory, offloading the output data to host memory, replacing model data for an already processed layer with model data corresponding to a next layer, and moving to a next layer. The window size is updated during execution based on a transfer duration for loading into accelerator memory, a transfer duration for loading into host memory, or a processing duration of a layer.

In one aspect, a method includes receiving, in a first wireless device, a data transmission including at least one orthogonal frequency division multiplexing (OFDM) packet from a second wireless device; processing the at least one OFDM packet to recover data and providing the data to a host processor of the first wireless device; encoding, in the first wireless device, at least one decoded symbol of the at least one OFDM packet using forward error correction coding; processing the encoded at least one decoded symbol to recover at least one corresponding transmission symbol of the at least one OFDM packet; and determining a distance estimate between the first wireless device and the second wireless device based at least in part on the corresponding transmitted symbols.

The application provides a method and system for optimizing a DSP core simulation based on a SIMD instruction, wherein the method comprises the following steps: firstly, obtaining a DSP simulation project file, and identifying target instructions with CPU occupation time reaching a preset threshold by combining a performance profiling tool; secondly, analyzing the semantics of the target instructions and extracting parallel operations, and matching a host processor SIMD instruction set to determine a corresponding execution function; thirdly, writing a processing function for calling the execution function; fourthly, replacing original simulation logic of the target instructions in the source code with a processing function call, and supplementing a file reference declaration; and finally, recompiling through a compiler adapted to the SIMD instruction set to generate an optimized executable file, namely a target executable file. The application can effectively improve the simulation running speed of a VLIW type DSP core, has strong optimization targeting, and guarantees accurate simulation calculation results.

A data security verification method and an electronic apparatus are provided. In the data security verification method, when the electronic apparatus is powered on, a verification circuit verifies integrity of an executable image in a storage device. If verification fails, the verification circuit stops a host processor from executing the executable image. If the verification is successful, the verification circuit releases a host reset, and a processor reads and executes the executable image. When the processor reads the executable image, the verification circuit re-verifies the executable image, and the processor executes the executable image according to a verification result.

Disclosed herein is a sensor system that detects a stylus on at least one panel surface having an effective region. The sensor system includes a memory device including computer-executable instructions, and a processor. The processor, when loaded with the computer-executable instructions, performs: and obtaining a position of the stylus and a pen pressure value indicating a pressure applied to a pen tip of the stylus; outputting the position and the pen pressure value to a host processor. In response to the position being outside the effective region, the processor performs processing to conceal from the host processor occurrence of at least one of a pen-down indicating the stylus contacting the panel surface and a pen-up indicating the stylus being removed from the panel surface.

Implementations for chiplet fault management through hierarchical error reporting and coordinated recovery in an accelerator interconnect. In some implementations, a system for a UALink-based network comprises a chiplet die coupled to an accelerator die, a management agent on the accelerator die, and a centralized controller. Upon fault detection, the chiplet die transmits a fault notification to the accelerator die, the management agent reports the fault to the centralized controller, and the centralized controller determines a recovery action based on the fault identifier and severity. In some implementations, the accelerator die reports the fault through dual paths, to a host processor via CXL or PCIe error reporting and to the centralized controller via the management agent, and the host processor and the centralized controller coordinate recovery, with the host managing workload-level recovery and the centralized controller managing network-level recovery.

There is provided a system having a server unit with a host processor and a service processor, a first bus interface and a second bus interface, a data storage unit with a plurality of drives grouped into a first and second group, a first serial-to-parallel-input / output (S2PIO) device connected to the first group, and a second S2PIO device connected to the second group. The system is configured to acquire, by the service processor from the host processor, an indication of a faulty memory drive in the data storage unit, the indication being indicative of a target link amongst the first link and the second link, and a position of the faulty memory drive in the target group. The system is configured to transmit, by the service processor using the target link, a command to a target S2PIO device for triggering a visual indicator associated with the faulty memory drive.

The application discloses a bottom-layer security defense architecture and method based on thermodynamic entropy and nanosecond physical short circuit, which comprises a thermodynamic chaotic true random number generator configured to collect physical thermal noise and generate a true random number; a time-space jump memory management configured to dynamically remap the physical storage address of a volatile memory based on the true random number; a programmable hardware logic unit configured to run independently of a host processor and perform out-of-band polling on a physical intrusion detection signal; and a physical short circuit module connected between the power supply rail and the ground of the volatile memory, wherein the programmable hardware logic unit sends a trigger signal to the physical short circuit module when detecting the physical intrusion signal, and the physical short circuit module responds to the trigger signal to short the power supply rail of the volatile memory to the ground within a preset transient time threshold, so that the physical level data destruction less than 5 nanoseconds and the dynamic address confusion driven by the true random number are realized.

Disclosed embodiments provide systems, methods, and techniques enabling Non-Volatile Memory Express (NVMe) namespace promotion from a private namespace to a shared namespace, which eliminate conventional operations of deleting existing private namespaces and creating new namespaces as shared. In a disclosed embodiment, an NVMe host driver issues an NVMe management command to change an NVMe private namespace to a shared namespace during a namespace promotion. An NVMe controller sends an NVMe response to the NVMe host indicating an attribute of the NVMe private namespace changed to the shared namespace. The NVMe response is received by a host processor and the private namespace is promoted to shared and attachable by multiple NVMe controllers in an NVMe subsystem.

The present application relates to the technical field of image processing, and more particularly to a video decoding and Unreal Engine rendering method based on GPU full-link zero-copy, which comprises the following steps: step one, hardware decoding of an input video code stream on a GPU, and construction of a motion vector description buffer for storing compressed domain motion vector information in macroblock order; step two, reading of the motion vector description buffer by a calculation shader on the GPU to generate a dynamic special effect control buffer corresponding to each macroblock; and step three, in the post-processing material of the Unreal Engine rendering module, taking a shared video texture resource as an input texture and outputting a video picture. The present application realizes unified management of pixel data and motion data without relying on a host processor and without excessively occupying video memory bandwidth, significantly reduces delay, and improves special effect stability and direction consistency.

A display device includes a display panel, and a panel driver which drives the display panel. The panel driver receives a multi-frequency driving (“MFD”) enable command from a host processor. In a first frame period, the panel driver receives a boundary setting command indicating a boundary between a first panel region and a second panel region of the display panel from the host processor. In a second frame period after the first frame period, the panel driver receives input image data for the first panel region from the host processor, does not receive the input image data for the second panel region from the host processor, drives the first panel region based on the input image data for the first panel region, and does not drive the second panel region.

Systems and methods for Unified Extensible Firmware Interface (UEFI)-level processing of Out-of-Band (OOB) commands in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include: a heterogeneous computing platform having a plurality of devices, and an OOB Microcontroller Unit (MCU), Embedded Controller (EC), or networking device integrated into or coupled to the heterogeneous computing platform and distinct from a host processor of the heterogeneous computing platform, where the OOB MCU, EC, or networking device is configured to: receive an OOB packet while the host processor is in a low-power state, and execute an OOB command contained in the OOB packet, by the host processor, at least in part through initialization of UEFI without initialization of any video device.

A system on chip includes an accelerator configured to generate a demand request for demand data corresponding to a neural network operation based on instructions received from a host processor, and to generate a prefetch request for prefetch data based on a memory access pattern predicted from the neural network operation; a memory controller configured to read the demand data from a memory based on the demand request, and read the prefetch data from the memory based on the prefetch request; and a system cache configured to store at least one of prefetch data and demand data read from the memory as read data, where the accelerator is configured to perform the neural network operation on the read data received from the system cache.

A data processing system is presented that is configured as a server in a client-server configuration for executing applications that a client in the client-server configuration can offload as execution tasks for execution on the server. The data processing system includes a reconfigurable processor, a storage device that stores configuration files for the applications, and a host processor that is coupled to the storage device and to the reconfigurable processor. The host processor is configured to receive an execution task of the execution tasks with an identifier of an application from the client, retrieve a configuration file that is associated with the application from the storage device using the identifier of the application, configure the reconfigurable processor with the configuration file, and start execution of the application on the reconfigurable processor, whereby the reconfigurable processor provides output data of the execution of the application to the client.