350 results about "Host processor" patented technology

A decentralized mesh-network platform provides real-time governance, supervision, and audit of large-language-model persona agents in regulated environments such as healthcare. Each computing node hosts processor circuitry, memory, a network interface, and an integrated suite comprising a User-Prompt Interface, Metadata Filter & Enrichment Engine, Persona Role Constructor, Policy Constraint Engine, gating logic module, Supervisor Review Interface, Session Memory Governance Module, Audit Logging Subsystem, cryptographically linked audit ledger, and Fallback Control Module. Devices communicate over a peer-to-peer channel, exchange role-switch tokens, and merge local ledgers into a composite audit graph when connectivity returns. The architecture supports continuous compliance and resilient operation across institutional boundaries, network partitions, and device failures, enabling conversational interaction with heterogeneous medical data while maintaining rigorous credential lineage, policy oversight, and forensic traceability.

Mechanisms for unordered input / output direct memory access operations are provided, including: issuing using a hardware processor a back invalidate snoop request to a cache coherency control unit of a host processor; and issuing an unordered input / output direct memory access operation request to a Compute Express Link memory device. In some of these mechanisms, the unordered input / output direct memory access operation request is for a read operation. In some of these mechanisms, the mechanisms further comprise receiving a response to the unordered input / output direct memory access operation request including data from the Compute Express Link memory device. In some of these mechanisms, the data was updated in response to the back invalidate snoop request. In some of these mechanisms, the unordered input / output direct memory access operation request is for a write operation.

The invention relates to the technical field of image processing, and further relates to a video decoding and unreal engine rendering method based on GPU full-link zero copy, which comprises the following steps of: 1, performing hardware decoding on an input video code stream on a GPU, and constructing a motion vector description buffer region for storing compressed domain motion vector information according to a macro block sequence; step 2, reading the motion vector description buffer area on the GPU through a calculation shader, and generating dynamic special effect control buffer areas in one-to-one correspondence with the macro blocks; and step 3, in a post-processing material of the unreal engine rendering module, taking the shared video texture resource as an input texture, and outputting a video picture. On the premise of not depending on a host processor and not excessively occupying video memory bandwidth, unified management of pixel data and motion data is achieved, delay is remarkably reduced, and special effect stability and direction consistency are improved.

A method of controlling a display panel for a display driver circuit includes steps of: starting counting time in a time period for receiving a first frame of display data, to generate a timing result; determining whether a timeout occurs according to the timing result; and outputting a control signal to instruct a host processor to transmit a second frame of display data at a time when the timeout occurs.

Multiple roots of trust are described under a super Root of trust (SROT). One embodiment includes: cores of a host processor; a host processor memory subsystem to provide access to a host processor memory; a home agent to provide access by the cores to the host processor memory subsystem and an expansion memory subsystem, a source address decoder to decode memory requests generated from the plurality of cores to determine whether the memory requests are to be directed to the host processor memory subsystem or the expansion memory subsystem. Host-based security circuitry encrypts and decrypts memory requests directed to the expansion memory subsystem, the host-based security circuitry to perform the encryption and decryption based on a second key stored in a cache maintained by the host-based security circuitry.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

Systems and methods provide an Information Handling System (IHS) comprising one or more host processor modules configured to host pluggable hardware devices and a secure control module configured to host a baseboard management controller. The baseboard management controller obtain an SPDM alias certificate from at least one pluggable hardware device, and retrieve an extended reality content link from the SPDM alias certificate and an error code database from the SPDM alias certificate. The extended reality content link may include one or more of a virtual reality content link, an augmented reality content link, and a mixed reality content link. The extended reality content link comprises a URL or address where virtual, augmented, or mixed reality content associated with the at least one pluggable hardware device is available. The error code database identifies error states associated with the at least one pluggable hardware device.

Data processing systems, methods, computer program products, devices, and graphics processors are provided that substantially remove, or reduce, latencies introduced or incurred by a (host) processor e.g. a central processing unit (CPU), during virtualisation, in which virtual machines that are operable to execute on the (host) processor are scheduled or assigned to the graphics processor in a time-slice manner.

In one embodiment, a system comprises a host processor and a storage system. The storage system comprises one or more storage devices, and each storage device comprises a non-volatile memory and a compute offload controller. The non-volatile memory stores data, and the compute offload controller performs compute tasks on the data based on compute offload commands from the host processor.

A DataCenter Secure Control Module (DC-SCM) as-a-service system includes a DataCenter Modular Hardware System (DC-MHS) computing device having a Host Processor Module (HPM) and a networking device that is coupled to the HPM and a network, and a DC-SCM provisioning system that is coupled to the networking device via the network. The DC-SCM provisioning system provides a networking device service instance for the networking device, receives a networking device DC-SCM functionality configuration for the networking device through the network via the networking device service instance, and configures at least one image to provide networking device DC-SCM functionality defined by the networking device DC-SCM functionality configuration. The networking device receives the at least one image via the network, and executes the at least one image to perform the networking device DC-SCM functionality with the HPM.

The disclosed embodiments relate to securing operations accessing a non-volatile storage area of a memory device. In one embodiment, a method is disclosed comprising generating, by firmware of a memory device, a cryptographic key using a value of a physically unclonable function (PUF); writing, by the firmware, the cryptographic key to a volatile storage area; receiving, by the firmware, a command accessing a non-volatile storage area from a host processor; and processing, by the firmware, the command using the cryptographic key.

A cabinet x-ray system incorporates a voice command module and a gamma probe system for obtaining x-ray images and gamma probe measurements of a specimen. The system includes a cabinet; a display; and a microphone connected to the base unit. The x-ray system includes an x-ray source and detector; a specimen platform; and a controller to collect a projection x-ray image of the specimen when the x-ray source is energized and display the x-ray image on the display. The gamma probe system includes a gamma probe to receive signals from external sources and transmit signals corresponding to the signals received to the gamma probe base unit; and a gamma probe base unit in communication with the gamma probe and including a processor. The processor receives signals from the gamma probe and presents a visual numerical readout on the displays and generates a sound output.

The invention discloses a data search processing method and a host. A host processor obtains a query vector and a centroid of each to-be-searched graph; the to-be-searched graph is constructed for the query scene, so that the number of candidate vectors of the corresponding to-be-searched graph is determined according to the query vector and the centroid; a query request is sent to the hardware accelerator, the query request comprises query vectors and the number of candidate vectors, the hardware accelerator distributes the query request to different search units, and candidate vector search is conducted on the corresponding graphs to be searched in the external storage through the different search units.

Apparatuses, systems, and techniques to assign a processing resource to an inference request directed to a neural network based on an amount of information to be inferenced indicated by said request. In at least one embodiment, an AI application is deployed with a software wrapper that intercepts inference requests and dynamically distributes such requests among available processing resources such as host processor(s) and / or AI accelerator(s) to improve execution performance of said AI application.

A computing device includes a memory having one or more processing-in-memory units, and a host processor that includes one or more caches. The host processor receives a workload that accesses a page of the memory. Further, the host processor dynamically assigns different modes of operation to the page of the memory during different phases of execution of the workload. The different modes are assigned based on whether the workload is to be executed by the host processor, the one or more processing-in-memory units, or the host processor and the one or more processing-in-memory units during the different phases of execution. The host processor processes requests of the workload that access the page of the memory in accordance with the different modes of operation during the different phases of execution. Notably, the different modes of operation specify different caching policies for the page of the memory.

Systems and methods for routing manageability data in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform comprising a plurality of devices and an Out-of-Band (OOB) Microcontroller Unit (MCU), an Embedded Controller (EC), or a network device integrated into or coupled to the heterogeneous computing platform and distinct from any host processor of the heterogeneous computing platform, where the OOB MCU, EC, or network device is configured to receive a packet or command from a cloud service, and send the packet or command to a selected one of the plurality of devices.

According to one embodiment, a memory module includes: a memory die including a dynamic random access memory (DRAM) banks, each including: an array of DRAM cells arranged in pages; a row buffer to store values of one of the pages; an input / output (IO) module; and an in-memory compute (IMC) module including: an arithmetic logic unit (ALU) to receive operands from the row buffer or the IO module and to compute an output based on the operands and one of a plurality of ALU operations; and a result register to store the output of the ALU; and a controller to: receive, from a host processor, operands and an instruction; determine, based on the instruction, a data layout; supply the operands to the DRAM banks in accordance with the data layout; and control an IMC module to perform one of the ALU operations on the operands in accordance with the instruction.SPL

A computing system includes a host processor, a plurality of accelerators that communicate with the host processor based on a communication interface, and a plurality of memory nodes that are connected with the plurality of accelerators through an interconnection network. A first data link is established between a first accelerator of the plurality of accelerators and a first memory node of the plurality of memory nodes, and a second data link is established between the first accelerator and a second memory node of the plurality of memory nodes.

Computing architectures, platforms, and systems are provided herein. In one example, system is provided. The system includes a management processor configured to initiate a communication arrangement between a first endpoint device coupled to a communication fabric and a second endpoint device coupled to the communication fabric. The communication arrangement is configured to redirect a transfer from the first endpoint device based on an address corresponding to an address range of the second endpoint device without passing the transfer through a host processor coupled to the communication fabric that executes an application initiating the transfer.

Provided are methods, systems, and devices for financial risk assessment and digital security enhancement. This includes receiving, at the host processor via the computing network, a plurality of input signals from a plurality of primary systems, the input signals corresponding to a client identifier to generate a corresponding first record; analyzing the corresponding first record, to extract a corresponding second record by implementing a plurality of predefined tags and generating a categorized record; receiving physical asset signals, associated to the client identifier, from an external asset system; generating a qualifier score based on a predictive algorithm applied to the categorized record and the physical asset signals, the predictive algorithm assigning weights to the plurality of data categories in the categorized record; and determining whether the qualifier score meets a one or more threshold range.

Systems and methods provide an Information Handling System (IHS), comprising a host processor module and a secure control module. A baseboard management controller executes a process that binds the host processor module to the secure control module using a hash value calculated from characteristics of components of the first host processor module. The process to bind the first host processor module to the secure control module comprises retrieving hardware identity certificates from all SPDM-capable hardware devices in the first host processor module, retrieving firmware measurements from all SPDM-capable hardware devices in the first host processor module, calculating an initial hash value from the hardware identity certificates and the firmware measurements, and storing the initial hash value either in the baseboard management controller or in the security processor.

There is provided a system having a server unit with a host processor and a service processor, a first bus interface and a second bus interface, a data storage unit with a plurality of drives grouped into a first and second group, a first serial-to-parallel-input / output (S2PIO) device connected to the first group, and a second S2PIO device connected to the second group. The system is configured to acquire, by the service processor from the host processor, an indication of a faulty memory drive in the data storage unit, the indication being indicative of a target link amongst the first link and the second link, and a position of the faulty memory drive in the target group. The system is configured to transmit, by the service processor using the target link, a command to a target S2PIO device for triggering a visual indicator associated with the faulty memory drive.

Efficient simulation of a quantum computer can be achieved by minimizing the time required for data exchange between a host processor and a specialized processor simulating quantum computations. The data exchange time can be minimized using a partitioned memory that facilitates the exchange from the host processor to the specialized processor of the data to be processed simultaneously with the exchange from the specialized processor to the host processor of the data already processed. The data exchange time can also be minimized by identifying data that would not change as a result of a quantum computation, and by not exchanging such data.

In accordance with the described techniques for host accesses to processing-in-memory oriented data structures, a computing device includes a memory, a host processing unit, and multiple processing-in-memory units each configured to access one or more banks of the memory. The host processor receives an access request to access an element of a data structure stored in the memory. In particular, the access request includes input parameters indicating a processing-in-memory unit of the multiple processing-in-memory units by which the element is accessible, and an offset of the element relative to other elements of the data structure. The host processor generates a memory address based on the processing-in-memory unit and the offset, and the element of the data structure is accessed based on the memory address.

Systems and methods for Out-of-Band (OOB) networking for heterogeneous computing platforms in low-power states. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform and a network device integrated into or coupled to the heterogeneous computing platform, and the network device may be configured to: wake up from a low-power state while a host processor of the heterogeneous computing platform remains in the low-power state, and access a cloud service through an OOB channel to check a status of an OOB command buffer while the host processor remains in the low-power state.

The invention discloses a data processing system, method and equipment, a medium and a program product in the technical field of computers. In the invention, a cache coherence root port of a computing device is connected with a cache coherence sub-port of a memory processing device through a cache coherence protocol, so that the computing device is used for synchronizing a query matrix of a model processing task and a first result output in a key value matrix calculation stage to the memory processing device through the cache coherence protocol; meanwhile, the memory processing device can synchronize the second result to the computing device through the cache coherence protocol, so that rapid data transmission between the computing device and the memory processing device is realized, the memory space of the computing device is saved, the overhead of a host processor in the execution process of the model processing task is reduced, and the performance of the model processing task is improved. And the task processing efficiency of the hardware computing equipment can be improved to a certain extent.

A cell matching system capable of extending the life of a battery pack belongs to the technical field of control systems, and particularly relates to a cell matching system capable of extending the life of a battery pack. The present invention provides a circuit hardware basis for a cell matching system capable of extending the life of a battery pack. The present invention includes a local host processor part, a node host and touch screen connection communication part, a host RS485 communication part, a node data upload part, a node host power supply part, a battery charging current acquisition part, a battery voltage acquisition part, a battery charge and discharge circuit part, an ADC acquisition post-filtering circuit part, a slave processor part, a slave RS485 communication part, a slave power supply part, a slave cell temperature control circuit part, and a battery discharge current ADC conversion circuit part.

Systems and methods for booting an alternate Operating System (OS) by Out-of-Band (OOB) processors in heterogeneous computing platforms. In some embodiments, a heterogeneous computing platform may include an OOB Microcontroller Unit (MCU) and a memory coupled to the OOB MCU, the memory having program instructions stored thereon that, upon execution by the OOB MCU, cause the OOB MCU to, in response to an OOB command, enable a host processor to load an alternate OS boot image, where the alternate OS boot image is stored in a storage device external to the heterogeneous computing platform.

A computer system executes a machine learning model having multiple layers, and includes host and work accelerator processors. A window size representing a number of layers to be loaded into accelerator memory is determined. Model data associated with a subset of layers the same size as the window is loaded to the accelerator. The model is iteratively executed by processing a current layer to provide output data and storing this in accelerator memory, offloading the output data to host memory, replacing model data for an already processed layer with model data corresponding to a next layer, and moving to a next layer. The window size is updated during execution based on a transfer duration for loading into accelerator memory, a transfer duration for loading into host memory, or a processing duration of a layer.

In one aspect, a method includes receiving, in a first wireless device, a data transmission including at least one orthogonal frequency division multiplexing (OFDM) packet from a second wireless device; processing the at least one OFDM packet to recover data and providing the data to a host processor of the first wireless device; encoding, in the first wireless device, at least one decoded symbol of the at least one OFDM packet using forward error correction coding; processing the encoded at least one decoded symbol to recover at least one corresponding transmission symbol of the at least one OFDM packet; and determining a distance estimate between the first wireless device and the second wireless device based at least in part on the corresponding transmitted symbols.