154 results about "Host processor" patented technology

A decentralized mesh-network platform provides real-time governance, supervision, and audit of large-language-model persona agents in regulated environments such as healthcare. Each computing node hosts processor circuitry, memory, a network interface, and an integrated suite comprising a User-Prompt Interface, Metadata Filter & Enrichment Engine, Persona Role Constructor, Policy Constraint Engine, gating logic module, Supervisor Review Interface, Session Memory Governance Module, Audit Logging Subsystem, cryptographically linked audit ledger, and Fallback Control Module. Devices communicate over a peer-to-peer channel, exchange role-switch tokens, and merge local ledgers into a composite audit graph when connectivity returns. The architecture supports continuous compliance and resilient operation across institutional boundaries, network partitions, and device failures, enabling conversational interaction with heterogeneous medical data while maintaining rigorous credential lineage, policy oversight, and forensic traceability.

The invention relates to the technical field of image processing, and further relates to a video decoding and unreal engine rendering method based on GPU full-link zero copy, which comprises the following steps of: 1, performing hardware decoding on an input video code stream on a GPU, and constructing a motion vector description buffer region for storing compressed domain motion vector information according to a macro block sequence; step 2, reading the motion vector description buffer area on the GPU through a calculation shader, and generating dynamic special effect control buffer areas in one-to-one correspondence with the macro blocks; and step 3, in a post-processing material of the unreal engine rendering module, taking the shared video texture resource as an input texture, and outputting a video picture. On the premise of not depending on a host processor and not excessively occupying video memory bandwidth, unified management of pixel data and motion data is achieved, delay is remarkably reduced, and special effect stability and direction consistency are improved.

Apparatuses, systems, and techniques to assign a processing resource to an inference request directed to a neural network based on an amount of information to be inferenced indicated by said request. In at least one embodiment, an AI application is deployed with a software wrapper that intercepts inference requests and dynamically distributes such requests among available processing resources such as host processor(s) and / or AI accelerator(s) to improve execution performance of said AI application.

Systems and methods for routing manageability data in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include a heterogeneous computing platform comprising a plurality of devices and an Out-of-Band (OOB) Microcontroller Unit (MCU), an Embedded Controller (EC), or a network device integrated into or coupled to the heterogeneous computing platform and distinct from any host processor of the heterogeneous computing platform, where the OOB MCU, EC, or network device is configured to receive a packet or command from a cloud service, and send the packet or command to a selected one of the plurality of devices.

Provided are methods, systems, and devices for financial risk assessment and digital security enhancement. This includes receiving, at the host processor via the computing network, a plurality of input signals from a plurality of primary systems, the input signals corresponding to a client identifier to generate a corresponding first record; analyzing the corresponding first record, to extract a corresponding second record by implementing a plurality of predefined tags and generating a categorized record; receiving physical asset signals, associated to the client identifier, from an external asset system; generating a qualifier score based on a predictive algorithm applied to the categorized record and the physical asset signals, the predictive algorithm assigning weights to the plurality of data categories in the categorized record; and determining whether the qualifier score meets a one or more threshold range.

Systems and methods for booting an alternate Operating System (OS) by Out-of-Band (OOB) processors in heterogeneous computing platforms. In some embodiments, a heterogeneous computing platform may include an OOB Microcontroller Unit (MCU) and a memory coupled to the OOB MCU, the memory having program instructions stored thereon that, upon execution by the OOB MCU, cause the OOB MCU to, in response to an OOB command, enable a host processor to load an alternate OS boot image, where the alternate OS boot image is stored in a storage device external to the heterogeneous computing platform.

A computer system executes a machine learning model having multiple layers, and includes host and work accelerator processors. A window size representing a number of layers to be loaded into accelerator memory is determined. Model data associated with a subset of layers the same size as the window is loaded to the accelerator. The model is iteratively executed by processing a current layer to provide output data and storing this in accelerator memory, offloading the output data to host memory, replacing model data for an already processed layer with model data corresponding to a next layer, and moving to a next layer. The window size is updated during execution based on a transfer duration for loading into accelerator memory, a transfer duration for loading into host memory, or a processing duration of a layer.

In one aspect, a method includes receiving, in a first wireless device, a data transmission including at least one orthogonal frequency division multiplexing (OFDM) packet from a second wireless device; processing the at least one OFDM packet to recover data and providing the data to a host processor of the first wireless device; encoding, in the first wireless device, at least one decoded symbol of the at least one OFDM packet using forward error correction coding; processing the encoded at least one decoded symbol to recover at least one corresponding transmission symbol of the at least one OFDM packet; and determining a distance estimate between the first wireless device and the second wireless device based at least in part on the corresponding transmitted symbols.

The application provides a method and system for optimizing a DSP core simulation based on a SIMD instruction, wherein the method comprises the following steps: firstly, obtaining a DSP simulation project file, and identifying target instructions with CPU occupation time reaching a preset threshold by combining a performance profiling tool; secondly, analyzing the semantics of the target instructions and extracting parallel operations, and matching a host processor SIMD instruction set to determine a corresponding execution function; thirdly, writing a processing function for calling the execution function; fourthly, replacing original simulation logic of the target instructions in the source code with a processing function call, and supplementing a file reference declaration; and finally, recompiling through a compiler adapted to the SIMD instruction set to generate an optimized executable file, namely a target executable file. The application can effectively improve the simulation running speed of a VLIW type DSP core, has strong optimization targeting, and guarantees accurate simulation calculation results.

Disclosed herein is a sensor system that detects a stylus on at least one panel surface having an effective region. The sensor system includes a memory device including computer-executable instructions, and a processor. The processor, when loaded with the computer-executable instructions, performs: and obtaining a position of the stylus and a pen pressure value indicating a pressure applied to a pen tip of the stylus; outputting the position and the pen pressure value to a host processor. In response to the position being outside the effective region, the processor performs processing to conceal from the host processor occurrence of at least one of a pen-down indicating the stylus contacting the panel surface and a pen-up indicating the stylus being removed from the panel surface.

Implementations for chiplet fault management through hierarchical error reporting and coordinated recovery in an accelerator interconnect. In some implementations, a system for a UALink-based network comprises a chiplet die coupled to an accelerator die, a management agent on the accelerator die, and a centralized controller. Upon fault detection, the chiplet die transmits a fault notification to the accelerator die, the management agent reports the fault to the centralized controller, and the centralized controller determines a recovery action based on the fault identifier and severity. In some implementations, the accelerator die reports the fault through dual paths, to a host processor via CXL or PCIe error reporting and to the centralized controller via the management agent, and the host processor and the centralized controller coordinate recovery, with the host managing workload-level recovery and the centralized controller managing network-level recovery.

The application discloses a bottom-layer security defense architecture and method based on thermodynamic entropy and nanosecond physical short circuit, which comprises a thermodynamic chaotic true random number generator configured to collect physical thermal noise and generate a true random number; a time-space jump memory management configured to dynamically remap the physical storage address of a volatile memory based on the true random number; a programmable hardware logic unit configured to run independently of a host processor and perform out-of-band polling on a physical intrusion detection signal; and a physical short circuit module connected between the power supply rail and the ground of the volatile memory, wherein the programmable hardware logic unit sends a trigger signal to the physical short circuit module when detecting the physical intrusion signal, and the physical short circuit module responds to the trigger signal to short the power supply rail of the volatile memory to the ground within a preset transient time threshold, so that the physical level data destruction less than 5 nanoseconds and the dynamic address confusion driven by the true random number are realized.

The present application relates to the technical field of image processing, and more particularly to a video decoding and Unreal Engine rendering method based on GPU full-link zero-copy, which comprises the following steps: step one, hardware decoding of an input video code stream on a GPU, and construction of a motion vector description buffer for storing compressed domain motion vector information in macroblock order; step two, reading of the motion vector description buffer by a calculation shader on the GPU to generate a dynamic special effect control buffer corresponding to each macroblock; and step three, in the post-processing material of the Unreal Engine rendering module, taking a shared video texture resource as an input texture and outputting a video picture. The present application realizes unified management of pixel data and motion data without relying on a host processor and without excessively occupying video memory bandwidth, significantly reduces delay, and improves special effect stability and direction consistency.

Systems and methods for Unified Extensible Firmware Interface (UEFI)-level processing of Out-of-Band (OOB) commands in heterogeneous computing platforms. In some embodiments, an Information Handling System (IHS) may include: a heterogeneous computing platform having a plurality of devices, and an OOB Microcontroller Unit (MCU), Embedded Controller (EC), or networking device integrated into or coupled to the heterogeneous computing platform and distinct from a host processor of the heterogeneous computing platform, where the OOB MCU, EC, or networking device is configured to: receive an OOB packet while the host processor is in a low-power state, and execute an OOB command contained in the OOB packet, by the host processor, at least in part through initialization of UEFI without initialization of any video device.

A system on chip includes an accelerator configured to generate a demand request for demand data corresponding to a neural network operation based on instructions received from a host processor, and to generate a prefetch request for prefetch data based on a memory access pattern predicted from the neural network operation; a memory controller configured to read the demand data from a memory based on the demand request, and read the prefetch data from the memory based on the prefetch request; and a system cache configured to store at least one of prefetch data and demand data read from the memory as read data, where the accelerator is configured to perform the neural network operation on the read data received from the system cache.

A data processing system is presented that is configured as a server in a client-server configuration for executing applications that a client in the client-server configuration can offload as execution tasks for execution on the server. The data processing system includes a reconfigurable processor, a storage device that stores configuration files for the applications, and a host processor that is coupled to the storage device and to the reconfigurable processor. The host processor is configured to receive an execution task of the execution tasks with an identifier of an application from the client, retrieve a configuration file that is associated with the application from the storage device using the identifier of the application, configure the reconfigurable processor with the configuration file, and start execution of the application on the reconfigurable processor, whereby the reconfigurable processor provides output data of the execution of the application to the client.

A satellite-borne safety intelligent computing system is used for guaranteeing safety of a satellite edge computing system and comprises a host processor, an AI accelerator and a safety bus connected with the host processor and the accelerator. The satellite-borne safe intelligent computing system further comprises a bus stream encoding and decoding engine which is embedded in the interface controller of the data bus and used for encrypting and decrypting transmission data of the data bus. By encrypting the cache stream on the data bus, key data such as Bias bias cache and the like can be protected. In addition, an attacker can be prevented from stealing structural information of the neural network model through interrupt signals by interrupting obfuscated codes, dual protection of'signal + data 'is formed, and time sequence detection Trojan horse and side channel attacks can be effectively resisted.

A system is provided including a host processor, a plurality of service processors, a universal processor associated with the host processor and capable of exchanging data with each service processor, a first user device of the first user and a second user device of a second user. The universal processor receives a request from the first user device for a data transaction between the host processor and a service processor, and in response generates a code that can be interpreted by the service processor. Universal processor transmits the code to the first user device, which transmits the code to the second user device. The second user device transmits the code to the service processor. The service processor decodes the code and requests the universal processor to perform the data transaction with the host processor. In response, the universal processor sets up the data transaction.

A system on chip includes an input output (IO) device configured to perform a direct memory access operation on a memory; an access control device configured to search for mapping information between a plurality of virtual identifiers corresponding to the plurality of virtual machines, respectively, and block a direct memory access operation based on a search result; and a host processor configured to provide a target address accessed by the direct memory access operation and a target virtual identifier corresponding to a driving virtual machine driving the IO device to the access control device.

The invention relates to reverse publication of subtasks from an accelerator to a host processor using cache storage. A computing system includes a main processor and an accelerator. The host processor includes a cache. The main processor is configured to assign a compute task to the accelerator. The accelerator is used to select a sub-task of the compute task and to allocate the sub-task back to the main processor by storing the sub-task directly into a cache of the main processor.

A memory device includes: a memory storing instructions; and a processing unit including one or more processors, wherein the memory device is connected with a host processor through an interface, and wherein, the instructions, when executed by the processing unit, cause the memory device to: select, from among memory blocks stored in the memory, candidate hot memory blocks, the selecting based on access counts of the respective memory blocks stored in the memory; select a hot sub-block based on a number access counts of respective sub-blocks, including the hot sub-block, split from the selected candidate hot memory blocks; and transmit the selected hot sub-block to the host processor, based on a memory command regarding the hot sub-block, wherein the memory command is received from the host processor by the processing unit.

Provided is a computer including a host processor which, in operation, generates a stroke image representing a stroke indicated by a series of coordinate data indicating a plurality of positions of a pen on a touch surface and generates a video signal representing the stroke image, a timing controller which, in operation, controls, based on the video signal, a potential of each of a plurality of gate lines provided in a display, and a temporary stroke image generation processor which in operation, generates, in parallel with the host processor, a temporary stroke image representing a same stroke as the stroke of the stroke image, in which the temporary stroke image is superimposed on the video signal before the video signal is supplied to the timing controller.

The present disclosure discloses a synchronized transmission system and method for dual-source wireless audio. The system comprises an audio device, a first audio source device, and a second audio source device. The audio device comprises a host processor and a plurality of controllers. The first audio source device establishes a first communication link with a first controller among the plurality of controllers to perform audio data transmission for a first audio stream; the second audio source device establishes a second communication link with a second controller among the plurality of controllers to perform audio data transmission for a second audio stream.

Disclosed in the present application are a bridging system and a computing architecture in the technical field of computers. The bridging system provided in the present application comprises a root device bridge controller and a slave device bridge controller. The two controllers communicate with each other by using a target bus standard, such that address configuration of the two controllers can be implemented without the aid of a host processor. The communication process does not require the participation of an external CPU, thereby reducing the complexity of chip configurations and communications. While ensuring high-speed data transmission, the present application simplifies and optimizes system architecture, and allows for more flexible overall design, great compatibility, and higher communication efficiency.

The invention discloses a method for a display driving circuit, comprising the following steps: receiving an input frame from a main processor, the input frame having a plurality of segments; detecting an earliest horizontal sync start packet in the plurality of segments, where the earliest horizontal sync start packet indicates a start of an earliest segment of a full-refresh display area on an output frame; and updating the full-refresh display area on the output frame when the earliest horizontal synchronization start packet of the earliest segment of the full-refresh display area is detected.

In some aspects, a Bluetooth (BT) device may include a BT controller configured to receive a power state indication from a host processor of the BT device, the power state indication to indicate a power state corresponding to a power source being utilized by the BT device; and to control one or more BT activities of the BT device according to a BT communication scheme, the BT controller to configure the BT communication scheme based on the power state indication.

The invention discloses a network defense detection method, device and equipment, a storage medium and a product thereof, and relates to the technical field of network security, the method is applied to a coprocessor module arranged in a terminal, the coprocessor module is used for network security testing, and the method comprises the following steps: monitoring a network service enabling event of the terminal, loading a corresponding attack script according to the started service to carry out a network security test; in the testing process, comparing a first transfer path of the protocol state expected by the attack script with a second transfer path of the protocol state actually executed by the main processor, and judging whether the first transfer path is consistent with the second transfer path or not; and if the first transfer path is not consistent with the second transfer path, determining that an exception exists in the test, and controlling a communication module of the terminal to repair the corresponding security hole. That is, the whole process from vulnerability identification to communication layer repair can be completed without depending on external network interaction, so that the autonomous defense capability of the Internet of Things terminal in a complex network environment is enhanced.

A hardware accelerator can receive, from a host processor, a slice of input data at a time-step. The hardware accelerator can process the input data using a machine learning model deployed on the hardware accelerator to compute a respective probability among multiple probabilities for each of multiple classes. The respective probability for each class being a likelihood that content in the slice belongs to the class. The hardware accelerator can determine, from the multiple probabilities, a preset number of highest probabilities for the slice of input data. The hardware accelerator can transmit the preset number of highest probabilities for the slice to the host processor. Related apparatus, systems, techniques and articles are also described.

In accordance with the described techniques, a device includes a host processor, a memory, and a memory physical layer. The memory physical layer enters an enhanced low power state in which a power supply is disconnected from a portion of the memory physical layer while the memory is inactive with respect to servicing memory requests of the host processor. In addition, the memory physical layer exits the enhanced low power state responsive to the memory being active with respect to servicing memory requests of the host processor and / or at least one memory request being enqueued for servicing by the memory.

Provided is a memory system and a method for improving bandwidth utilization in the memory system that includes receiving, at a host processor, a first read request from an input buffer, determining a combinable address range associated with the first read request, identifying one or more additional read requests in the input buffer having access addresses within the combinable address range, when one or more additional read requests are identified, modifying the first read request to represent the one or more additional read requests using a bit vector indicating their presence within the combinable address range, packing the modified first read request into a single slot of an outgoing flit, and transmitting the flit over an outgoing communication link.