3106 results about "Term memory" patented technology

A computer system implements a unified framework integrating an adaptive elastic funnel (AEF) with a convergent intelligence fabric (CIF) for flexible and contextualized multi-agent AI and human collaboration at scale. The system provides a universal multi-modal key-value subsystem for sharing partial computations across agents, implements a hybrid greedy / non-greedy placement strategy for dynamic memory management, orchestrates dynamic computational workflows and tensor workflows using hierarchical tensor-fragment scheduling, enables cross-agent orchestration with policy-based privacy preservation, and incorporates quantum-resistant secure memory enclaves. The architecture supports continuous learning without catastrophic forgetting, compositional reasoning across modalities, and secure task execution in distributed environments. This integration enables unprecedented computational efficiency, secure collaboration, and adaptive intelligence in high-dimensional decision-making environments while supporting incremental adoption through modular interfaces.

The invention belongs to the field of industrial control and computer data security, and particularly relates to a millisecond-level power failure data protection system for an industrial control panel. The invention discloses a millisecond power failure data protection system for an industrial control panel. The millisecond power failure data protection system comprises a core processing component, a real-time synchronous shadow memory component, a bus voltage monitoring component, a pre-entropy reduction logic control component, a nonvolatile storage component and a flight control bus arbitration component. The bus voltage monitoring assembly monitors a voltage drop trend and performs early warning, the pre-entropy reduction logic control assembly calculates a minimum data survival set according to energy entropy, the real-time synchronous shadow memory assembly constructs a synchronous shadow control domain and atomizes data, and the flight control bus arbitration assembly compulsively takes over a bus and freezes processor access at the moment of power failure. Atomized writing of data into the nonvolatile storage component is guaranteed. According to the invention, zero-delay data protection and millisecond-level hot start recovery at the moment of power failure are realized, and the data security and reliability of the industrial control equipment in a severe environment are enhanced.

A method includes: receiving, by a computing device of a first vehicle, a command from a host device; in response to receiving the command, storing a new device secret in memory; generating, by the computing device using the new device secret, a triple comprising an identifier, a certificate, and a public key; and sending, by the computing device, the triple to a second vehicle, where the second vehicle is configured to verify an identity of the first vehicle using the triple.

A user device joins a communication session between the user device and a plurality of devices. The user device and the plurality of devices use a Message Layer Security (MLS) protocol for end-to-end security. The user device identifies a first device of the plurality of devices and obtains a portion of authentication tree information associated with the communication session. The portion being associated with the first device. The user device authenticates the first device based on obtaining the portion of the authentication tree information.

This application relates to a tensor processing method, apparatus, device, and storage medium. The method includes: acquiring basic information and upsampling coefficients of an input tensor; wherein the basic information includes the storage address of the input tensor in memory; reading the input tensor from memory based on the storage address and storing the input tensor in a cache area; in the cache area, determining the number of copies based on the upsampling coefficients, and performing the number of copies on the input tensor to obtain a target tensor. This method can improve the upsampling efficiency of input tensors.

The utility model discloses a COME board with ECC memory expansion interface, include: mainboard body, the mainboard body surface panel carries memory one side is equipped with the on -board expansion seat for the memory expansion of mainboard storage and operation, the on -board expansion seat upper end is equipped with the memory pressure plate for the compression of memory combination after expansion switching over through the slot hole of surface both ends, the utility model discloses the cooperation of positioning stand and memory positioning hole, realize the three -dimensional space orientation of memory stick main body on the mainboard body, avoid horizontal or longitudinal displacement, simultaneously, the memory pressure plate is connected through locking screw and the locking slot of on -board expansion seat, forms the even compression force to memory expansion switching over board, ensures the close contact of memory stick main body and memory slot, memory switching over plug and memory expansion slot, significantly improves the connection reliability under the complex environment such as vibration, high temperature, and prevents the data transmission unstable problem caused by poor contact.

Devices and methods are disclosed, including receiving, by a memory controller of a memory device, a memory request from a host device; collecting packet trace data from the memory request; including the packet trace data in a log stored in a memory array of the memory device; and returning the log to the host device.

A present invention embodiment improves responsiveness when looping on speculative atomic memory updates. A conditionally atomic updating instruction is determined to have encountered a fail condition. A fail loop of the conditionally atomic updating instruction is determined to have occurred. In response to determining that the conditionally atomic updating instruction has encountered the fail condition and that the fail loop has occurred, a count that each cross-interrogation request (XI) instruction rejection contributes toward an XI rejection count that is compared to a threshold is increased. In response to the XI rejection count satisfying the threshold, performing a selfish store mitigation operation, wherein the selfish store mitigation operation blocks a thread or core responsible for the fail loop from inserting a new instruction into an instruction pipeline and flushes non-completed instructions of the thread or core from the instruction pipeline.

This invention belongs to the field of intelligent agent large language model service technology, and discloses a chip computing system, device and application for intelligent agent large language model. Through the collaborative design of hardware architecture and software scheduling, it systematically solves the core technical challenges faced by intelligent agent large language model services. Specifically, it includes a hardware and software collaborative implementation scheme for resource partitioning, key-value cache management and runtime scheduling of pre-filling, decoding and tool call related workloads in a multi-chip encapsulation and inconsistent memory access environment.

This invention relates to the field of intelligent predictive control technology, and more particularly to a digital twin predictive-driven electrochemical intelligent control system and method for circulating cooling water, comprising a physical operation device and a control device. The control device collects water quality monitoring parameters through a data acquisition module, and a state assessment module uses the entropy weight method to map and calculate a comprehensive index. A trend inference module inputs the comprehensive index into a long short-term memory network model for forward propagation, outputting a predicted water quality index, which is then iteratively optimized by a hyperparameter optimization unit using a sparrow search algorithm to optimize the network connection parameters. An instruction optimization module compares the predicted water quality index with a safety threshold to generate control instructions, driving the physical operation device to perform electric field adjustment, mechanical scaling, and coordinated water replenishment and chemical dosing. A virtual mapping module constructs a three-dimensional digital model to achieve state early warning. This invention solves the technical problem of lag in existing feedback control, achieving precise pre-control of water quality in circulating cooling water systems.

The application discloses a latching device for a DIMM memory slot and relates to the technical field of memory bar fixing, which comprises a fixing seat, an unlocking top block and a pressing handle. The unlocking top block is movably arranged on the fixing seat, and a guide groove is arranged on the unlocking top block to guide the accurate alignment of a memory bar and a memory slot. The pressing handle is movably connected to the fixing seat and is in linkage with the unlocking top block. When the pressing handle is pressed by external force to press the memory bar, the pressing handle drives the memory bar to enter the memory slot and is maintained at a locking position. When the pressing handle is separated from the memory bar by external force, the unlocking top block is driven to generate a pushing force to separate the memory bar from the memory slot, so that the memory bar is released from the memory slot. The application can provide a mechanical fixing solution for synchronously locking and stably releasing the memory bar in the slot.

A processing system including processing cores, a shared memory, a shift table that stores a maximum number of reservations to locations in the memory, and an exclusive monitor that uses the shift table and an eviction policy to enforce core synchronization. The eviction policy is based on priority, age of valid reservations, shift table fullness state, and reservation memory conflict. The shift table may include a memory address and a size value indicative of a flexible amount of reserved memory at the memory address. The exclusive monitor evicts an oldest reservation in the shift table having a same or lower priority level as the new reservation. The exclusive monitor rejects the new reservation when the shift table is full of higher priority reservations. Reservations are shifted to maintain age status. Stale reservations may be invalidated or have their priority lowered. Conflicting reservations may be made with the same priority level.

Disclosed in the embodiments of the present application are a root file system loading method and a related apparatus. In the method, a part of a virtual memory is simulated as a random access memory disk (RAMDISK) mechanism used by a block device. First, a read-only memory file system (ROMFS) mirror image file on an initial physical address is acquired; and then, a virtual address corresponding to the initial physical address of the ROMFS mirror image file is directly used as the starting address of the block device, such that the copy operation of copying the ROMFS mirror image file to the block device is executed on the initial physical address, thereby formatting the block device. Then, a kernel can be booted by means of mounting the ROMFS mirror image file in the block device as a root file system. By using the ROMFS image file as a root file system and reducing copy operations during a boot process, the kernel boot time is shortened in read‑only application scenarios requiring fast boot, thereby achieving fast kernel boot.

Systems, apparatuses, and methods are disclosed for improved matrix–vector operations in accelerators that may be useful or heavy AI training and inference workloads. The disclosed technology provides arrangements that permit more efficient computation by, for example, performing calculations without repeated conversion between numeric domains. In some implementations, a compute-in-memory (CIM) macro is configured to perform a vector matrix multiplication (VMM) operation between a vector of activation values and a matrix of weight values in floating point formats. The CIM macro has a functional block configured to align mantissa bits of primitive products between the activation values and the weight values by shifting the mantissa bits and an adder tree configured to output an accumulation value of the primitive products in an integer format by adding the shifted mantissa bits.

This invention relates to the field of communication technology, specifically to a method for implementing a virtual serial port based on Hook technology. The method includes the following steps: replacing functions of the serial port operation API to open, set, and close the serial port and transmit data over the network; compiling this into a dynamic link library; using the dynamic link library to obtain the addresses of the serial port operation API functions CreateFileW, ReadFile, and WriteFile in the host computer process space; constructing a JMP jump instruction; writing it at the beginning of the target API function to redirect to a custom Hook function during the call; the custom Hook function calls the original API functions as needed; and canceling the Hook writes back the original machine code and restores memory attributes, resulting in a switchable monitoring function. This invention solves the problems of traditional serial port implementations, such as easy conflicts when multiple programs compete for usage, difficulty in flexibly monitoring and debugging serial communication, inability to conveniently simulate specific serial port scenarios, and poor scalability and compatibility with new systems or hardware platforms.

This invention belongs to the field of image storage technology and solves the technical problem of video discontinuity caused by existing storage methods that transfer real-time video images from different folders to SD cards. It provides a method, apparatus, electronic device, and medium for step-by-step video data storage. The method includes transferring video images from the cache queue to the memory area using a first thread, and then transferring the video files from the memory area to a storage device such as an SD card using a second thread. This ensures that the processes of storing video images from the cache queue into the memory area and further transferring them to the SD card are independent. The first thread continuously creates files in the memory area to write the cached video images to the cache queue, while the second thread performs a second transfer of temporary video from the memory area. This controls the time interval between closing the current file and creating the next file in the memory area, preventing data frames corresponding to previously cached images from overflowing and being lost, thus ensuring video continuity.

Embodiments of the present disclosure relate to the field of processor hardware architecture, and provide an artificial intelligence chip and a computing system. The artificial intelligence chip comprises a first computing core, a shared memory device corresponding to the first computing core, and a data synchronization device. The first computing core is configured to issue a first data request instruction. The data synchronization device is configured to perform a read operation on first data, a flag detection operation, and a synchronization operation according to the first data request instruction. The first data is stored in a global memory device coupled to the artificial intelligence chip. The synchronization operation comprises sending the first data to the shared memory device. The shared memory device is configured to store the first data sent by the data synchronization device for reading by the first computing core. Embodiments of the present disclosure hardwareize data synchronization and retry, significantly reduce communication delay, and release core computing resources of the artificial intelligence chip.

The application relates to the technical field of flexible direct current power transmission, and particularly provides a lightweight real-time memory database transaction concurrent control method and device, which comprises the following steps: S101. Classifying to-be-processed transactions through cluster analysis to determine the cluster to which the to-be-processed transactions belong; S102. Obtaining a transaction lock corresponding to the to-be-processed transaction in the cluster to which the to-be-processed transaction belongs and a data lock called by the to-be-processed transaction, and executing S103 under the condition that the acquisition state is successful; S103. Conflict verification is performed on the to-be-processed transaction, if there is a conflict, the to-be-processed transaction is prevented, otherwise, the to-be-processed transaction is executed. The technical scheme provided by the application meets the demand of high-efficiency access of Internet of Things data and improves the transaction execution performance of the real-time memory database.

Methods, systems, and apparatus, including computer programs encoded on computer storage media, for table detection using text streams. One of the methods includes detecting, in a text stream and using column identification data, text for one or more cells in a table; creating, using the text for at least some of the one or more cells in the table, a data structure for the cell a) that associates two or more values from the table and b) for use by a downstream system as part of a natural language analysis process of data from the text stream; and storing, in memory, the data structure.

The system clearly displays the fields corresponding to the land parcel numbers entered by the field managers, etc. [Solution] This is a program to be executed by a computer equipped with a processor and memory. The program causes the processor to perform the following steps: acquire text information relating to the land number of a field; compare the acquired text information with the land number in the land register to identify the official land number of the field; associate the identified official land number with a polygon representing the field; and display the land number, the official land number, and the identification information of the polygon associated with the official land number in association with map data.

This invention belongs to the field of electronic digital data processing technology, specifically relating to a low-altitude communication data anomaly detection system and method based on edge intelligence. The system parses protocol fields from the raw bitstream of the low-altitude communication link layer, extracts type identifiers and payload lengths to construct a protocol state machine transition matrix, and utilizes a Long Short-Term Memory (LSTM) network to extract state transition probability sequence features. Geographically adjacent edge nodes are set as micro-federated learning groups. Each node, after training using local features, only uploads network gating weight parameters to its neighboring nodes for weighted aggregation to update its local model. An alarm is triggered when the real-time state transition probability sequence deviates from the normal transition matrix and exceeds a preset topology threshold. This invention can identify protocol state machine logic errors and transition anomalies, reducing the amount of communication data required for collaborative model updates between edge nodes.

For crypto assets mounted to pods as files or environment variables, security and compliance can be complex and therefore may be inadequately managed. [Solution] The system may include memory and a processor that communicates with the memory. The processor may be configured to perform operations. The operations may include steps to monitor network actions between resources in a network and steps to extract encrypted data from the network actions. The operations may include steps to detect connection security data from the encrypted data and steps to obtain resource health reports for the resources in the network. The operations may include steps to merge the connection security data with the resource health reports and steps to generate security compliance reports.

This application discloses a memory expansion method and related device. According to this method, when creating a zygote virtual machine, the electronic device can allocate virtual addresses corresponding to larger memory in the Java memory space and reserve a portion of the virtual addresses unused. After a cold start of the application, the electronic device can monitor the memory of the Java memory space in the virtual machine corresponding to the application. Under certain conditions, the Java memory space in the virtual machine corresponding to the application can not only continue to use the original virtual addresses but also use the reserved virtual addresses, thereby expanding the Java memory of the application. Through this method, the electronic device can expand the Java memory space for specific applications and scenarios (e.g., excessive memory usage) while ensuring system stability, thus avoiding stuttering and other problems caused by garbage collection (GC) when memory usage is too high.

Systems, apparatuses, and methods are disclosed for improved matrix-vector operations in accelerators that may be useful or heavy AI training and inference workloads. The disclosed technology provides arrangements that permit more efficient computation by, for example, performing calculations without repeated conversion between numeric domains. In some implementations, a compute-in-memory (CIM) macro is configured to perform a vector matrix multiplication (VMM) operation between a vector of activation values and a matrix of weight values in floating point formats. The CIM macro has a functional block configured to align mantissa bits of primitive products between the activation values and the weight values by shifting the mantissa bits and an adder tree configured to output an accumulation value of the primitive products in an integer format by adding the shifted mantissa bits.

A server issues challenge data and transmits the challenge data to a client. The client stores encrypted group data including a plurality of encrypted data encrypted with a server key, and parameter data A, in a memory, receives the challenge data, generates response data using a response key on the client side, and transmits the response data, the encrypted group data, and the parameter data A to the server. The server selects encrypted data to be used from the received encrypted group data, based on the received parameter data A, sets a response key on the server side, based on the selected encrypted data and data decrypted with the server key, verifies the received response data, based on the challenge data and the response key on the server side, and notifies a result of the verification to the client. The client receives the notification.

A Network-On-Chip (NoC) -based accelerator is disclosed for performing in-network and in-memory sparse tensor computations between an activation tensor and a weight tensor. The accelerator comprises a plurality of NoC nodes organized in a first two-dimensional (2D) network. Each NoC node includes a plurality of kernels organized in a second 2D network, and each kernel contains a plurality of cores organized in a third 2D network. The weight tensor is evenly distributed among the NoC nodes in the first 2D network. Within each NoC node, the kernels are configured to perform output-channel gathering on the weight tensor, while the cores within each kernel perform input-channel gathering. These gathering processes generate a condensed weight tensor that is evenly distributed among the NoC nodes. The activation tensor is broadcasted to the NoC nodes, enabling parallel sparse tensor computation using the evenly distributed and condensed weight tensor.

Disclosed are systems and methods for enhancing local node performance in a storage system through offloading cache replacement tasks to remote nodes. A periodic time-series analysis of CPU cycle utilization and network latency is conducted on one or more arrays to identify and / or forecast underutilized nodes in the one or more arrays. A first array detects a shortage of available cache slots in an allocation queue and identifies underutilized remote nodes in either its own array or another array. The array shares the metadata pages with the remote node. A worker thread on the remote node runs a search algorithm on the received meta data pages and creates a list of candidate replacement memory slots.

To achieve both stabilization of treated water quality and energy conservation. [Solution] A program to be executed by a computer having a processor and memory, the program causing the processor to perform the following steps: receiving a predetermined amount of wastewater flowing through the main stream of a wastewater treatment facility as sidestream wastewater; controlling water treatment for a predetermined amount of wastewater; measuring a predetermined value in the water treatment; and passing information relating to the measured result to the control of the main stream.

This disclosure relates to the field of data processing technology, and discloses a video processing method, apparatus, electronic device, and storage medium. The video processing method, applied to a terminal device, includes: acquiring a video; verifying the video; uploading the video to a server when it is determined, based on the verification result, that the video has not been edited; and receiving first indication information from the server, the first indication information being configured to indicate whether the video has been successfully uploaded to the server. This disclosure can distinguish between source videos and edited videos, so that when the video is an unedited source video, no transcoding file is obtained, reducing the memory usage of the terminal device and improving the success rate of video upload.