93 results about "Auxiliary memory" patented technology

The invention discloses a memory space indexing system and method for power grid data, and the system comprises a variable-length prefix compression coding unit and a multi-level indexing unit. The variable-length prefix compression coding unit is used for storing index information to adapt to the real-time change of power grid data; the multi-level index unit is used for retaining data which are most frequently accessed in a rapid memory, storing data which are less accessed in an auxiliary memory which is slower but larger in capacity, monitoring the change of power grid data in real time, dynamically encoding new data, updating an index structure, dynamically adjusting the size and the structure of an index according to the data access frequency and the updating frequency, and storing the data which are most frequently accessed in the rapid memory and the auxiliary memory which is slower but larger in capacity. Index nodes are split or merged by using the flexibility of compression coding of prefixes with variable lengths so as to adapt to the change of data volume. According to the method, the size and the structure of the index can be dynamically adjusted, so that the memory occupation is reduced, and the indexing efficiency is improved.

An improved content indexing (CI) system is disclosed herein. For example, the improved CI system may include a distributed architecture of client computing devices, media agents, a single backup and CI database, and a pool of servers. After a file backup occurs, the backup and CI database may include file metadata indices and other information associated with backed up files. Servers in the pool of servers may, in parallel, query the backup and CI database for a list of files assigned to the respective server that have not been content indexed. The servers may then request a media agent to restore the assigned files from secondary storage and provide the restored files to the servers. The servers may then content index the received restored files. Once the content indexing is complete, the servers can send the content index information to the backup and CI database for storage.

Described herein is the simulation of an input quantum circuit, including a machine-readable specification of the quantum circuit. Aspects include partitioning the input quantum circuit into a set of sub-circuits based on at least two sets of qubits identified for tensor slicing, where the resulting sub-circuits have associated qubit sets for tensor slicing. The simulation can be performed in stages, one stage for each sub-circuit. The qubit sets associated with the sub-circuits can be used to partition the simulation quantum state tensor of the input quantum state circuit into quantum state tensor slices, and the quantum gates in the sub-circuits can be used to update the quantum state tensor slices into updated quantum state tensor slices. The updated quantum state tensor slices are stored as micro-slices in auxiliary memory.

A data processing method and apparatus, and a heterogeneous system, pertaining to the field of computer technologies are provided. The heterogeneous system includes a processor connected to an accelerator. A secondary memory is connected to the accelerator. The processor is configured to write to-be-processed data into the secondary memory and trigger the accelerator to access and process the to-be-processed data stored in the secondary memory according to a processing instruction. The accelerator is configured to write a processing result of the to-be-processed data into the secondary memory and to trigger the processor to read the processing result. Processing efficiency is enhanced by reducing the number of times of interaction between the processor and the accelerator and simplifying the procedure for data processing.

1. Name of the Design Product: Formula Auxiliary Memory Board. 2. Use of the Design Product: The design product is used as a writing board for auxiliary memory of formulas in applied mathematics. 3. Design Key Points of the Design Product: Lies in the shape. 4. Picture or Photograph that Best Illustrates the Design Key Points: Perspective view.

Methods, systems, and devices for memory array seasoning are described. Some memory cells may have an undesirably high threshold voltage and thus a seasoning operation may be performed on a target memory cell. To season the target memory cell, a bit line and a word line associated with the cell may be activated. Additionally or alternatively, a word line coupled with a second memory cell (e.g., a helper memory cell) that shares the activated bit line may be activated. Accordingly, current flowing across the target memory cell may be increased, which may reduce its threshold voltage.

The invention relates to the technical field of memory management, in particular to a dynamic memory management method based on a bidirectional queue, electronic equipment and a medium. A first pointer and a second pointer are set to orderly control bidirectional insertion or deletion of queue elements, a queue main memory is started firstly, and when the storage requirement of the queue elements is not met, areas stored with the queue elements are reordered and then a queue auxiliary memory is started; when the queue main memory and the queue auxiliary memory are not enough to meet the storage requirements of the queue elements, updating the sizes of the queue main memory and the queue auxiliary memory to expand the queue memory, reordering discrete regions, in which the queue elements are stored, in the original queue memory, generating a continuous region, and writing the continuous region into a new queue main memory; the frequency of queue element copying and memory releasing in the dynamic change process of the bidirectional queue is reduced, and the memory utilization rate of the bidirectional queue is increased.

1. Name of the Design Product: Device for Assisting Chromatographic Column Memory Function. 2. Use of the Design Product: This design product is used to provide an auxiliary memory function for chromatographic columns. 3. Design Key Points of the Design Product: Lies in the shape. 4. Picture or Photograph that Best Illustrates the Design Key Points: Perspective View 1.

An example system includes a first memory that includes primary storage; a second memory that includes secondary storage; and a control system for predicting paths through a test program that will be taken during a planned execution of the test program, and for causing test data associated with the test program to be stored in the first memory or the second memory based on the paths predicted.

A method of operating a ring communication network, including providing a management device having a first processor, a first memory, a first communicator, and a computer program stored in the first memory and capable of running on the first processor; providing a network device having a network processor, a network memory, and a network communicator; disposing an auxiliary memory in the network device; organizing the management device and the network device to form the ring communication network; determining a location of the auxiliary memory in the ring communication network; and assigning a transmission direction such that a transmission distance between the management device and the auxiliary memory is minimized.

Embodiments of the present disclosure relate to a method of protecting a system such as a microcontroller and a corresponding system. A system comprising a processing unit, a memory configured to store at least one first set of instructions and one second set of instructions for execution by the processing unit, the processing unit being configured to sequentially fetch instructions of the first set and instructions of the second set from the memory for their execution. The system further comprises a controller comprising a first auxiliary memory configured to store a protection criterion, a comparator configured to compare a memory address of each fetched instruction with the protection criterion, and a control circuit configured to trigger a protection mechanism in response to the memory address satisfying the protection criterion, the protection mechanism comprising at least one prohibition of the processing unit to execute again at least a portion of the instructions of the first set during the execution of the instructions of the second set.

This increases the likelihood that storage at a tier relatively close to the computing resources is holding the data at the time it is used to execute a job. [Solution] Before starting the execution of job 102, the job analysis unit 300 analyzes the workflow of job 102 to identify the data that the computing resource 210 will read when executing job 102. The pre-read management unit 1200 controls the pre-reading from secondary storage 240 to primary storage 230 for data identified by the job analysis unit 300 for job 102 where the actual data 920 does not exist in primary storage 230 but does exist in secondary storage 240.

This invention provides a management system for controlling the audio information output from an audio generator when multiple target objects are used separately at multiple locations. [Solution] A management system 10 comprising a first target object 13 and a second target object 14, a user terminal 12, a speaker and audio output device 43 for outputting sound, and a management computer 11 that is communicatively connected to the user terminal 12 and performs processing, wherein the management computer 11 is configured to perform the following processes: storing the first target object 13 and the second target object 14, the first usage location A1 and the second usage location A2 in an auxiliary memory 49; determining which of the first usage location A1 and the second usage location A2 is being used; determining the usage location of the used target object; and controlling the audio information output from the speaker and audio output device 43 based on the determination result of the target object and usage location being used.

To provide an information managing device that facilitates the development of a relationship between a user and the character of the user.SOLUTION: An information managing device 10 includes a processor 19 that executes processes, and is connected to a user terminal 12 via a network 22. This information managing device 10 is configured to cause the processor 19 to execute: a first process of storing, in an auxiliary memory 21, the personality and activity of a character which are generated in accordance with activity information on the character that shows up in a first action application which is run upon operation given to the user terminal 12 from a user 13; and a second process of taking over, as the personality and activity of the character that shows up in a second action application which is run after the first process is executed, and which has different functions from those of the first action application, the personality and activity of the character stored in the auxiliary memory 21 in the first process.SELECTED DRAWING: Figure 1A

When a memory controller reads target data in a memory, the memory controller reads the target data and first check code of the target data from the memory. The memory controller checks the target data using the first check code. If the check fails, it indicates that error data exists in the target data. The memory controller then performs error correction on the target data using the first check code. After failing to perform error correction on the target data using the first check code in the memory, the memory controller performs error correction on the target data using the second check code in the secondary storage.

An IC includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary Chip Select (CS) signal via a primary CS line that connects to the primary memory die. The secondary memory die is coupled to the bus, excluding the primary CS line, and to a secondary CS line carrying a secondary CS signal provided by the primary memory die. The primary memory die is configured to receive a command over the bus, while the primary CS signal is active, in response to identifying that the command is destined to the primary memory die, to execute the command within the primary memory die, and in response to identifying that the command is destined to the secondary memory die, to cause the secondary memory die to execute the command by transferring the primary CS signal on the secondary CS line.

System, comprehensive: an embedded modem with an internal memory whose size is too small to store the received data, which communicates with controllers via a vehicle bus, each controller including a working memory and an auxiliary memory, wherein the modem is programmed to to query the controllers via the bus in order to identify controllers that have available memory in the auxiliary memory, If the available memory is located in the auxiliary memory of a priority controller, the received data is sent to the priority controller via the bus, and Otherwise, if the available memory in the auxiliary memory of a subordinate controller is available, the received data should be sent to the subordinate controller via the bus. to query the controllers via the bus to confirm that the controller storing the received data is available for data storage, and to confirm that the controllers are not operating in a driving mode, and in response to the confirmation, to request the stored data via the bus and to transmit the stored data to a telematics server via a wide area network; the embedded modem is further programmed, if no available memory is found, to reduce the data to a size corresponding to the internal memory of the embedded modem.

A method of defining a logic device is provided in which the definition incorporates the definition of special auxiliary memory cells reserved for the presentation of a special code, incorporating a signature of the definition as a whole so as to constitute a watermark securing the design as a whole, and possibly other information. In certain embodiments, the special code may incorporate recursive signatures from preceding versions of the same device to as to constitute a watermark blockchain. A LUT based FPGA architecture is proposed with special addressable memory cells reserved for this purpose, in which case a programming bitstream may constitute a definition in accordance with the inventive method.

An IC includes a primary memory die and a secondary memory die. The primary memory die is coupled to a bus providing a primary Chip Select (CS) signal via a primary CS line that connects to the primary memory die. The secondary memory die is coupled to the bus, excluding the primary CS line, and to a secondary CS line carrying a secondary CS signal provided by the primary memory die. The primary memory die is configured to receive a command over the bus, while the primary CS signal is active, in response to identifying that the command is destined to the primary memory die, to execute the command within the primary memory die, and in response to identifying that the command is destined to the secondary memory die, to cause the secondary memory die to execute the command by transferring the primary CS signal on the secondary CS line.

A printing system includes a printing device that receives print jobs. The printing device includes a controller having a raster image processing (RIP) system that includes a RIP manager and at least one renderer. The RIP manager detects that the print engine of the printing device is idle. The RIP system renders various jobs using renderers during the idle time and stores the rendered pages in a storage for the RIP system. Once a storage threshold is reached, the RIP system allocates the renderers to render only complex pages within the print job and stores the rendered complex pages to a secondary storage. If a secondary job is active, then available renderers are allocated to rendering pages of the secondary job. Once printing resumes at the print engine, the RIP manager reallocates the rendering resources back to normal.

The disclosure provides a system and method for reducing inference latency of an artificial intelligence (AI) system. During operation, the system can obtain an AI model and compile the AI model to generate at least one Directed Acyclic Graph (DAG), which comprises determining an offset address associated with a piece of intermediate data to be transferred from a primary memory shared among multiple AI accelerators to a secondary memory. The AI accelerators, the primary memory, and the secondary memory are located on the same system on a chip (SoC). The system can then schedule computing tasks, which comprises determining a base address associated with the DAG in the secondary memory, and perform inference based on the DAG, which comprises transferring the piece of intermediate data from the primary memory to the secondary memory based on the offset address and the base address.

The invention discloses an English word note segmentation system and an auxiliary memory method, and belongs to the technical field of English word memory. An English word note segmentation system comprises a segmentation learning module: when a user enters the system for the first time, the user can select to enter the segmentation learning module to learn how to segment words through a manual segmentation module, and mainly learn the segmentation mode of the words according to phonetic symbols and symbols; according to the invention, the word is segmented by using the corresponding symbols and according to the segmentation mode through the segmentation module, so that a learner can more clearly and intuitively master the pronunciation and spelling of the word, and the word is disassembled and marked as a sound knot and a single auxiliary by using the least common symbols, so that the learner is helped to quickly decode, read and memorize the word, and the learning efficiency is improved. The spelling method enables a learner to more clearly and visually master pronunciation and spelling of words, is easy to learn, and is especially easy for Chinese to learn English words.

A method of defining a logic device is provided in which the definition incorporates a definition of a special auxiliary memory cell reserved for presentation of a special code, the signature of the definition incorporated as a whole so as to constitute a watermark that protects the design and possibly other information as a whole. In some embodiments, the special code may incorporate a recursive signature from a previous version of the same device in order to constitute a watermark blockchain. According to the invention, a LUT-based FPGA architecture is proposed having special addressable memory cells reserved for this purpose, in which case the programming bitstream can form the definition according to the method of the invention.

This disclosure provides methods, components, devices and systems for device coordinated dynamic configuration management for high reliability communication. Some aspects more specifically relate to techniques to coordinate the transfer of data between primary and secondary memories of a device such as an access point (AP) for communication with a wireless station (STA). The AP may be capable of storing data in a directly accessible primary memory, and in a secondary memory, which may be inaccessible until the data in the secondary memory is transferred to the primary memory. In some aspects, the AP may dynamically transfer data based on changes in one or more operating modes of a STA. The AP may transfer data from the secondary memory to the primary memory in accordance with the STA entering an active mode, or from the primary memory to the secondary memory in accordance with the STA entering a power saving mode.

The invention belongs to the technical field of valve executing parts, and discloses an executing device based on shape memory alloy, which comprises a sleeve-shaped shell and a sliding block, the sliding block is arranged in the sleeve-shaped shell in a sliding manner, two groups of binding posts are oppositely arranged on the sliding block, and the bottom ends of the two groups of binding posts are respectively connected with two ends of a main memory alloy wire; the lower portion of the main memory alloy wire is connected with the moving part, a main positioning spring is arranged between the moving part and the sliding block, a sealing plug is arranged on the bottom face of the moving part and penetrates through a liquid drainage through hole in the base, two sets of auxiliary memory alloy wires are oppositely arranged on the base, and the top ends of the two sets of auxiliary memory alloy wires are connected with the sliding block. An auxiliary positioning spring is arranged between the sliding block and the base; when the temperature changes, the main memory alloy wire contracts to drive the moving part to move, and the auxiliary memory alloy wire also contracts to pull the sliding block to move downwards by the same distance, so that the position of the moving part is kept unchanged, and the actuator can resist the temperature influence and is more stable and reliable.

Computing device (100) comprising a main memory (104) configured to store a sparse matrix in a dense vector format (106, 108, 110) and to store a second vector (112) or a second matrix, a computing unit (102) configured to multiply the sparse matrix by the second vector or by the second matrix, and a streamer (114) comprising: an indexed loading block (116) comprising a secondary memory (118) and a FIFO memory (120) for requests to send values stored in the secondary memory to the computing unit; an indexed loading engine (122) configured to sequentially generate and store requests in the FIFO request memory according to an order in which the values are intended to be sent to the computing unit; the request storage order being calculated and stored in the form of firmware (124).

In some examples, a data storage device includes a cache memory, an auxiliary memory including at least one memory location associated with a swap, and a processor to: identify the at least one memory location of the auxiliary memory associated with the swap; in response to receiving a write request for writing data, determining whether the write request is a request for writing data into the at least one memory position associated with the swap of the auxiliary memory; in response to determining that the write request is the request for writing data to the at least one memory location of the secondary memory associated with swap, only the data is written to the cache memory.

The invention discloses a semiconductor device, a preparation method thereof and electronic equipment. The semiconductor device comprises a substrate, a plurality of storage units and at least one auxiliary storage layer, the storage layers of two adjacent storage units are arranged at intervals in the direction perpendicular to the substrate; each auxiliary storage layer is located between every two adjacent storage units and located on the periphery of the corresponding channel structure, and the auxiliary storage layers and the storage layers are arranged in a staggered mode in the direction perpendicular to the substrate. The invention relates to but not limited to the technical field of semiconductor devices, in particular to a semiconductor device, a preparation method thereof and electronic equipment, and can solve the problem of coupling between adjacent layers of storage units.

Computer computing device with memory optimized for matrix calculation. Computer computing device (100) comprising a main memory (104) configured to store a sparse matrix in a dense vector format (106, 108, 110) and to store a second vector (112) or a second matrix, a computing unit (102) configured to multiply the sparse matrix by the second vector or by the second matrix, and a loading circuit (114) comprising: - an indexed loading block (116) having a secondary memory (118) and a FIFO query memory (120) for sending values ​​stored in the secondary memory to the computing unit; - an indexed loading engine (122) configured to sequentially generate and store the queries in the FIFO query memory in an order in which the values ​​are intended to be sent to the computing unit;the order in which queries are stored is calculated and stored in the form of a microprogram (124). Figure for the abbreviation: Fig. 1;

A system for reading, writing, and verifying data is provided, where the system for reading data includes: a code cache; and a memory controller connected to the code cache and configured to: receive a read command for reading requested data from a location in a main memory connected to the memory controller through a first interface; reading the first data stored in the position from the main memory; reading a code corresponding to data of a request associated with the read command from the code cache or from an auxiliary memory connected to the memory controller through a second interface different from the first interface; performing error detection and / or correction based on the first data and the code; selecting second data based on a result of the error detection and / or correction; and outputting the second data for the requested data.