432 results about "Network processor" patented technology

The invention provides a complex scene-oriented AI large model lightweight deployment method, and relates to the technical field of edge computing, and the method comprises the steps: carrying out the structured pruning of a pre-trained Transform network based on the attention head importance score, carrying out the dynamic sparsification of the activation state of a feedforward network according to the input tensor entropy value, employing the dynamic mixing precision quantization, and carrying out the reconstruction of an AI large model. Obtaining network parameters after pruning quantization; deploying the pruned and quantized network parameters to an edge computing device, distributing a feature extraction operator to a neural network processor through a heterogeneous computing scheduler, and unloading a classification operator to a multi-core central processing unit; and managing an on-chip memory in combination with a virtual memory paging mechanism, realizing zero-copy data transmission by utilizing a direct memory access controller, and outputting a reasoning result tensor. According to the method, efficient and reliable operation of the large model at the resource-constrained edge node is realized.

The invention provides a power grid dispatching strategy optimization method and system, and the method comprises the steps: deploying a device based on a quantum entanglement technology between transformer substations, and collecting the state information of a power grid, and encrypting and transmitting the state information to a control center through a quantum network; a pulse neural network processor is used in a control center to extract spatial-temporal characteristics, and a quantum game theory model is used to generate an optimized scheduling strategy. Multi-modal verification data is collected, including visual deformation, abnormal sound monitoring, and operational resistance data. A genetic algorithm and deep reinforcement learning are utilized to optimize a decision model, and a dynamic weight distribution mechanism is included. And through a photon-quantum hybrid computing architecture execution model, a scheduling strategy is collaboratively optimized, and a result is fed back to a physical power grid. According to the method, the quantum technology and the spiking neural network are combined, new energy fluctuation is captured in real time, the multi-target weight is dynamically adjusted through the quantum game theory model, and the scheduling strategy robustness is improved. And a photon-quantum hybrid computing architecture is adopted, so that the feature extraction speed and the optimization efficiency are improved.

The invention discloses a task scheduling method and device, equipment, a storage medium and a product, and relates to the technical field of artificial intelligence. According to the method, a large model is divided into a plurality of sub-tasks, the computing power demand is quantified in real time, and the matching score of the schedulable task and each neural network processor node is calculated in combination with the computing power evaluation information of each neural network processor node; the schedulable task with the highest priority in the scheduling queue is allocated to the neural network processor node with the highest matching score, and all subtasks of different large models are reasonably allocated through loop execution; besides, priorities are distributed to the to-be-scheduled sub-tasks in the scheduling queue based on the scheduling strategy, scheduling is carried out through a greedy algorithm, it can be guaranteed that each scheduling behavior is a real-time optimal scheduling scheme, and therefore the problem how to schedule large model tasks more efficiently is solved, and the scheduling efficiency is improved. And the computing power resource of the neural network processor is efficiently utilized to reduce the technical problem of computing power waste.

The invention relates to a message uploading method, a data processing unit and a network processor, and the method comprises the steps: obtaining the number of messages currently cached in the data processing unit in a target queue, so as to determine the number of descriptors to be read, obtaining the descriptors in batches through one PCIe reading operation, and sending the descriptors to the target queue; the messages of the currently cached target queue are written into host side caches pointed by the descriptors, and every time one message is successfully uploaded, one is subtracted from the message count of the currently cached target queue; and if the currently read descriptor is used up, but the target queue has unprocessed messages, repeating the above steps, determining and reading the required descriptor according to the number of the remaining messages of the currently cached target queue again, continuing to write the messages, and repeating the above steps. And all the messages of the currently cached target queue are successfully carried to the host side for caching. According to the method and the device, the message uploading efficiency and the bandwidth utilization rate are improved by optimizing the descriptor reading mode.

The invention provides an SIMT-based neural network processor and a task execution method thereof, and the method comprises the steps that a general processor queries a state register of a coprocessor, and the state register stores the resource condition of the coprocessor; the universal processor completes splitting from a thread block to a thread bundle according to the resource condition, and the universal processor forwards a thread bundle instruction to a thread bundle distributor of the coprocessor; and the thread beam distributor decodes instructions in the thread beams in sequence and schedules the instructions to instruction queues of different calculation cores, and the thread beams sequentially perform thread beam scheduling, instruction emission and instruction execution according to the sequence, so that all calculations of a neural network task are completed in parallel, and a running result of the neural network task is obtained. According to the method, a general processor for task splitting is introduced in front of the thread beam scheduler or a specific compiler is directly used, so that dynamic scheduling of the threads can be realized, and a scheme for dynamically expanding the number of the threads according to data precision becomes a feasible architecture option.

The invention discloses a tensor processing architecture based on reconfigurable calculation, a working mode of the tensor processing architecture and an FPGA (Field Programmable Gate Array) development board. The overall architecture comprises a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, an RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module and a result return network. The working modes of the overall architecture are divided into two modes: a CPU control mode and a cluster computing mode, wherein the CPU control mode is used for controlling global computing and output through a CPU during single-chip computing; the cluster calculation mode is used for being connected with an upper computer to cooperate with the upper computer to execute calculation tasks such as matrix calculation; the whole architecture is realized through an FPGA (Field Programmable Gate Array) development board, and the FPGA development board adopts Virtex UltraScale + VU13P as a main logic realization platform. Through the dynamic granularity configuration of the on-chip microcode, multiple operation modes can be realized, and the utilization rate of hardware is improved; and hardware realizes multiple configuration strategies, and the universality is high.

The invention discloses an error correction method of a neural network processor and a related device, and belongs to the technical field of neural networks. The method comprises the steps that according to a fault PE table obtained through error detection, the fault PE table comprises a two-dimensional list of fault occurrence and position information, a newly detected fault PE is positioned according to the fault PE table, and a multi-stage fault-tolerant decision is executed: i, a fine-grained error correction stage; ii, a coarse granularity error correction stage; according to the current error correction mode, a pipeline submission mechanism or a submission mechanism is selected, and a calculation result is output. According to the method, a mixed granularity fault recovery scheme is adopted, and the error correction function can be achieved under the condition that any standby PE is not added. The fine-grained scheme provides more flexibility and does not waste PE, and the coarse-grained scheme ensures that the reasoning precision is not reduced along with the increase of the failure rate.

The invention provides a network processor and a related instruction scheduling method, relates to the technical field of chips, and can improve the execution efficiency of instructions. The network processor comprises a scheduler, a plurality of scheduling control modules and a plurality of cache queues. The plurality of scheduling control modules are used for obtaining a first number of instructions from each cache queue in the plurality of non-empty cache queues, generating a scheduling request based on first indication information of the first number of instructions in each non-empty cache queue so as to obtain a plurality of scheduling requests, and sending the plurality of scheduling requests to the scheduler, the scheduler is used for responding to a plurality of scheduling requests and sending at least one scheduling response signal to the at least one scheduling control module, and the at least one scheduling control module is further used for responding to the at least one scheduling response signal and generating to-be-executed instruction words based on a first number of instructions in a target cache queue and a target scheduling mode.

A method for monitoring a data network in a motor vehicle is provided, wherein a switch device is operated in the data network, in which physical ports for receiving and for transmitting data packets are interconnected via a switch circuit. A network processor reads out detection data in monitoring positions of the data packets and forms pseudo target determination data for an associative memory therefrom, which actually is to process target determination data for a target port determination, and it is examined if certain action data results, which signalizes a necessity of a detection action, by inputting the pseudo target determination data into the associative memory.

The invention relates to a heterogeneous trusted execution environment architecture construction method and device, and the method comprises the following steps: constructing a tensor analyzer which is located in a memory control unit of a central processing unit of a heterogeneous trusted execution environment architecture; and providing memory protection with uniform tensor granularity for data interaction between the neural network processor of the heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer.

The invention discloses an improved method for logging in a weak network by a mobile phone number through one key and electronic equipment, and belongs to the technical field of communication, and the method comprises the following steps: a main processor creates a pre-connection pool, records a pre-connection domain name and a port list, and executes pre-connection; meanwhile, various parameters required by number prefetching are prepared, and a number prefetching request is sent; the network processor creates a retry controller, and the retry controller intelligently determines a corresponding retry mode according to the failure reason and the network state; unnecessary repeated operation is avoided by means of implementing a breakpoint resume type retry mechanism, error type detection and classification processing, network availability judgment and automatic reconstruction, private network IP change detection and URL reconstruction, an exponential backoff algorithm to control a retry interval and the like, and a staged timeout mechanism is introduced, so that the retry efficiency is improved. The personalized reasonable timeout time of different stages is set, the problem that a certain stage consumes too long time is avoided, and the network request success rate of the SDK in the weak network environment is improved.

The invention provides a coagulant addition control system and method based on multi-scale alumen ustum characteristic analysis, and relates to the technical field of coagulant addition control. Comprising an underwater camera device, an embedded prediction module, an integrated neural network processor NPU, a dosing device, a feature extraction module and a time sequence feature coding module. According to the method, underwater camera devices are arranged in a flocculation area and a settlement area respectively, spatial multi-dimensional feature analysis is carried out on images acquired at double view angles, spatial multi-scale parameters are obtained, and real-time prediction of coagulant dosage is realized through an improved deep learning model; the improved deep learning model is embedded into a controller of an integrated neural network processor NPU, after the controller receives a model prediction result, regulation and control signals of PAC and PAM are generated in combination with the current operation state of the dosing pump, and dosing equipment is driven to execute actions; meanwhile, a regulation and control result is fed back to the feature extraction module in real time, and accurate matching of the coagulant dosage and dynamic evolution of alumen ustum is ensured.

This application provides example packet forwarding methods and packet forwarding apparatuses. One example method includes sending, by a network processor, at least one descriptor to a traffic manager, where the at least one descriptor indicates a storage address of at least one packet in a buffer module. First information of a to-be-forwarded packet is sent by the traffic manager to the network processor based on the at least one descriptor. The to-be-forwarded packet is obtained by the network processor based on the first information. The to-be-forwarded packet is sent by the network processor to the traffic manager. The to-be-forwarded packet is received and forwarded by the traffic manager.

The invention relates to the technical field of office automation, in particular to an intelligent control method, device, equipment and system for automatic stamping, and aims to recognize and semantically analyze the recognized file content of a paper material through a multi-modal stamping feature recognition model, realize intelligent determination and calibration of a stamping position, improve the stamping accuracy and improve the stamping efficiency. The stamping method can adapt to different file formats and is flexible without presetting a fixed template, so that the applicability of the stamping method is improved; edge AI computing power is deployed in the stamping equipment, and a neural network processor is locally integrated, so that data processing localization is realized, data security is improved, data response delay in the stamping processing process is reduced, and network dependence is reduced; and based on local powerful computing power support of the stamping equipment, large-batch stamping processing can be achieved, the stamping efficiency is improved, and therefore the working efficiency is improved, and the human resource cost is reduced.

A method for encapsulating transaction instrument information in a transaction includes storing, in association with a first transaction and by a processor of the primary transaction processor server, transaction data associated with a transaction instrument for a first transaction. The primary transaction processor server transmits the transaction data to a payment network processor, and receives an authorization package in response that includes a cryptograph and a first network token. The primary transaction processor server generates a second token that includes a changeable alpha-numeric string associated with the transaction instrument used in the first transaction, and transmits the second token to a merchant device. The second token indicates that a transaction associated with the second token is either i) a customer-initiated transaction or ii) a merchant-initiated transaction. The secondary transaction processor may approve or reject a transaction using the second token without a cryptogram.

The invention provides a code compiling method and device based on a P4 assembler, the assembler and a medium. The code compiling method comprises the steps that a to-be-processed assembly code file is obtained; splitting and compiling the assembly code file to obtain a plurality of code segment compiling results; according to the auxiliary information, by taking Parser components, Mat components and Deparser components contained in the Ingress unit and the Egress unit as classification types, classifying the code segment compiling results to obtain code segment groups; linking the P4 table item data and the machine instruction code contained in the code segment group, and endowing a link result with a global instruction identifier and code segment header information to obtain a code segment binary code; and generating a firmware file based on the code segment binary code. The compiling process of the network processor can be simplified, so that the development efficiency is improved.

The system comprises a plurality of sensor systems, a counter drone, and a processor. A sensor system of the plurality of sensor systems comprises one or more sensors that are connected to a network. The counter drone is connected to the network. The processor is configured to receive an indication of a potential target from the plurality of sensor systems; generate a fused data set for the potential target, determine whether the potential target comprises the threat drone based at least in part on the fused data set; and in response to determining that the potential target comprises the threat drone, provide counter drone instructions to the counter drone.

The invention provides a network processor and a message processing method, and relates to the technical field of computers. The network processor comprises a matching module, an execution module and a cache, wherein the matching module and the execution module share the cache. Wherein the cache is used for storing first program state information. The matching module is used for updating the first program state information according to the to-be-processed message to obtain second program state information, and the second program state information comprises feature information of the to-be-processed message. And the execution module is used for processing the second program state information in the cache. Under the architecture of the network processor, the PS information does not need to be fully written and read back and forth between the two modules, so that the reading and writing times of the full PS information are greatly reduced, the bandwidth resource of the network processor is saved, and the power consumption of the network processor is reduced.

Provided in the present invention are an image perspective conversion display apparatus, an image perspective conversion display method, and a computer-readable storage medium. The image perspective conversion display apparatus comprises: a digital signal processor, which is configured to perform warping processing on a first video image from a camera's perspective and depth data corresponding thereto, so as to obtain a second video image from a user's human eye perspective; a network processor, which is configured to perform target detection on the first video image so as to determine a first image mask indicating an occluded region in the second video image, and which is configured to perform an inpainting operation on the basis of the second video image and the first image mask so as to obtain an inpainted image that fills the value of at least one pixel in the occluded region; and an application-specific integrated circuit, which is configured to perform correction and layer blending on the first video image and the inpainted image so as to obtain a third video image to be displayed.

Described are methods, systems, and media for detecting malicious activity in a network by performing operations comprising: feeding network packets from the network into a header crypto engine; sending the network packets from the header crypto engine to a work scheduler; divaricating the network packets using the work scheduler based on flow data and header data of the network packets to at least one of a firewall and a neural network processor; generating output data comprising: a first output data from the firewall according to rules of the firewall; a second output data from the neural network processor based on behavioral analysis performed by the neural network processor, wherein the second output data is used to update the rules in the firewall; and aggregating the output data from the firewall and the neural network processor to detect malicious activity in the network.

The invention relates to a quantization method, an inverse quantization method and a neural network processor in a large language model. A core (namely a quantization unit) in a neural network processor is arranged to execute quantization processing in a large-scale language model reasoning process, and the quantization unit has a data partitioning function, so that the quantization processing efficiency is greatly improved compared with an existing quantization processing core which is limited by the data size (such as block wise) when receiving data to be quantized. And frequent interaction with a cache is not needed, so that online high-efficiency large-model quantification processing is realized. And performing an inverse quantization process in a large language model inference process by setting a core (i.e., an inverse quantization unit) in a neural network processor, and the inverse quantization unit having a data partitioning function, a matrix multiplication function, and a high precision accumulation function (e.g., multiplying by a corresponding quantization parameter), the inverse quantization processing does not need to frequently carry data in a plurality of cores, and the inverse quantization processing efficiency of a large model is improved.

Disclosed are a data access method and apparatus, a storage medium, and an electronic device. The method includes: determining a first instruction to be executed by the neural network processor; determining, based on requested storage space information corresponding to the first instruction, storage space address information meeting the requested storage space information, the storage space address information comprising first storage space address information of a first storage space and second storage space address information of a second storage space; and executing, based on the storage space address information, the first instruction through the neural network processor.

The embodiment of the invention provides an energy efficiency ratio tuning method of a neural network processor and related equipment, and belongs to the technical field of computer processing, and the method comprises the steps: obtaining a matrix parameter set of the neural network processor, and determining a working energy efficiency ratio function of the neural network processor based on the matrix parameter set; a Bayesian distribution model is constructed based on the working energy efficiency ratio function and the matrix parameter set, and the Bayesian distribution model comprises an acquisition function used for evaluating the quality of the matrix parameter set; performing Bayesian optimization processing on the matrix parameter set by using the acquisition function to obtain a target matrix parameter set; and controlling the neural network processor to enter a running state based on the target matrix parameter set. According to the invention, the energy efficiency ratio of the NPU can be improved, and the energy consumption is reduced.

The density and power consumption of modern integrated circuits, such as Graphic Processing Units (GPUs), Central Processing Units (CPUs), and Network Processing Units (NPUs) is growing rapidly, which necessitates designing advanced cooling systems. Existing solutions for characterizing and validating these cooling system are inadequate. A flexible, scalable Thermal Test Vehicle (TTV) is disclosed which is based on an array of power transistors, measurement / control circuitry, and onboard computer. The TTV is configured for characterizing the performance of electronic cooling solutions under a variety of operating conditions.

Systems and methods for providing executable instructions to a neural network processor are provided. In one example, a system comprises a database that stores a plurality of executable instructions and a plurality of subgraph identifiers, each subgraph identifier of the plurality of subgraph identifiers being associated with a subset of instructions of the plurality of executable instructions. The system further includes a compiler configured to: identify a computational subgraph from a computational graph of a neural network model; compute a subgraph identifier for the computational subgraph, based on whether the subgraph identifier is included in the plurality of subgraph identifiers, either: obtain, from the database, first instructions associated with the subgraph identifier; or generate second instructions representing the computational subgraph; and provide the first instructions or the second instructions for execution by a neural network processor to perform computation operations for the neural network model.

The invention provides a model task scheduler, a computing core, a neural network processor and a method, and the model task scheduler comprises a model task queue unit which is configured to receive model tasks issued by a host and cache the model tasks to corresponding task queues according to task priorities, outputting the model tasks in the task queue to a model task scheduling unit according to task priorities; wherein the model task queue unit comprises a plurality of task queues, and each task queue corresponds to one task priority; and the model task scheduling unit is configured to distribute the model tasks to one or more computing cores corresponding to the task types in the neural network processor according to the task types of the model tasks output by the model task queue unit.

The invention discloses a software and hardware collaborative optimization method for a hybrid in-memory architecture, which comprises the following steps of: performing joint feature representation on a target AI algorithm and an in-memory computing architecture, extracting context features, and parameterizing in-memory computing unit configuration, a neural network processor assembly line, a multi-core interconnection topology and a storage level interface of the in-memory computing architecture; an off-line reference data set is constructed, a predictive agent model is trained, discrete architecture parameters are processed by the model by adopting an embedding method, feature association is learned by applying an encoder with a self-attention mechanism, joint prediction of multi-dimensional PPA indexes is realized through a parallel prediction network, and a feasible region constraint learning mechanism is introduced in training; the trained agent model is embedded into a multi-objective evolutionary algorithm, the energy efficiency ratio, the average computing power utilization rate, the model execution delay and the like serve as optimization objectives, chip area efficiency and power consumption constraints are met at the same time, and a Pareto optimal in-memory computing architecture configuration set is searched.

This disclosure relates to integrated circuit devices that may include a network processor in a data processing die and an on-package memory in a base die. The data processing die may implement one or more network functionalities that may exchange data with low-latency memory, high capacity in the base die. The data processing die may be programmable fabric, which may be dynamically reconfigured during operation.

The invention discloses a tensor data acceleration processing device, a tensor data acceleration processing system and an integrated circuit. The device is used for post-processing tensor data output by a neural network processor and comprises an interface unit, a cache unit, a data processing unit and an output unit. And the interface unit is connected with the neural network processor and is used for transmitting the to-be-processed tensor data output by the neural network processor. The cache unit is connected with the interface unit and is used for storing tensor data to be processed in processing; and the data processing unit is connected with the interface unit and the cache unit and is used for processing the tensor data to be processed. And the output unit is connected with the data processing unit and transmits the processed tensor data to be processed to an external memory. According to the device, the tensor post-processing efficiency is improved, the time delay is reduced, and the bandwidth consumption in the data reading and writing process is saved.

Embodiments of the present disclosure relate to a tensor access operation circuit in a neural processor circuit. The neural processor circuit further includes a data processor circuit and at least one neural engine circuit. The tensor access operation circuit indirectly accesses at least a region of a source tensor in a system memory having a rank, and maps one or more source components of the source tensor into an input tensor having another rank. The data processor circuit stores an output version of the input tensor obtained from the tensor access operation circuit and sends the output version of the input tensor as multiple of units of input data to the at least one neural engine circuit. The at least one neural engine circuit performs at least convolution operations on the units of input data and at least one kernel to generate output data.