603 results about "Network processor" patented technology

The invention provides a complex scene-oriented AI large model lightweight deployment method, and relates to the technical field of edge computing, and the method comprises the steps: carrying out the structured pruning of a pre-trained Transform network based on the attention head importance score, carrying out the dynamic sparsification of the activation state of a feedforward network according to the input tensor entropy value, employing the dynamic mixing precision quantization, and carrying out the reconstruction of an AI large model. Obtaining network parameters after pruning quantization; deploying the pruned and quantized network parameters to an edge computing device, distributing a feature extraction operator to a neural network processor through a heterogeneous computing scheduler, and unloading a classification operator to a multi-core central processing unit; and managing an on-chip memory in combination with a virtual memory paging mechanism, realizing zero-copy data transmission by utilizing a direct memory access controller, and outputting a reasoning result tensor. According to the method, efficient and reliable operation of the large model at the resource-constrained edge node is realized.

The invention provides a power grid dispatching strategy optimization method and system, and the method comprises the steps: deploying a device based on a quantum entanglement technology between transformer substations, and collecting the state information of a power grid, and encrypting and transmitting the state information to a control center through a quantum network; a pulse neural network processor is used in a control center to extract spatial-temporal characteristics, and a quantum game theory model is used to generate an optimized scheduling strategy. Multi-modal verification data is collected, including visual deformation, abnormal sound monitoring, and operational resistance data. A genetic algorithm and deep reinforcement learning are utilized to optimize a decision model, and a dynamic weight distribution mechanism is included. And through a photon-quantum hybrid computing architecture execution model, a scheduling strategy is collaboratively optimized, and a result is fed back to a physical power grid. According to the method, the quantum technology and the spiking neural network are combined, new energy fluctuation is captured in real time, the multi-target weight is dynamically adjusted through the quantum game theory model, and the scheduling strategy robustness is improved. And a photon-quantum hybrid computing architecture is adopted, so that the feature extraction speed and the optimization efficiency are improved.

The invention discloses a task scheduling method and device, equipment, a storage medium and a product, and relates to the technical field of artificial intelligence. According to the method, a large model is divided into a plurality of sub-tasks, the computing power demand is quantified in real time, and the matching score of the schedulable task and each neural network processor node is calculated in combination with the computing power evaluation information of each neural network processor node; the schedulable task with the highest priority in the scheduling queue is allocated to the neural network processor node with the highest matching score, and all subtasks of different large models are reasonably allocated through loop execution; besides, priorities are distributed to the to-be-scheduled sub-tasks in the scheduling queue based on the scheduling strategy, scheduling is carried out through a greedy algorithm, it can be guaranteed that each scheduling behavior is a real-time optimal scheduling scheme, and therefore the problem how to schedule large model tasks more efficiently is solved, and the scheduling efficiency is improved. And the computing power resource of the neural network processor is efficiently utilized to reduce the technical problem of computing power waste.

A method may include partitioning a tensor that includes a plurality of data values into a number (K) of subtensors, where each of the K subtensors may include a respective subset of the plurality of data values. The method may also include retrieving one or more first data values of the subset of data values included in a first subtensor of the K subtensors in accordance with an access pattern associated with a neural network processor. The method may include storing the one or more first data values of the subset of data values in one of K segments of cache memory, where each of the K segments may be associated with a respective one of the K subtensors. Further, the method may include processing, using the neural network processor, the one or more first data values of the subset of data values in accordance with the access pattern.

The invention relates to a message uploading method, a data processing unit and a network processor, and the method comprises the steps: obtaining the number of messages currently cached in the data processing unit in a target queue, so as to determine the number of descriptors to be read, obtaining the descriptors in batches through one PCIe reading operation, and sending the descriptors to the target queue; the messages of the currently cached target queue are written into host side caches pointed by the descriptors, and every time one message is successfully uploaded, one is subtracted from the message count of the currently cached target queue; and if the currently read descriptor is used up, but the target queue has unprocessed messages, repeating the above steps, determining and reading the required descriptor according to the number of the remaining messages of the currently cached target queue again, continuing to write the messages, and repeating the above steps. And all the messages of the currently cached target queue are successfully carried to the host side for caching. According to the method and the device, the message uploading efficiency and the bandwidth utilization rate are improved by optimizing the descriptor reading mode.

The invention provides an SIMT-based neural network processor and a task execution method thereof, and the method comprises the steps that a general processor queries a state register of a coprocessor, and the state register stores the resource condition of the coprocessor; the universal processor completes splitting from a thread block to a thread bundle according to the resource condition, and the universal processor forwards a thread bundle instruction to a thread bundle distributor of the coprocessor; and the thread beam distributor decodes instructions in the thread beams in sequence and schedules the instructions to instruction queues of different calculation cores, and the thread beams sequentially perform thread beam scheduling, instruction emission and instruction execution according to the sequence, so that all calculations of a neural network task are completed in parallel, and a running result of the neural network task is obtained. According to the method, a general processor for task splitting is introduced in front of the thread beam scheduler or a specific compiler is directly used, so that dynamic scheduling of the threads can be realized, and a scheme for dynamically expanding the number of the threads according to data precision becomes a feasible architecture option.

The invention discloses a tensor processing architecture based on reconfigurable calculation, a working mode of the tensor processing architecture and an FPGA (Field Programmable Gate Array) development board. The overall architecture comprises a QSFP interface, a DDR storage module, a memory access control module, a microcode control module, a matrix module, an on-chip shared storage module, a control network, an RISC-V processor, a reconfigurable computing interface module, a reconfigurable computing module, a reconfigurable configuration module and a result return network. The working modes of the overall architecture are divided into two modes: a CPU control mode and a cluster computing mode, wherein the CPU control mode is used for controlling global computing and output through a CPU during single-chip computing; the cluster calculation mode is used for being connected with an upper computer to cooperate with the upper computer to execute calculation tasks such as matrix calculation; the whole architecture is realized through an FPGA (Field Programmable Gate Array) development board, and the FPGA development board adopts Virtex UltraScale + VU13P as a main logic realization platform. Through the dynamic granularity configuration of the on-chip microcode, multiple operation modes can be realized, and the utilization rate of hardware is improved; and hardware realizes multiple configuration strategies, and the universality is high.

The embodiment of the invention provides a chip system, an image processing method and electronic equipment, and is applied to the technical field of chip image processing. The chip system comprises an image processor, a neural network processor and a scheduling circuit. Wherein the image processor is used for outputting a first rendered image according to the image subtask. And the scheduling circuit is used for instructing the neural network processor to acquire the first rendered image according to the scheduling sub-task. And the neural network processor is used for performing neural network algorithm processing on the first rendered image according to the operation subtask and outputting an operation result. And the scheduling circuit is also used for indicating the image processor to obtain an operation result according to the scheduling sub-task. And the image processor is also used for carrying out image processing on the operation result according to the image subtask to obtain a second rendered image. According to the embodiment of the invention, image processing is carried out based on multi-IP linkage so as to improve the imaging quality, the power consumption and the processing complexity of a chip system are reduced, and the method can be suitable for different chip architectures.

The invention discloses an error correction method of a neural network processor and a related device, and belongs to the technical field of neural networks. The method comprises the steps that according to a fault PE table obtained through error detection, the fault PE table comprises a two-dimensional list of fault occurrence and position information, a newly detected fault PE is positioned according to the fault PE table, and a multi-stage fault-tolerant decision is executed: i, a fine-grained error correction stage; ii, a coarse granularity error correction stage; according to the current error correction mode, a pipeline submission mechanism or a submission mechanism is selected, and a calculation result is output. According to the method, a mixed granularity fault recovery scheme is adopted, and the error correction function can be achieved under the condition that any standby PE is not added. The fine-grained scheme provides more flexibility and does not waste PE, and the coarse-grained scheme ensures that the reasoning precision is not reduced along with the increase of the failure rate.

The invention provides a network processor and a related instruction scheduling method, relates to the technical field of chips, and can improve the execution efficiency of instructions. The network processor comprises a scheduler, a plurality of scheduling control modules and a plurality of cache queues. The plurality of scheduling control modules are used for obtaining a first number of instructions from each cache queue in the plurality of non-empty cache queues, generating a scheduling request based on first indication information of the first number of instructions in each non-empty cache queue so as to obtain a plurality of scheduling requests, and sending the plurality of scheduling requests to the scheduler, the scheduler is used for responding to a plurality of scheduling requests and sending at least one scheduling response signal to the at least one scheduling control module, and the at least one scheduling control module is further used for responding to the at least one scheduling response signal and generating to-be-executed instruction words based on a first number of instructions in a target cache queue and a target scheduling mode.

A method for monitoring a data network in a motor vehicle is provided, wherein a switch device is operated in the data network, in which physical ports for receiving and for transmitting data packets are interconnected via a switch circuit. A network processor reads out detection data in monitoring positions of the data packets and forms pseudo target determination data for an associative memory therefrom, which actually is to process target determination data for a target port determination, and it is examined if certain action data results, which signalizes a necessity of a detection action, by inputting the pseudo target determination data into the associative memory.

The invention relates to a heterogeneous trusted execution environment architecture construction method and device, and the method comprises the following steps: constructing a tensor analyzer which is located in a memory control unit of a central processing unit of a heterogeneous trusted execution environment architecture; and providing memory protection with uniform tensor granularity for data interaction between the neural network processor of the heterogeneous trusted execution environment architecture and the central processing unit through the tensor analyzer.

Accelerated convolution of neural networks can be performed by executing N computing engines (CEs) of a neural network processor in parallel. An input dataset can be divided spatially into N chunks such that a respective last portion of each chunk overlaps with a respective first portion of a subsequent chunk. Portions of each chunk can be processed by a respective CE to generate a respective portion of an output dataset. The overlapping intermediate states computed by each CE from processing the overlapping portion can be stored locally for sharing with a subsequent CE using an on-chip bus.

The embodiment of the invention provides an instruction processing device, an instruction processing method and a chip system. The instruction processing device comprises a data control module configured to receive and process a loop initial instruction to obtain a loop descriptor; the loop processing module is configured to construct a loop according to the loop descriptor and generate loop level information and control information for realizing loop control; and the instruction control module is configured to generate an executable instruction of the neural network processor according to the loop level information and the control information, the executable instruction is provided for the neural network processor to execute, and the instruction control module corresponds to the loop processing module. According to the instruction processing device, efficient, high-robustness and high-expansibility instruction control and generation can be carried out, the instruction sending efficiency is improved, the load of the coprocessor can be relieved, the performance of the coprocessor can be released for other functions, and the maximum utilization of system resources is achieved.

The invention discloses a deep learning noise suppression reconstruction method applied to a quantum image sensor, and relates to the field of image processing, and the method comprises the steps: firstly, carrying out the calculation of a block and an image of a three-dimensional frame plane sequence, and facilitating the improvement of the suppression capability of Poisson noise through precise unbiased variance stabilization transformation; secondly, the method is based on a network framework fusing Transform and CNN, the framework serves as a core denoising device and can deeply search key information in image denoising in a linear and nonlinear component combination mode, and the adaptability of the network to the denoising capacity of various scenes is enhanced through the sub-network parallel technology; and finally, using accurate unbiased variance to stabilize inverse transformation, using maximum likelihood estimation to restore a real photon number, and starting from a QIS imaging principle, further suppressing noise in a reconstructed image. According to the method provided by the invention, the reconstructed image noise of the QIS can be remarkably suppressed, and the method has the potential of being applied to a customized neural network processor chip, so that the method can obtain a relatively high operation speed.

The invention discloses an improved method for logging in a weak network by a mobile phone number through one key and electronic equipment, and belongs to the technical field of communication, and the method comprises the following steps: a main processor creates a pre-connection pool, records a pre-connection domain name and a port list, and executes pre-connection; meanwhile, various parameters required by number prefetching are prepared, and a number prefetching request is sent; the network processor creates a retry controller, and the retry controller intelligently determines a corresponding retry mode according to the failure reason and the network state; unnecessary repeated operation is avoided by means of implementing a breakpoint resume type retry mechanism, error type detection and classification processing, network availability judgment and automatic reconstruction, private network IP change detection and URL reconstruction, an exponential backoff algorithm to control a retry interval and the like, and a staged timeout mechanism is introduced, so that the retry efficiency is improved. The personalized reasonable timeout time of different stages is set, the problem that a certain stage consumes too long time is avoided, and the network request success rate of the SDK in the weak network environment is improved.

The invention provides a coagulant addition control system and method based on multi-scale alumen ustum characteristic analysis, and relates to the technical field of coagulant addition control. Comprising an underwater camera device, an embedded prediction module, an integrated neural network processor NPU, a dosing device, a feature extraction module and a time sequence feature coding module. According to the method, underwater camera devices are arranged in a flocculation area and a settlement area respectively, spatial multi-dimensional feature analysis is carried out on images acquired at double view angles, spatial multi-scale parameters are obtained, and real-time prediction of coagulant dosage is realized through an improved deep learning model; the improved deep learning model is embedded into a controller of an integrated neural network processor NPU, after the controller receives a model prediction result, regulation and control signals of PAC and PAM are generated in combination with the current operation state of the dosing pump, and dosing equipment is driven to execute actions; meanwhile, a regulation and control result is fed back to the feature extraction module in real time, and accurate matching of the coagulant dosage and dynamic evolution of alumen ustum is ensured.

This application provides example packet forwarding methods and packet forwarding apparatuses. One example method includes sending, by a network processor, at least one descriptor to a traffic manager, where the at least one descriptor indicates a storage address of at least one packet in a buffer module. First information of a to-be-forwarded packet is sent by the traffic manager to the network processor based on the at least one descriptor. The to-be-forwarded packet is obtained by the network processor based on the first information. The to-be-forwarded packet is sent by the network processor to the traffic manager. The to-be-forwarded packet is received and forwarded by the traffic manager.

The invention relates to the technical field of office automation, in particular to an intelligent control method, device, equipment and system for automatic stamping, and aims to recognize and semantically analyze the recognized file content of a paper material through a multi-modal stamping feature recognition model, realize intelligent determination and calibration of a stamping position, improve the stamping accuracy and improve the stamping efficiency. The stamping method can adapt to different file formats and is flexible without presetting a fixed template, so that the applicability of the stamping method is improved; edge AI computing power is deployed in the stamping equipment, and a neural network processor is locally integrated, so that data processing localization is realized, data security is improved, data response delay in the stamping processing process is reduced, and network dependence is reduced; and based on local powerful computing power support of the stamping equipment, large-batch stamping processing can be achieved, the stamping efficiency is improved, and therefore the working efficiency is improved, and the human resource cost is reduced.

A method for encapsulating transaction instrument information in a transaction includes storing, in association with a first transaction and by a processor of the primary transaction processor server, transaction data associated with a transaction instrument for a first transaction. The primary transaction processor server transmits the transaction data to a payment network processor, and receives an authorization package in response that includes a cryptograph and a first network token. The primary transaction processor server generates a second token that includes a changeable alpha-numeric string associated with the transaction instrument used in the first transaction, and transmits the second token to a merchant device. The second token indicates that a transaction associated with the second token is either i) a customer-initiated transaction or ii) a merchant-initiated transaction. The secondary transaction processor may approve or reject a transaction using the second token without a cryptogram.

The invention provides a code compiling method and device based on a P4 assembler, the assembler and a medium. The code compiling method comprises the steps that a to-be-processed assembly code file is obtained; splitting and compiling the assembly code file to obtain a plurality of code segment compiling results; according to the auxiliary information, by taking Parser components, Mat components and Deparser components contained in the Ingress unit and the Egress unit as classification types, classifying the code segment compiling results to obtain code segment groups; linking the P4 table item data and the machine instruction code contained in the code segment group, and endowing a link result with a global instruction identifier and code segment header information to obtain a code segment binary code; and generating a firmware file based on the code segment binary code. The compiling process of the network processor can be simplified, so that the development efficiency is improved.

The system comprises a plurality of sensor systems, a counter drone, and a processor. A sensor system of the plurality of sensor systems comprises one or more sensors that are connected to a network. The counter drone is connected to the network. The processor is configured to receive an indication of a potential target from the plurality of sensor systems; generate a fused data set for the potential target, determine whether the potential target comprises the threat drone based at least in part on the fused data set; and in response to determining that the potential target comprises the threat drone, provide counter drone instructions to the counter drone.

The invention provides a network processor and a message processing method, and relates to the technical field of computers. The network processor comprises a matching module, an execution module and a cache, wherein the matching module and the execution module share the cache. Wherein the cache is used for storing first program state information. The matching module is used for updating the first program state information according to the to-be-processed message to obtain second program state information, and the second program state information comprises feature information of the to-be-processed message. And the execution module is used for processing the second program state information in the cache. Under the architecture of the network processor, the PS information does not need to be fully written and read back and forth between the two modules, so that the reading and writing times of the full PS information are greatly reduced, the bandwidth resource of the network processor is saved, and the power consumption of the network processor is reduced.

The present invention discloses a request processing method and device based on a neural network model, which relates to the field of computer technology and can solve the problem in the prior art that hardware resources cannot change rapidly and dynamically with changes in traffic and have poor flexibility. The method of the present invention mainly includes: determining whether at least one target neural network model is stored in the video memory of a network processor, the target neural network model including a neural network model corresponding to a queue of pending requests; if the target neural network model is not stored in the video memory, pre-fetching the target neural network model from the internal memory and loading it into the video memory to cover at least one neural network model pre-stored in the video memory; processing the requests in the queue of pending requests based on the target neural network model stored in the video memory. The present invention is mainly applicable to scenarios in which different requests are processed based on multiple neural network models.

The invention discloses a power system automation equipment network card hardware architecture and a message processing method and system, and the system comprises a network interface subsystem, a hardware encryption / decryption subsystem, a programmable network processor subsystem, a management control subsystem, a message information memory, a message processing strategy table, an equipment interface subsystem, an internal bus and a power supply circuit. And the subsystems are interconnected through a data bus and a control bus for data interaction. The network card equipment based on programmable network processing can adapt to various industrial communication networks, analyze and process received messages, realize network traffic flow sensing and security defense capabilities, realize deep sensing and preprocessing of network messages through hardware network processing acceleration under the condition of not influencing the communication performance of the equipment, and improve the communication efficiency of the equipment. Flexible message distribution is achieved, flexible expandability is achieved, and new technologies and equipment are easy to integrate; hardware encryption and security protection measures meet the urgent demand of security protection enhancement of the novel power system.

A system and method for performing tensor transforms on customized digital hardware. The system is comprised of a plurality of computational blocks, a control unit, and memory. The control unit is configured to read the generated source tensor slices for the generated indexes and read from memory the source tensor data and weight data interpolate the tensor slices based on the weights according to a transformation guide. The source tensor data and tensor weights are sent to multiple computational blocks for parallel generation of interpolated output tensor data. The data in memory can be configured so that only one address is needed to read multiple tensor dimensions or a tensor slice. Additionally, the memory can be configured to accept multiple memory addresses in parallel. The computational block output provides a grid-sampled output tensor.

The invention provides a data processing method and device based on a deep learning model and a medium, and relates to the technical field of artificial intelligence, in particular to the calculation fields of deep learning, large models and the like. According to the specific implementation scheme, the deep learning model comprises an expert network layer, and the expert network layer comprises a plurality of expert networks; the processor segments an input feature representing a lexical element into a plurality of sub-features corresponding to a plurality of expert networks; the processor determines at least one target sub-feature from the plurality of sub-features according to the evaluation values of the plurality of sub-features; wherein the evaluation values represent the importance of the sub-features relative to the input features; and according to the at least one target sub-feature and network parameters of at least one target expert network corresponding to the at least one target sub-feature in the plurality of expert networks, the processor executes a model training task or a model reasoning task to obtain a processing result.

A neural network processing unit (NPU) includes a processing element array, a SRAM memory configured to store at least one data of the artificial neural network model processed in the processing element array; and an NPU scheduler configured to control the processing element array and the SRAM memory based on predefined operation order information of the artificial neural network model processed by the processing element array and the NPU scheduler is configured to reuse a memory address value in which an operation value of a first layer of a first scheduling is stored as a memory address value corresponding to an input data of a second layer of a second scheduling, which is a next scheduling of the first scheduling.

Provided in the present invention are an image perspective conversion display apparatus, an image perspective conversion display method, and a computer-readable storage medium. The image perspective conversion display apparatus comprises: a digital signal processor, which is configured to perform warping processing on a first video image from a camera's perspective and depth data corresponding thereto, so as to obtain a second video image from a user's human eye perspective; a network processor, which is configured to perform target detection on the first video image so as to determine a first image mask indicating an occluded region in the second video image, and which is configured to perform an inpainting operation on the basis of the second video image and the first image mask so as to obtain an inpainted image that fills the value of at least one pixel in the occluded region; and an application-specific integrated circuit, which is configured to perform correction and layer blending on the first video image and the inpainted image so as to obtain a third video image to be displayed.

The present disclosure includes a smart pet bowl to monitor pet feeding behavior, which includes a pet bowl to carry pet food or water or carry a bowl insert to carry pet food or water. The smart pet bowl also can include a load sensor associated with the pet bowl that is sensitive to load changes of pet food or water carried within the pet bowl. The load sensor has a sensitivity of + / −50 grams or less and load data collectable therefrom is at a sample rate from 10 to 150 samples per second in sequential time increments from about 0.01 second to 5 seconds. The smart pet bowl may also include a data communicator to communicate the load data over a computer network, a processor, and a memory storing instructions that, when executed by the processor, communicates the load data over the computer network.