465 results about "Hardware architecture" patented technology

The invention discloses a large language model accelerator architecture based on a three-dimensional NAND flash memory, and belongs to the technical field of calculation, reckoning or counting. The architecture comprises a three-dimensional NAND flash memory used for executing feedforward neural network calculation; the auxiliary calculation unit is used for executing attention mechanism calculation; the DRAM chip is used for storing attention mechanism related weights and KV cache; and the interconnection resource is used for realizing data interaction among the components. Wherein the three-dimensional NAND flash memory comprises a logic chip and an NAND array chip, the logic chip is used for controlling and executing calculation, and the NAND array chip is used for storing weights and participating in calculation. The invention further provides a scheduling method based on KV cache awareness. The scheduling method comprises decomposition and dynamic allocation of calculation tasks. Through collaborative design of the hardware architecture and the scheduling method, the memory wall bottleneck in large language model calculation can be relieved, the energy consumption is reduced, and the overall calculation performance is improved.

The invention discloses a multi-modal space-time fusion and distributed cluster fire extinguishing robot cooperative control system, aims to solve the problems of low efficiency and poor precision of multi-machine cooperative fire extinguishing in wide-area fire investigation and flammable and explosive scenes, and provides a whole set of unmanned fire extinguishing technical solution for the multi-mode space-time fusion and distributed cluster fire extinguishing robot cooperative control system. The system comprises four core hardware architectures, namely a cloud dispatching center (A), an unmanned aerial vehicle cluster (B), an unmanned resource guarantee vehicle (C) and a crawler-type fire extinguishing robot cluster (D), and has the following core functions: 1, the cloud dispatching center (A) updates a fire scene model through distributed dispatching by fusing multi-modal sensor data, dynamically allocates tasks and plans a safe approach path; 2, the unmanned aerial vehicle cluster (B) executes the instruction, completes fire global positioning and cluster cooperative sensing, generates a high-precision fire topographic map and feeds back a signal; thirdly, the unmanned resource support vehicle (C) autonomously says for help, and has the functions of automatic mechanical arm water feeding and power supply, environment detection, on-site cleaning after fire extinguishing and communication relay; and fourthly, the crawler-type fire extinguishing robot cluster (D) autonomously navigates and positions the root of a fire source, detects and predicts the drop point of a water column, carries out fire extinguishing feedback evaluation, and interacts with the dispatching center cooperatively to dynamically adjust the strategy, so that closed-loop control is formed, and the fire extinguishing efficiency and accuracy are remarkably improved.

The invention discloses a network construction type inverter for a photovoltaic energy storage system and a virtual synchronous machine control method. The network construction type inverter comprises an inverter power module and a central controller. The central controller is used for collecting power grid operation data in real time and generating a power grid impedance state vector through online impedance identification; and dynamically adjusting virtual inertia and damping parameters of the inverter power module according to the impedance state vector by using an adaptive mapping function so as to realize cooperative control and circulating current suppression between the modules. Performing stability boundary evaluation based on the adjusted parameters, then performing intelligent early warning of the photovoltaic energy storage system, and smoothly switching the operation mode of the inverter power module; according to the invention, through deep integration of a modular hardware architecture and intelligent adaptive control, the inverter has strong autonomous network construction capability, the problems of weak power grid adaptability and transient stability are effectively solved, and the dynamic response and reliability of a photovoltaic energy storage system are improved.

The invention discloses a GPU Box hardware decoupling system based on a Retimer card and a PCIe Switch chip, and belongs to the technical field of computer hardware architecture and high-speed interconnection. According to the system, a Retimer card and a PCIe Switch chip are integrated in an independent GPU Box, and a decoupling link of a CPU server and a GPU acceleration card is constructed; the Retimer card realizes 30-meter long-distance PCIe signal transmission and breaks through physical distance limitation; the PCIe Switch chip pools GPU resources through a dynamic routing and MRIOV technology, supports flexible allocation of computing power by multiple servers, and realizes Peer-to-Peer direct connection communication between GPUs. Aiming at a large model reasoning scene, the system optimizes KV cache bandwidth allocation and video memory and memory cooperative scheduling, so that the 100B parameter model reasoning throughput is greatly improved; and meanwhile, the usability of the system is greatly improved through fault isolation and hot plug design. According to the method, the problems of physical binding of the CPU and the GPU, limited transmission distance, rigid resource allocation and the like in a traditional architecture are solved, and the method is suitable for large-scale AI calculation and distributed GPU cluster deployment.

The invention provides an MCU function security implementation system based on a domain controller, and relates to the technical field of domain controllers, the system realizes dual backup storage and on-site execution of program codes by combining a security MCU without a built-in program memory with at least two redundant plug-in nonvolatile storage units, and the security of the MCU is improved. Consistency verification is carried out on key codes or data in the running process, and system failure caused by single-point storage faults or data tampering is effectively prevented; meanwhile, read-write operation without losing data during power failure is isolated through the independent data storage unit, and resource conflict and interference between program execution and data storage are avoided; the ASIL D-level power management unit supporting two-way fault monitoring is matched, resetting can be triggered in time or the MCU enters a safe state when a power supply is abnormal or an MCU internal fault occurs, and therefore a high-reliability and high-safety domain controller MCU system is constructed on the hardware architecture level, and the capacity of the MCU for meeting the ASIL D function safety level in a plug-in storage scene is improved.

The invention provides a closed-loop nerve regulation and control system and method based on electroencephalogram detection. The defects that a traditional open-loop method lags in stimulation, equipment is heavy and the like are overcome. The system integrates an electroencephalogram acquisition module, an electroencephalogram analysis module, a remote program control module and a stimulation output module to form a closed-loop link. Through 32-channel 1kHz signal acquisition and 1-100Hz filtering pretreatment, pathological features are extracted in real time by using a deep convolutional neural network, stimulation parameters are modified through a remote program control module, and multi-channel collaborative stimulation and safe electrical stimulation are realized in combination with a time division multiplexing architecture and bipolar optocoupler isolation output. The method has the advantages that the pathological feature recognition accuracy of the deep convolutional neural network is greater than or equal to 95%, and the dynamic response delay is less than 50ms; a time division multiplexing hardware architecture is designed, multi-channel collaborative stimulation is achieved through a single DAC, and the size is reduced by 30%; + / -5V bipolar output is realized by using an optocoupler isolated H bridge driver, and the IEC 60601 medical safety standard is met; wireless regulation and control of stimulation parameters are supported, the long-term implantation requirement is met, and the risk of a secondary operation is reduced.

The invention discloses a coal loading and unloading equipment operation detection system based on visual identification, and relates to the technical field of visual identification. The system comprises a hardware architecture and a software architecture, the hardware architecture comprises an image acquisition unit, a data processing unit and a control feedback unit; the software architecture comprises an image processing layer, an intelligent analysis layer and a decision application layer; the image processing layer comprises an image acquisition subsystem, a preprocessing algorithm library and a feature extraction module; the intelligent analysis layer comprises a target detection and identification module, a three-dimensional reconstruction module and an abnormal behavior identification module; and the decision application layer comprises a rule engine, an alarm management subsystem and a data visualization platform. By deploying sensor equipment such as a multi-angle industrial camera and a laser radar and combining a deep learning algorithm and a computer vision technology, various illegal operations and abnormal conditions in the loading and unloading process are automatically identified, total-factor digital monitoring of the loading and unloading process is realized, the detection efficiency is improved, and the loading and unloading risk is reduced.

The invention discloses an interface conversion device and circuit, electronic equipment and an interface conversion method, and relates to the technical field of computer system structures. Extracting a cache or memory transaction request from the first preset interface signal through a channel processing module, generating consistency transaction information, sending the consistency transaction information to a consistency transaction concurrent processing module, receiving response data of the consistency transaction concurrent processing module, and packaging the response data into a second preset interface signal; the consistency transaction concurrent processing module carries out processing according to the received consistency transaction information to obtain a concurrent signal; and the interface conversion module decodes and converts the concurrent signal into a first target protocol control signal, and / or converts the authorized transaction into a second target protocol control signal. Therefore, concurrent analysis, consistency transaction mapping and direct conversion are carried out on a multi-channel protocol through a configurable modular hardware architecture, and high-concurrency and low-delay protocol conversion and cache consistency maintenance between an inter-chip consistency interconnection protocol and an on-chip bus protocol are realized.

The invention provides a cloud edge collaboration algorithm arrangement and deployment method, system and device and a storage medium, and relates to the technical field of cloud edge collaboration.The method comprises the steps that algorithm task requirements input by a user are analyzed, and after corresponding task information is obtained, an intermediate representation file is generated; collecting computing power state information of the plurality of edge devices to determine a target edge device used for executing an algorithm link, and generating an operation parameter configuration file according to a hardware architecture of the target edge device and algorithm characteristics of the intermediate representation file; and issuing the intermediate representation file and the operation parameter configuration file to the target edge device, and performing automatic compiling and deployment according to the chip type of the target edge device. By issuing the intermediate representation file and the operation parameter configuration file to the target edge device and automatically executing compiling and deployment, the effects of cross-platform automatic adaptation, rapid deployment and efficient operation are achieved, and the problem that in the prior art, task organization and deployment flexibility is insufficient is solved.

The invention provides an FPGA (Field Programmable Gate Array) multi-modal control method based on dynamic partial reconfiguration, which comprises the following steps that: a main body adopts a layered hardware architecture to realize multi-modal control, firstly, a system module of a whole system is divided, so that FPGA logic resources are divided into a static region and a reconfigurable region; wherein the static area is responsible for global control and a communication interface part, the reconfigurable area realizes a multi-mode function by loading different configurations, and the middle layer is used for deploying the dynamic part to reconfigure a controller and is responsible for time sequence coordination and bit stream management. Compared with the prior art, the method has the advantages that the mapping relation between the modal feature library and the hardware module is established, the priority preemptive reconfiguration strategy and the modal switching cost model are adopted, the real-time matching of the sensor data flow and the hardware architecture is achieved, the dynamic data path reconstruction technology supports multi-modal parallel processing, and the real-time matching of the sensor data flow and the hardware architecture is achieved. Meanwhile, time sequence constraint, resource occupancy rate and power consumption budget are considered.

The invention discloses a dynamic self-adaptive precision switching method for a voice recognition NPU, and aims to solve the core problems that precision and energy efficiency of an end-side voice recognition NPU in multiple scenes cannot be considered at the same time, fixed-precision hardware resources are seriously wasted, software switching efficiency is low, and errors are accumulated. A hardware architecture of a 4 * 4 reconfigurable MAC subunit array and a switch matrix is constructed, and a task-driven adaptive scheduling mechanism, an operation period synchronous control technology (single-period hardware reconfiguration is realized by utilizing idle gap latch configuration) and a direction-sensitive error compensation algorithm (historical data interpolation extension or correction truncation) are combined; hardware-level dynamic lossless switching of the MAC unit between 8bit / 16bit / 32bit precision is realized, so that different voice tasks achieve the highest necessary computing power with the lowest necessary power consumption, no data is lost in the switching process, and finally, the energy efficiency rigidity of a fixed-precision framework is oppositely converted into the precision on-demand supply capability capable of being deployed in an engineering manner.

The invention belongs to the technical field of fault-tolerant control of an electronic system, and particularly relates to a dual-microcontroller system and a control method thereof, and the dual-microcontroller system comprises a hardware architecture and a software architecture; the hardware architecture specifically comprises a main MCU module, a standby MCU module, a dual-power module, a dual-measurement acquisition module, a hardware arbiter and an output switching value module; the software architecture comprises the steps of initializing a data synchronization communication interface of the main MCU module and the standby MCU module, starting the main MCU module and the standby MCU module, reading data of the measurement acquisition module in a working program state machine by the main MCU module, interacting with external equipment through the communication interface and driving switching value output; and when the main MCU module has no fault, the hardware arbiter selects the switching value output of the main MCU module to drive the external equipment, and when the main MCU module has a fault, the hardware arbiter selects the switching value output of the standby MCU to drive the external equipment.

The invention relates to the technical field of project supervision informatization, and provides a supervision multi-heterogeneous system cloud edge collaborative adaptation method, which comprises the following steps: collecting heterogeneous information such as edge equipment hardware architecture and an operating system to generate records; integrating supervision monitoring data and cloud instructions, classifying the data according to functions and updating frequencies, and marking high-frequency units; unifying a data format and adding Hash verification information; the cloud constructs a three-dimensional mapping table, and edge nodes are grouped in combination with high-frequency data; converting the private protocol of the edge device into a general protocol; by taking minimization of transmission quantity and energy consumption as a target, distributing tasks by using an integer linear programming model; dynamically adjusting the equipment energy consumption; and dynamically optimizing the configuration based on the interface indexes. The cloud edge interaction efficiency can be improved, the energy consumption is reduced, and the reliable operation of supervision business is ensured.

The invention provides a software and hardware integrated intelligent terminal power transaction system and method, relates to the technical field of power market transaction, and solves the technical problems of data potential safety hazards and insufficient real-time performance caused by dependence on an external platform in a power transaction process in the prior art. The system specifically comprises a hardware architecture and a software function module, the hardware architecture comprises a processor, a redundant power supply, a storage device, a network interface, a security encryption chip and a display interface; the software function module comprises a core function layer, an interface layer and a security layer; wherein the core function layer is used for being responsible for processing and controlling the whole flow of power transaction; the interface layer is used for carrying out standardized and ordered external data interaction; and the security layer is used for guaranteeing the security of the terminal from multiple dimensions of communication, transaction, data and operation and maintenance. The method is used for electricity market transaction.

The invention discloses a construction method for dynamically reconstructing a multi-modal edge computing hardware architecture and a cross-industry application method, and relates to the field of edge computing hardware architectures. A five-level heterogeneous architecture is adopted to construct a field self-adaptive dynamic reconstruction calculation unit, and an equipment abstraction layer is constructed to realize module hot plugging and calculation power distribution; a multi-protocol ubiquitous interconnection interface engine is established, a hardware-level analysis architecture is integrated, and multi-protocol analysis and rapid switching are supported; an environment self-adaptive energy efficiency regulation and control system is deployed, and wide-temperature operation is realized by adopting a bionic composite heat dissipation design; an edge-region-cloud three-layer elastic scheduling network is constructed, cross-domain computing power arrangement is realized through federal learning, and the method is adaptive to multi-industry scenes. According to the method, the hardware reuse rate and the wide-temperature environment adaptability are improved, the multi-protocol processing delay is reduced, the computing power scheduling efficiency is optimized, the limitation of traditional equipment is broken through, and the efficient and stable operation requirements of cross-industry scenes such as electric power and medical treatment are met.

The invention discloses a self-adaptive heterogeneous server system based on AI prediction and dynamic hardware reconstruction and a resource management method of the self-adaptive heterogeneous server system, relates to the technical field of server hardware architecture and resource management, and discloses the self-adaptive heterogeneous server system based on AI prediction and dynamic hardware reconstruction and the resource management method of the self-adaptive heterogeneous server system. Through the dynamic adjustment capability of the modular heterogeneous hardware unit pool and the reconfigurable interconnection Fabric and in combination with the accurate prediction of the AI prediction engine on the resource demand and power consumption, the real-time optimal configuration and heat dissipation management of the hardware resources are realized, the resource utilization rate of the server can be improved, the energy consumption can be reduced, and the diversified workload demand of the server can be adapted.

The invention discloses a modeling analysis and calculation optimization method for operator performance on an intelligent chip. The modeling analysis and calculation optimization method comprises the following steps: carrying out graph representation modeling on an intelligent chip hardware architecture and an interconnection mode; designing a link mechanism of operator loop tree nodes, so that operator loops are described and mapped in a hardware architecture model represented by a graph; and performing delay performance analysis on the single operators and the fusion operators in various combination forms by using a pipeline analysis method to obtain the performance of the operators under a hardware architecture, and further performing calculation optimization acceleration. By the adoption of the technical scheme, sufficient guidance can be provided for the initial stage of optimization of the hardware architecture, guidance is provided for optimization space exploration of operators, and therefore the calculation performance of intelligent chip hardware is improved.

The invention relates to the technical field of airborne signal detection, and discloses an airborne signal anomaly detection and predictive maintenance system based on an AI model, which comprises a hardware part and a software part, the hardware part comprises a signal acquisition module, a data storage module, a data transmission module, an edge calculation module and a display alarm module; the software part comprises a data preprocessing module, an AI model construction module, an anomaly detection module, a fault prediction module and a maintenance decision module. According to the invention, through an integrated hardware architecture and an intelligent software algorithm, real-time acquisition of airborne signals, accurate anomaly detection, fault prediction in advance and intelligent making of a maintenance plan are realized, and the operation reliability and maintenance efficiency of airborne equipment are improved.

The invention relates to the technical field of integrated circuit testing, and discloses a method and equipment for scanning a voltage and current flip point of a chip, and the method comprises the following steps: an upper computer completes parameter configuration and wave table loading and then sends a starting instruction, a global synchronization unit generates a synchronization signal, and the synchronization signal is sent to a chip; the random waveform generator is started in parallel for scanning, the trigger unit is started for monitoring, the internal counter is started for timing, when the trigger unit monitors overturning, a stop signal is sent, the global synchronization unit latches a count value immediately, and finally, the upper computer reads the count value and calculates an overturning point value in combination with a wave table rate and a clock period. According to the invention, the global synchronization unit is used for coordinating the parallel hardware architecture of the arbitrary waveform generator and the trigger unit, so that the continuous scanning of the excitation signal and the real-time monitoring of the response signal can be autonomously operated on the hardware level, and the overall time consumption of a single flip point test is greatly shortened.

The invention provides an intelligent data management method and system, and relates to the technical field of data processing. Standardized packaging and automatic execution of the data governance instruction are achieved, and the problem that a traditional storage medium cannot dynamically adapt to the multi-source data processing requirement is solved. Through the decoupling design of the pre-compilation instruction and the runtime environment, the same storage medium can adapt to data management nodes of different hardware architectures, and the deployment complexity during system upgrading is effectively reduced. Furthermore, based on an instruction execution mechanism of a streaming computing engine, the real-time performance of data quality evaluation and early warning triggering is ensured, and decision lag caused by batch processing delay is avoided. Through the on-demand loading characteristic of the modular instruction set, the function expansion requirement of a specific business scene is supported while the core governance function is ensured.

The invention provides a storage and calculation integrated structure and a chip, and belongs to the technical field of integrated circuits, and the storage and calculation integrated structure comprises at least one near storage core grain which is used for providing large-capacity storage; the in-memory computing unit is used for providing computing processing, and the near-memory core grains provide cache space for data and / or instructions processed by the in-memory computing unit; the at least one logic processing core particle is used for loading the data and / or instructions stored in the near memory core particle into the in-memory computing unit, and updating and storing the data and / or instructions processed by the in-memory computing unit into the near memory core particle; and the logic processing core particle is integrated with the near memory core particle and the in-memory computing unit through hybrid bonding and / or TSV (Through Silicon Via). The storage and calculation integrated structure is applied to high-performance calculation, the high-performance calculation requirement and the large-capacity storage requirement can be met at the same time, the high-performance calculation of the system is maximized, and support is provided for the development of the calculation power technology from the hardware structure.

The invention relates to the technical field of new energy power generation control, and discloses a frequency modulation control and online monitoring system, which comprises an AGC (Automatic Gain Control) system for realizing automatic gain control to stabilize the signal transmission quality of the system, and an FPGA (Field Programmable Gate Array) functional module for high-speed data acquisition and logical operation processing, and the CPU processing module is used for overall planning of data analysis, instruction generation and system cooperative control. According to the invention, the FPGA + CPU hardware architecture is adopted, so that the precision requirement of power grid frequency sampling can be ensured, and the precision of the calculated grid-connected point power information can be ensured, thereby obtaining the high-precision power adjusting quantity, adjusting the new energy station according to the power adjusting quantity, and carrying out real-time adjustment control on the new energy station. The requirement for primary frequency modulation of the new energy station is met, and the operation stability of the new energy station is effectively improved.

The invention relates to the technical field of artificial intelligence, can be applied to business scenes of financial science and technology, medical health and the like, and discloses a systolic array scheduling processing method, device, equipment and medium, and the method comprises the steps: obtaining a data processing model, and compiling the data processing model into an initial processing task based on hardware architecture features of a systolic array, acquiring to-be-processed data and analyzing data characteristics of the to-be-processed data, monitoring a real-time operation state of the systolic array processing device, inputting the real-time operation state, the data characteristics and an initial processing task into a scheduling decision module to generate a scheduling strategy, executing the scheduling strategy to complete data processing, and collecting performance data; and updating optimization parameters of the compiling module and strategy generation parameters of the scheduling decision module based on the performance data. According to the method, the initial processing task is generated through compiling, the scheduling strategy is dynamically generated in combination with the data features and the running state, parameter updating is achieved through performance data feedback, self-adaptive closed-loop optimization of compiling and scheduling is formed, and the calculation efficiency and the energy efficiency ratio are improved.

The invention discloses an idle computing power resource dynamic scheduling method based on node allocation, and relates to the technical field of node allocation. Sequentially executing to-be-scheduled calculation tasks to perform lightweight simulation execution to generate task feature vectors, collecting idle node hardware architecture feature data to generate node hardware feature tags, calculating a matching degree based on a bidirectional adaptability evaluation matrix, allocating main execution nodes, and performing task scheduling; the redundancy is determined by combining the task key level and the overall reputation score of the node pool, the standby redundant nodes are allocated for parallel execution, and the closed-loop scheduling process of the consensus verification window period and the arbitration mechanism is synchronously set, so that compared with the prior art, the accuracy of idle-time computing power scheduling and the credibility of an execution result can be improved, and the scheduling efficiency is improved. Therefore, the problems of low resource utilization rate and high error rate of calculation results caused by disjunction of task and node adaptation and lack of effective verification in the execution process in the existing idle computing power scheduling can be solved.

The invention relates to the field of tensor processing, and provides a tensor dimension recombination method and device for a tensor processing unit, and a chip. The method comprises the following steps: checking whether the total number of elements of an input tensor is equal to that of elements of a target output tensor; based on the shape parameters of the input tensor and the target output tensor, storage layout information and hardware architecture characteristics of a tensor processing unit, performing mode judgment on the current dimension recombination operation to judge whether the current dimension recombination operation is matched with a preset high-frequency special judgment mode or not; when the current dimension recombination operation is matched with the high-frequency special judgment mode, a hardware acceleration execution mode corresponding to the high-frequency special judgment mode is adopted, and tensor dimension recombination is completed in an on-chip storage range; when the current dimension recombination operation is not matched with the high-frequency special judgment mode, tensor dimension recombination is completed through parallel computing and cooperative processing in a general recombination execution mode oriented to a hierarchical storage structure. The respe execution efficiency can be improved, occupation of on-chip memory resources is reduced, and waste of bandwidth resources is avoided.

The invention provides an airborne task system comprehensive video display device and method, the system comprises a device main body, the device main body comprises a programmable logic device, a video processing unit, a cache memory and an internal bus; the programmable logic device is configured with a plurality of video interface drivers and data interface drivers and is used for receiving video streams and data streams from external equipment; the programmable logic device is configured to analyze a video stream and a data stream, extract image pixel information and sensor data, and cache the analyzed information to the cache memory; and the video processing unit is configured to read the information from the cache memory, perform fusion processing and video coding, generate a comprehensive display picture and output the comprehensive display picture to at least one display device. According to the comprehensive video display device provided by the invention, efficient processing and real-time display of multi-source airborne data are realized through a special hardware architecture, and the system compatibility and reliability are remarkably improved.

The invention discloses a method for deploying a spiking neural network on neuromorphic hardware, and belongs to the technical field of collaborative design of neural network software and hardware. In order to solve the problem of high delay of spiking neural network deployment under different hardware topological structures and routing algorithms, modeling is mainly carried out on a mapping scheme of a neural network between hardware cores under the constraint of preset hardware parameters; and performing iterative optimization on the initial deployment scheme through the deployment scheme selection strategy to meet the response time constraint. The method can be suitable for various hardware architecture and route combinations, response time after deployment is effectively shortened, and system operation efficiency is improved.

The invention discloses a sparse reasoning method, system, equipment and product for large language model reasoning, and relates to the technical field of artificial intelligence. The method comprises the following steps: firstly, acquiring a weight matrix of a large language model, and then carrying out pruning sparsification processing on the weight matrix to obtain a sparse matrix; the storage format of the sparse matrix is converted into a bitmap coding storage format which is suitable for tensor calculation core perception and adopts a multi-level block structure to respectively correspond to different calculation granularities in a GPU / NPU hardware architecture so as to obtain a sparse model, and then the sparse model is deployed to respond to a reasoning request to perform reasoning service; sparse matrix multiplication is completed through a sparse matrix multiplication kernel based on on-chip storage bitmap coding so as to perform reasoning, so that through an innovative sparse matrix storage format and calculation optimization, the storage efficiency and the calculation performance in the reasoning process are remarkably improved, and especially in a low-sparseness scene, the reasoning efficiency is greatly improved. And the performance blank of the existing sparse reasoning framework in the field is filled.

Apparatuses, systems, and techniques to enable efficient use of mixed precision hardware architecture. In at least one embodiment, one or more first precision circuits and one or more second precision circuits are used on portions of data sets.

The invention relates to the technical field of industrial automatic measurement and control communication, and particularly discloses multi-protocol fusion intelligent measurement and control host equipment, which comprises a data acquisition module, a health assessment module, a thermal simulation module and a cooperative control module. The equipment adopts a dual-core hardware architecture with a bottom plate and a top plate, integrates seven communication interfaces, realizes multi-protocol parallel processing through a hardware accelerator and a FreeRTOS system, the protocol switching time does not exceed 10ms, and the health assessment module adopts an online incremental learning recurrent neural network to calculate the health state index of the super capacitor module in real time, so that the super capacitor module can be used as the health state index of the super capacitor module. The thermal simulation module predicts the thermal runaway risk level based on an embedded finite volume method, and the cooperative control module dynamically adjusts the rotating speed of a fan and the switching frequency of a power supply by adopting a Nash equilibrium optimization algorithm, so that early performance attenuation recognition, thermal runaway risk prediction and intelligent cooperative control of the super-capacitor module in an extreme environment are realized. And the reliability and the safety of the system are obviously improved.