609 results about "Hardware architecture" patented technology

The invention provides a split type direct current charging multi-split group charging and group control control system, and belongs to the technical field of split type direct current charging piles. The split type direct current charging system comprising a main control cabinet, a power distribution unit, a charging pile terminal and other hardware architectures is constructed; a voltage monitoring unit, a current sensor module, a harmonic filter and other multi-dimensional sensor networks are integrated to acquire power grid state data in real time, and a sliding time window method is used to carry out segmented analysis on the data to extract power grid characteristic parameters; establishing a multi-objective optimization model comprising a power balance equation and a power grid stability equation to calculate an optimal power distribution matrix, adopting a neural network to realize intelligent distribution and dynamic balance adjustment of the power of each charging pile terminal, and starting an emergency power redistribution mechanism to ensure stable operation of the system when the power grid is detected to be abnormal. The technical problem of unbalanced power distribution of the multi-pile charging system caused by power grid voltage fluctuation and harmonic pollution is solved.

The invention discloses a large language model accelerator architecture based on a three-dimensional NAND flash memory, and belongs to the technical field of calculation, reckoning or counting. The architecture comprises a three-dimensional NAND flash memory used for executing feedforward neural network calculation; the auxiliary calculation unit is used for executing attention mechanism calculation; the DRAM chip is used for storing attention mechanism related weights and KV cache; and the interconnection resource is used for realizing data interaction among the components. Wherein the three-dimensional NAND flash memory comprises a logic chip and an NAND array chip, the logic chip is used for controlling and executing calculation, and the NAND array chip is used for storing weights and participating in calculation. The invention further provides a scheduling method based on KV cache awareness. The scheduling method comprises decomposition and dynamic allocation of calculation tasks. Through collaborative design of the hardware architecture and the scheduling method, the memory wall bottleneck in large language model calculation can be relieved, the energy consumption is reduced, and the overall calculation performance is improved.

The invention discloses rendering equipment based on three-dimensional Gaussian sputtering. The hardware architecture includes a memory interface, a pre-processing engine, a cardinality ordering engine, a rasterization engine, and the like. The preprocessing engine converts the three-dimensional Gaussian point into a two-dimensional representation and generates a key value pair containing a tile identifier and depth information; the cardinal number sorting engine performs staged efficient sorting through a parallel processing mechanism and a BRAM alternate working mode; and the rasterization engine performs rendering processing by adopting a full-pipeline design and an early-stage stopping mechanism. According to the method, parallel execution of depth sequencing and rasterization is achieved, memory access and calculation redundancy are reduced through optimized data flow design, an efficient and low-power-consumption hardware acceleration solution is provided for three-dimensional Gaussian sputtering rendering, and the method is particularly suitable for application scenes such as virtual reality, games and scientific visualization requiring real-time rendering.

The invention belongs to the field of edge computing, and relates to a model deployment method based on pruning compression in an edge device, which comprises the following steps of: constructing a joint constraint condition set by analyzing hardware architecture configuration of a target edge device, and determining an upper limit of a compression ratio of each network layer of a to-be-deployed model in combination with an interlayer dependency relationship of the to-be-deployed model; the method comprises the following steps: performing hybrid pruning operation on a to-be-deployed model, reserving a redundant weight block on a key network layer, compiling and deploying the pruned model, sensing environment operation interference characteristics in a running period after the model is deployed in real time, and judging whether to trigger an online fine tuning mechanism to update parameters of the redundant weight block. And the pruning boundary parameters are iteratively optimized based on the fine tuning performance feedback data, so that the risk of model collapse caused by a static pruning strategy in the prior art is avoided, continuous self-adaption and performance optimization of the model on the resource-constrained edge device are realized by reserving redundant weight blocks, and the deployment flexibility of the edge device model is effectively improved.

The invention discloses a multi-modal space-time fusion and distributed cluster fire extinguishing robot cooperative control system, aims to solve the problems of low efficiency and poor precision of multi-machine cooperative fire extinguishing in wide-area fire investigation and flammable and explosive scenes, and provides a whole set of unmanned fire extinguishing technical solution for the multi-mode space-time fusion and distributed cluster fire extinguishing robot cooperative control system. The system comprises four core hardware architectures, namely a cloud dispatching center (A), an unmanned aerial vehicle cluster (B), an unmanned resource guarantee vehicle (C) and a crawler-type fire extinguishing robot cluster (D), and has the following core functions: 1, the cloud dispatching center (A) updates a fire scene model through distributed dispatching by fusing multi-modal sensor data, dynamically allocates tasks and plans a safe approach path; 2, the unmanned aerial vehicle cluster (B) executes the instruction, completes fire global positioning and cluster cooperative sensing, generates a high-precision fire topographic map and feeds back a signal; thirdly, the unmanned resource support vehicle (C) autonomously says for help, and has the functions of automatic mechanical arm water feeding and power supply, environment detection, on-site cleaning after fire extinguishing and communication relay; and fourthly, the crawler-type fire extinguishing robot cluster (D) autonomously navigates and positions the root of a fire source, detects and predicts the drop point of a water column, carries out fire extinguishing feedback evaluation, and interacts with the dispatching center cooperatively to dynamically adjust the strategy, so that closed-loop control is formed, and the fire extinguishing efficiency and accuracy are remarkably improved.

The invention discloses a network construction type inverter for a photovoltaic energy storage system and a virtual synchronous machine control method. The network construction type inverter comprises an inverter power module and a central controller. The central controller is used for collecting power grid operation data in real time and generating a power grid impedance state vector through online impedance identification; and dynamically adjusting virtual inertia and damping parameters of the inverter power module according to the impedance state vector by using an adaptive mapping function so as to realize cooperative control and circulating current suppression between the modules. Performing stability boundary evaluation based on the adjusted parameters, then performing intelligent early warning of the photovoltaic energy storage system, and smoothly switching the operation mode of the inverter power module; according to the invention, through deep integration of a modular hardware architecture and intelligent adaptive control, the inverter has strong autonomous network construction capability, the problems of weak power grid adaptability and transient stability are effectively solved, and the dynamic response and reliability of a photovoltaic energy storage system are improved.

The invention provides a multimode communication network dynamic scheduling system fused with AI computing power, which belongs to the technical field of communication equipment and artificial intelligence hardware fusion, and is characterized in that based on a four-layer hardware architecture of'core control-computing power support-multimode communication-high-speed interconnection ', an interconnection layer is constructed by adopting high-speed interfaces such as PCIe / SGMII + and the like, and inter-module fault is realized; 10ms low-delay data transmission is realized; the AI computing power module integrated with the 8TOPS NPU is deeply coupled with the multi-mode communication module, and the AI computing power module is quantized and compressed through an LSTM / Transform model and then solidified to an NPU special storage to realize scene self-adaptive scheduling; a'acquisition-identification-decision-feedback 'hardware closed loop is established, the communication interruption rate is reduced in an emergency scene, the overall power consumption is reduced, and AI reasoning is delayed. Through breakthrough hardware architecture design, AI computing power and a multi-mode communication module are deeply integrated, an intelligent communication resource scheduling system is constructed, and dynamic optimal configuration of communication resources in multiple scenes can be realized.

The invention provides a notebook computer pre-installed environment simulation test method and system based on a virtualization technology, and the method comprises the steps: firstly creating a virtualization environment instance which is matched with a target notebook computer hardware architecture and comprises a pre-installed operation system and a preset software set, and then injecting a simulation user operation behavior sequence according to a predefined environment configuration strategy, the method comprises the steps of generating a dynamic test case set, executing and monitoring running state data in a virtual environment instance, generating an environment compatibility analysis report by extracting an abnormal response mode in the running state data, and finally adjusting resource configuration parameters of the virtual environment instance according to the environment compatibility analysis report. And generating the optimized pre-installed environment mirror image file, so that efficient and comprehensive simulation test on the notebook computer pre-installed environment is realized, and the test efficiency and accuracy are effectively improved.

The invention requests to protect a multifunctional FFT (Fast Fourier Transform) hardware acceleration architecture capable of configuring software in real time, which comprises a first sample sequence rearrangement module, a first calculation unit, a second sample sequence rearrangement module, a second calculation unit, a third sample sequence rearrangement module, a butterfly operation circuit, a multiplexer and a dual-port RAM (Random Access Memory) which are sequentially connected end to end, in order to solve the technical problems that in an existing FFT hardware architecture, the operation length is fixed, the function is single, the fftshift function is lacked, and software dynamic configuration cannot be achieved, through software and hardware collaborative design, FFT hardware has operation flexibility, functional diversity and frequency spectrum processing capacity; the method can be widely applied to various digital signal processing scenes such as communication, images, radars and audios.

The embodiment of the invention provides a data processing method, a data processing device, electronic equipment and a storage medium. The data processing method includes: receiving a signal about an input tensor and an index tensor; target data are read from a source storage space corresponding to the input tensor based on the index tensor through a general tensor operation interface, the target data are written into a target storage space corresponding to the output tensor, and the general tensor operation interface supports unified tensor operation involving at least two data arrangement modes. According to the data processing method, a universal and efficient index operation implementation scheme is provided, different data arrangement modes can be adapted, and complex index access requirements under different hardware architectures are compatible, so that the generalization ability and execution efficiency of index operators are remarkably improved, and the data processing efficiency is improved. High-efficiency and low-latency indexing operation on heterogeneous computing equipment can be supported.

The invention discloses a GPU Box hardware decoupling system based on a Retimer card and a PCIe Switch chip, and belongs to the technical field of computer hardware architecture and high-speed interconnection. According to the system, a Retimer card and a PCIe Switch chip are integrated in an independent GPU Box, and a decoupling link of a CPU server and a GPU acceleration card is constructed; the Retimer card realizes 30-meter long-distance PCIe signal transmission and breaks through physical distance limitation; the PCIe Switch chip pools GPU resources through a dynamic routing and MRIOV technology, supports flexible allocation of computing power by multiple servers, and realizes Peer-to-Peer direct connection communication between GPUs. Aiming at a large model reasoning scene, the system optimizes KV cache bandwidth allocation and video memory and memory cooperative scheduling, so that the 100B parameter model reasoning throughput is greatly improved; and meanwhile, the usability of the system is greatly improved through fault isolation and hot plug design. According to the method, the problems of physical binding of the CPU and the GPU, limited transmission distance, rigid resource allocation and the like in a traditional architecture are solved, and the method is suitable for large-scale AI calculation and distributed GPU cluster deployment.

The invention relates to the technical field of intelligent detection of power equipment, in particular to a complex illumination low-voltage electricity meter frequency sensing detection method, system and equipment and a medium, and aims to solve the problems of high-frequency noise interference, intra-class feature difference, insufficient edge end energy efficiency and the like existing in electricity meter detection in a high-brightness environment. Proposing a dynamic frequency domain compensation mechanism to suppress light noise and recover signal details, and optimizing dense scene feature consistency in combination with adaptive filtering and a multi-scale sampling strategy; the boundary fuzzy problem is solved through dynamic feature alignment and an edge compensation mechanism, and parallel acceleration of frequency domain decomposition and dynamic resampling is realized by adopting a heterogeneous hardware architecture; a multi-modal data training framework and a cross-domain transfer learning strategy are fused to enhance the generalization ability of the model; according to the invention, collaborative optimization of detection precision, real-time performance and low power consumption is realized in a complex illumination scene, and high-robustness technical support is provided for intelligent power grid inspection.

The invention provides an MCU function security implementation system based on a domain controller, and relates to the technical field of domain controllers, the system realizes dual backup storage and on-site execution of program codes by combining a security MCU without a built-in program memory with at least two redundant plug-in nonvolatile storage units, and the security of the MCU is improved. Consistency verification is carried out on key codes or data in the running process, and system failure caused by single-point storage faults or data tampering is effectively prevented; meanwhile, read-write operation without losing data during power failure is isolated through the independent data storage unit, and resource conflict and interference between program execution and data storage are avoided; the ASIL D-level power management unit supporting two-way fault monitoring is matched, resetting can be triggered in time or the MCU enters a safe state when a power supply is abnormal or an MCU internal fault occurs, and therefore a high-reliability and high-safety domain controller MCU system is constructed on the hardware architecture level, and the capacity of the MCU for meeting the ASIL D function safety level in a plug-in storage scene is improved.

The invention provides a closed-loop nerve regulation and control system and method based on electroencephalogram detection. The defects that a traditional open-loop method lags in stimulation, equipment is heavy and the like are overcome. The system integrates an electroencephalogram acquisition module, an electroencephalogram analysis module, a remote program control module and a stimulation output module to form a closed-loop link. Through 32-channel 1kHz signal acquisition and 1-100Hz filtering pretreatment, pathological features are extracted in real time by using a deep convolutional neural network, stimulation parameters are modified through a remote program control module, and multi-channel collaborative stimulation and safe electrical stimulation are realized in combination with a time division multiplexing architecture and bipolar optocoupler isolation output. The method has the advantages that the pathological feature recognition accuracy of the deep convolutional neural network is greater than or equal to 95%, and the dynamic response delay is less than 50ms; a time division multiplexing hardware architecture is designed, multi-channel collaborative stimulation is achieved through a single DAC, and the size is reduced by 30%; + / -5V bipolar output is realized by using an optocoupler isolated H bridge driver, and the IEC 60601 medical safety standard is met; wireless regulation and control of stimulation parameters are supported, the long-term implantation requirement is met, and the risk of a secondary operation is reduced.

The invention discloses a coal loading and unloading equipment operation detection system based on visual identification, and relates to the technical field of visual identification. The system comprises a hardware architecture and a software architecture, the hardware architecture comprises an image acquisition unit, a data processing unit and a control feedback unit; the software architecture comprises an image processing layer, an intelligent analysis layer and a decision application layer; the image processing layer comprises an image acquisition subsystem, a preprocessing algorithm library and a feature extraction module; the intelligent analysis layer comprises a target detection and identification module, a three-dimensional reconstruction module and an abnormal behavior identification module; and the decision application layer comprises a rule engine, an alarm management subsystem and a data visualization platform. By deploying sensor equipment such as a multi-angle industrial camera and a laser radar and combining a deep learning algorithm and a computer vision technology, various illegal operations and abnormal conditions in the loading and unloading process are automatically identified, total-factor digital monitoring of the loading and unloading process is realized, the detection efficiency is improved, and the loading and unloading risk is reduced.

The invention provides an FPGA (Field Programmable Gate Array) implementation method for receiving and transmitting 16-path CAN (Controller Area Network) and 16-path serial port data. The FPGA implementation method comprises the following steps of: constructing a hardware architecture suitable for efficiently receiving and transmitting the 16-path CAN and 16-path serial port data by utilizing the characteristic of cooperative work of a processing system PS of XC7Z045FFG900-2 and a programmable logic PL; a CAN bus controller on the PL side is configured; configuring a serial port transceiver chip at a PL side; a ping-pong buffering function on a PL side is realized; establishing register mapping; and a double-AXI interface collaborative interaction mechanism of the PL side and the PS side is realized. The method has the beneficial effects that the ping-pong buffer technology and the parallel processing capability of the FPGA are adopted, so that efficient concurrent processing of 16-path CAN and 16-path serial port data is realized; through reasonable hardware design and register configuration, the stability of communication between the CAN bus and the serial port is ensured; based on the programmable characteristic of the FPGA, the system is flexibly configured and adjusted according to different application requirements; the advantages of an XC7Z045FFG900-2 hardware platform are fully exerted, and the resources of the PL side and the PS side are reasonably distributed and utilized.

The invention belongs to the technical field of braille input, and particularly relates to a braille input system, device and method, the input system comprises a braille input module, a braille display module, a communication module, a voice broadcast module, an algorithm processing unit and a core control unit, and the device is a contact display assembly and comprises a reset spring, a coil, a driving needle and an iron core. A plurality of round holes for accommodating the contact display components are formed in the shell, the iron cores, the reset springs and the driving needles are sequentially arranged in the round holes from bottom to top, the coils are sleeved on the iron cores, and the driving needles extend out under the action of the traction springs to form Braille convex points. According to the Braille input method, through hardware architecture optimization and multi-algorithm fusion, a Braille input solution with low cost, high portability and high recognition rate is realized, meanwhile, triple interaction modes of voice broadcast, visual display and tactile feedback are integrated, and the information interaction efficiency of visually impaired groups is remarkably improved.

The invention discloses an interface conversion device and circuit, electronic equipment and an interface conversion method, and relates to the technical field of computer system structures. Extracting a cache or memory transaction request from the first preset interface signal through a channel processing module, generating consistency transaction information, sending the consistency transaction information to a consistency transaction concurrent processing module, receiving response data of the consistency transaction concurrent processing module, and packaging the response data into a second preset interface signal; the consistency transaction concurrent processing module carries out processing according to the received consistency transaction information to obtain a concurrent signal; and the interface conversion module decodes and converts the concurrent signal into a first target protocol control signal, and / or converts the authorized transaction into a second target protocol control signal. Therefore, concurrent analysis, consistency transaction mapping and direct conversion are carried out on a multi-channel protocol through a configurable modular hardware architecture, and high-concurrency and low-delay protocol conversion and cache consistency maintenance between an inter-chip consistency interconnection protocol and an on-chip bus protocol are realized.

The invention provides a cloud edge collaboration algorithm arrangement and deployment method, system and device and a storage medium, and relates to the technical field of cloud edge collaboration.The method comprises the steps that algorithm task requirements input by a user are analyzed, and after corresponding task information is obtained, an intermediate representation file is generated; collecting computing power state information of the plurality of edge devices to determine a target edge device used for executing an algorithm link, and generating an operation parameter configuration file according to a hardware architecture of the target edge device and algorithm characteristics of the intermediate representation file; and issuing the intermediate representation file and the operation parameter configuration file to the target edge device, and performing automatic compiling and deployment according to the chip type of the target edge device. By issuing the intermediate representation file and the operation parameter configuration file to the target edge device and automatically executing compiling and deployment, the effects of cross-platform automatic adaptation, rapid deployment and efficient operation are achieved, and the problem that in the prior art, task organization and deployment flexibility is insufficient is solved.

The invention discloses an https protocol data forwarding system for ultrahigh frequency data, and relates to the technical field of data forwarding, the forwarding system comprises a client initialization module, the client initialization module comprises a hardware adaptation layer, a data forwarding layer and a data forwarding layer, the hardware adaptation layer is based on reader-writer development boards of different architectures, generating a binary running file matched with the hardware architecture through a cross compiling tool chain; the library function integration layer is used for integrating an encryption module and a URL (Uniform Resource Locator) analysis module of a Curl library, and loading to a development board system in a dynamic link library or static link library form; and a data processing interface. On the premise of guaranteeing the data transmission security, the transmission efficiency of the ultrahigh frequency data and the stability of the system are greatly improved, many problems in the prior art are effectively solved, and the ultrahigh frequency data transmission system has remarkable innovativeness and practicability, can be widely applied to various scenes with strict requirements on ultrahigh frequency data transmission, and has wide application prospects. And a powerful technical support is provided for the development of related fields.

The invention provides an FPGA (Field Programmable Gate Array) multi-modal control method based on dynamic partial reconfiguration, which comprises the following steps that: a main body adopts a layered hardware architecture to realize multi-modal control, firstly, a system module of a whole system is divided, so that FPGA logic resources are divided into a static region and a reconfigurable region; wherein the static area is responsible for global control and a communication interface part, the reconfigurable area realizes a multi-mode function by loading different configurations, and the middle layer is used for deploying the dynamic part to reconfigure a controller and is responsible for time sequence coordination and bit stream management. Compared with the prior art, the method has the advantages that the mapping relation between the modal feature library and the hardware module is established, the priority preemptive reconfiguration strategy and the modal switching cost model are adopted, the real-time matching of the sensor data flow and the hardware architecture is achieved, the dynamic data path reconstruction technology supports multi-modal parallel processing, and the real-time matching of the sensor data flow and the hardware architecture is achieved. Meanwhile, time sequence constraint, resource occupancy rate and power consumption budget are considered.

The invention discloses a dynamic self-adaptive precision switching method for a voice recognition NPU, and aims to solve the core problems that precision and energy efficiency of an end-side voice recognition NPU in multiple scenes cannot be considered at the same time, fixed-precision hardware resources are seriously wasted, software switching efficiency is low, and errors are accumulated. A hardware architecture of a 4 * 4 reconfigurable MAC subunit array and a switch matrix is constructed, and a task-driven adaptive scheduling mechanism, an operation period synchronous control technology (single-period hardware reconfiguration is realized by utilizing idle gap latch configuration) and a direction-sensitive error compensation algorithm (historical data interpolation extension or correction truncation) are combined; hardware-level dynamic lossless switching of the MAC unit between 8bit / 16bit / 32bit precision is realized, so that different voice tasks achieve the highest necessary computing power with the lowest necessary power consumption, no data is lost in the switching process, and finally, the energy efficiency rigidity of a fixed-precision framework is oppositely converted into the precision on-demand supply capability capable of being deployed in an engineering manner.

The invention relates to the field of computer hardware architecture, in particular to a parallel processor dynamic resource allocation method, system and device and a storage medium, and the method comprises the steps: monitoring inter-node communication indexes and in-node parallel processor index data in real time; calculating an optimal connection path through an optimization algorithm which comprehensively considers the communication cost between nodes and the load balancing condition of a parallel processor; dynamically adjusting the configuration of a switch matrix according to the optimal connection path so as to switch the connection topology between the nodes; inputting the monitoring data of the continuous time window into the trained LSTM prediction model, and predicting a load prediction value in a future set time period; and according to the task priority, the resource state of the parallel processor and the load prediction value, dynamically adjusting the resource allocation of the parallel processor, and generating a resource allocation table. The communication cost between the nodes is reduced, the performance bottleneck caused by unsmooth communication is avoided, the load balancing of the parallel processor is realized, and the resource utilization rate is improved.

A method for securing a plurality of compute nodes includes authenticating a hardware architecture of each of a plurality of components of the compute nodes. The method also includes authenticating a firmware of each of the plurality of components. Further, the method includes generating an authentication database comprising a plurality of authentication descriptions that are based on the authenticated hardware architecture and the authenticated firmware. Additionally, a policy for securing a specified subset of the plurality of compute nodes is implemented by using the authentication database.

The invention discloses a distributed AI training task processing method and system, and relates to the technical field of cloud computing. The distributed AI training task processing method comprises the steps that labels are set for hardware resources of nodes of each cluster of each cloud platform, and resource information of each hardware resource is acquired; and intercepting a CRD configuration file containing a hardware resource quantity request through a pre-deployed webhook service in the cluster, and creating an AI training task carrying the hardware resource quantity request after modifying resource information in the CRD configuration file into a parameter format adaptive to the hardware environment of the cluster according to the tag. According to the method and the device, hardware resources in multi-cloud platform heterogeneous resources can be scheduled and used in a unified manner without manual intervention, dynamic parameter adaptation and automatic injection of hardware resource configuration can be completed through the webhook service deployed in the cluster, and seamless resource scheduling and adaptation across cloud platforms and across hardware architectures are realized.

The invention belongs to the technical field of fault-tolerant control of an electronic system, and particularly relates to a dual-microcontroller system and a control method thereof, and the dual-microcontroller system comprises a hardware architecture and a software architecture; the hardware architecture specifically comprises a main MCU module, a standby MCU module, a dual-power module, a dual-measurement acquisition module, a hardware arbiter and an output switching value module; the software architecture comprises the steps of initializing a data synchronization communication interface of the main MCU module and the standby MCU module, starting the main MCU module and the standby MCU module, reading data of the measurement acquisition module in a working program state machine by the main MCU module, interacting with external equipment through the communication interface and driving switching value output; and when the main MCU module has no fault, the hardware arbiter selects the switching value output of the main MCU module to drive the external equipment, and when the main MCU module has a fault, the hardware arbiter selects the switching value output of the standby MCU to drive the external equipment.

The invention relates to the technical field of project supervision informatization, and provides a supervision multi-heterogeneous system cloud edge collaborative adaptation method, which comprises the following steps: collecting heterogeneous information such as edge equipment hardware architecture and an operating system to generate records; integrating supervision monitoring data and cloud instructions, classifying the data according to functions and updating frequencies, and marking high-frequency units; unifying a data format and adding Hash verification information; the cloud constructs a three-dimensional mapping table, and edge nodes are grouped in combination with high-frequency data; converting the private protocol of the edge device into a general protocol; by taking minimization of transmission quantity and energy consumption as a target, distributing tasks by using an integer linear programming model; dynamically adjusting the equipment energy consumption; and dynamically optimizing the configuration based on the interface indexes. The cloud edge interaction efficiency can be improved, the energy consumption is reduced, and the reliable operation of supervision business is ensured.

The invention provides a software and hardware integrated intelligent terminal power transaction system and method, relates to the technical field of power market transaction, and solves the technical problems of data potential safety hazards and insufficient real-time performance caused by dependence on an external platform in a power transaction process in the prior art. The system specifically comprises a hardware architecture and a software function module, the hardware architecture comprises a processor, a redundant power supply, a storage device, a network interface, a security encryption chip and a display interface; the software function module comprises a core function layer, an interface layer and a security layer; wherein the core function layer is used for being responsible for processing and controlling the whole flow of power transaction; the interface layer is used for carrying out standardized and ordered external data interaction; and the security layer is used for guaranteeing the security of the terminal from multiple dimensions of communication, transaction, data and operation and maintenance. The method is used for electricity market transaction.

The invention discloses a compiling optimization device and method supporting Page Attention and a medium, and belongs to the field of compiling optimization devices.The device comprises a multi-core AI accelerator, and each calculation core comprises a tensor component, a vector component, a DMA component and an IMM component; the compiling optimization device is optimized through the following modules: (a) a KV Cache management module, which is used for storing page table items corresponding to different KV Cache blocks according to a batch sequence and generating standardized page table items; (b) a DMA control module which supports a linear reading and remapping mode, carries discrete KV Cache blocks from an external memory to an on-chip weight buffer area in a segmented manner according to an index table, and hides data loading delay by adopting a double-buffer technology; and (c) a multi-batch reasoning scheduling module which dynamically allocates computing resources according to the data scale in a code stage. According to the invention, through deep cooperation of a hardware architecture and functional logic, the problems of low KV Cache management efficiency, complex multi-batch dynamic scheduling and insufficient computing resource utilization rate on an ASIC platform are solved.

The invention discloses a construction method for dynamically reconstructing a multi-modal edge computing hardware architecture and a cross-industry application method, and relates to the field of edge computing hardware architectures. A five-level heterogeneous architecture is adopted to construct a field self-adaptive dynamic reconstruction calculation unit, and an equipment abstraction layer is constructed to realize module hot plugging and calculation power distribution; a multi-protocol ubiquitous interconnection interface engine is established, a hardware-level analysis architecture is integrated, and multi-protocol analysis and rapid switching are supported; an environment self-adaptive energy efficiency regulation and control system is deployed, and wide-temperature operation is realized by adopting a bionic composite heat dissipation design; an edge-region-cloud three-layer elastic scheduling network is constructed, cross-domain computing power arrangement is realized through federal learning, and the method is adaptive to multi-industry scenes. According to the method, the hardware reuse rate and the wide-temperature environment adaptability are improved, the multi-protocol processing delay is reduced, the computing power scheduling efficiency is optimized, the limitation of traditional equipment is broken through, and the efficient and stable operation requirements of cross-industry scenes such as electric power and medical treatment are met.