81 results about "Hardware architecture" patented technology

This invention belongs to the field of intelligent agent large language model service technology, and discloses a chip computing system, device and application for intelligent agent large language model. Through the collaborative design of hardware architecture and software scheduling, it systematically solves the core technical challenges faced by intelligent agent large language model services. Specifically, it includes a hardware and software collaborative implementation scheme for resource partitioning, key-value cache management and runtime scheduling of pre-filling, decoding and tool call related workloads in a multi-chip encapsulation and inconsistent memory access environment.

This invention belongs to the field of artificial intelligence hardware architecture design and discloses a method, system, device, and medium for cross-layer optimization of multi-core packaging and optical interconnect clusters for large language model training. The method includes: constructing a design space, including a core hardware architecture layer, an optical interconnect network layer, and a training parallel strategy layer; performing an outer-layer search to search for the architecture parameters of the multi-core modules within the core hardware architecture layer; for each outer-layer search sampling point, performing an inner-layer search to collaboratively optimize the optical interconnect network topology and training parallel strategy within the optical interconnect network layer and the training parallel strategy layer; and outputting the Pareto optimal design point on the training performance and cluster cost plane. The technical solution described in this invention can guide the design of related training clusters, thereby fully leveraging the advantages and potential of core technology and optical interconnect technology in large language model training.

This invention belongs to the field of flight control computer hardware architecture technology, specifically relating to a heterogeneous flight control core circuit and system. This invention integrates a microcontroller unit and an artificial intelligence coprocessor unit on the same printed circuit board, achieving data and command interaction through isolated high-speed interconnect channels. The microcontroller unit constitutes the safety control and real-time decision-making domain, used to execute safety-critical and hard real-time tasks, and to implement operational management and fault isolation for the artificial intelligence coprocessor unit; the artificial intelligence coprocessor unit constitutes the intelligent sensing and computing domain, used to execute computationally intensive and non-real-time critical tasks. This architecture achieves decoupling and collaboration between the safety domain and the computing domain at the hardware level, ensuring both high functional safety and determinism in flight control, while fully releasing the high-performance computing power required for intelligent sensing, thus meeting the dual requirements of advanced aircraft for highly reliable flight control and intelligent function expansion.

The application provides a gateway device and system for a distributed photovoltaic power generation system and a communication method, comprising a master control module, a downlink communication module, a data processing module, and an uplink communication module, which can support multi-protocol compatibility, high integration, high reliability, and deep fusion Internet of Things technology. The application can improve compatibility and integration: unified conversion of multi-brand device bottom layer data into IEC104 standard protocol, breaking heterogeneous barriers; high integration hardware architecture greatly reduces device volume, realizing seamless embedding with field circuit breakers. Optimize deployment efficiency: built-in one-key configuration logic, automatically identify online devices and dynamically generate polling lists through active broadcast handshake, eliminating manual entry hassle and significantly reducing field implementation cost. Safeguard system security: establish an abnormal interruption triggering mechanism, skip regular polling when monitoring data is out of limit, real-time priority transmission of alarm messages, realize second-level response to power station risks, and reduce device damage rate.

Embodiments of the present disclosure relate to the field of processor hardware architecture, and provide an artificial intelligence chip and a computing system. The artificial intelligence chip comprises a first computing core, a shared memory device corresponding to the first computing core, and a data synchronization device. The first computing core is configured to issue a first data request instruction. The data synchronization device is configured to perform a read operation on first data, a flag detection operation, and a synchronization operation according to the first data request instruction. The first data is stored in a global memory device coupled to the artificial intelligence chip. The synchronization operation comprises sending the first data to the shared memory device. The shared memory device is configured to store the first data sent by the data synchronization device for reading by the first computing core. Embodiments of the present disclosure hardwareize data synchronization and retry, significantly reduce communication delay, and release core computing resources of the artificial intelligence chip.

The application provides a maintainable control unit architecture for spacecraft, comprising a hardware architecture and a software running architecture; a high-performance CPU processor is selected, and the following devices are externally expanded: one piece of one-time programming anti-fuse PROM memory for storing a boot program; one piece of large-capacity FLASH memory for storing application software; and one piece of large-capacity SRAM memory for software running. The application provides a high-reliability and maintainable control unit architecture for spacecraft, which can meet the demand of long-term on-orbit spacecraft for high-reliability and maintainable control units, and ensure the high-reliability storage and running of the boot program.

This invention provides an industrial control system for electrically heated molten salt thermal energy storage that absorbs fluctuations in wind and solar power generation. Belonging to the fields of energy and electrical engineering, it includes a hardware architecture for the measurement and control of the electrically heated molten salt thermal energy storage system, a communication architecture for the system's equipment, and a software architecture for its measurement and control. This invention combines a stable hardware platform, an efficient communication architecture, and flexible industrial control algorithms to achieve real-time monitoring and industrial control of key parameters during the molten salt thermal energy storage process. While absorbing fluctuations in wind and solar power generation, it effectively improves the overall operating efficiency and reliability of the system, ensuring stable operation under different conditions and promoting the application and development of molten salt thermal energy storage technology in the field of large-scale energy storage.

This invention relates to a three-site mutual backup method under a commercial encrypted network virtualization architecture, belonging to the field of network communication technology. It addresses the technical problems of existing cross-regional and cross-network segment communication schemes, including insufficient interconnection security, adaptability, data backup efficiency, fault switching response speed, hardware architecture cost-effectiveness, and incomplete scenario coverage. The method includes the following steps: master station backup generation; parallel off-site replication; breakpoint resumption and anomaly recovery; local storage and version retention at branch stations; fault switching and local recovery. The three-site mutual backup method under the commercial encrypted network virtualization architecture of this invention offers: superior interconnection security and adaptability, more efficient and complete data backup, low-impact automated fault switching, a more reasonable and cost-controllable hardware architecture, higher detection accuracy, and stronger scalability.

The application provides a method and system for deploying a large language model on a graphics card with limited computing power, relating to the technical field of software engineering, and aiming at the characteristics of the target graphics card hardware architecture lacking a dedicated matrix acceleration unit, reconstructing key operators required by the large language model, including: adapting the core computing process of the key operator to be executed by the general computing unit of the graphics card; optimizing the key operator to make it suitable for a computing scenario with an input dimension of 1xN; quantizing the model weights in the key operator by 4-bit integers and using 16-bit floating-point numbers for activation in the forward calculation process; constructing a lightweight inference engine; loading the target large language model and executing the inference task on the target graphics card by using the lightweight inference engine. The application realizes system-level improvement in three dimensions of hardware compatibility, resource utilization, and inference efficiency, and provides a feasible technical path for deploying advanced large models on a wide range of existing and low-power graphics cards.

The present application relates to the field of project supervision information technology, and provides a supervision multi-heterogeneous system cloud edge collaborative adaptation method, which comprises collecting edge device hardware architecture, operating system and other heterogeneous information to generate records; integrating supervision monitoring data and cloud instructions, classifying data according to functions and update frequencies and marking high-frequency units; unifying data formats and adding hash check information; constructing a three-dimensional mapping table in the cloud, combining high-frequency data grouping edge nodes; converting edge device private protocols into general protocols; using an integer linear programming model to allocate tasks with the goal of minimizing transmission volume and energy consumption; dynamically adjusting device energy consumption; and dynamically optimizing configuration based on interface indicators. The method can improve cloud edge interaction efficiency, reduce energy consumption and ensure reliable operation of supervision business.

The application discloses an engine electronic control method based on an AI agent, and relates to the field of engine electronic control.The method comprises the following steps: S1, based on bottom support, collecting engine state signals, receiving vehicle instructions, collecting deviation data, and executing control instructions; the bottom support comprises a heterogeneous multi-core SoC hardware architecture; S2, based on the heterogeneous multi-core SoC hardware architecture, at least three physically isolated computing domains are divided, and the following is executed respectively: reaction agent logic, planning agent logic and learning agent logic; S6, further comprising deploying a shared digital twin engine: a digital twin model based on an integrated physical mechanism model and a neural network model, which simulates the running state and performance parameters of the engine in real time, and provides a prediction basis for the planning agent logic and an update object for the learning agent logic.

A low-area hardware architecture to execute the ASCON cipher suite and resist side-channel attacks that have a co-processor having controllers, register file, a permutation operably configured to receive input from a multiplexor structure and execute ASCON permutation, an ASCON state register that can be optionally removed and substituted by the register layer inside the permutation unit, and XOR logic gates that are operably configured to receive input from the register file and the permutation unit and provide input to the multiplexor structure.

This invention provides an interactive system based on a low-power MCU and an attitude sensor, including a microcontroller unit, an attitude sensing unit, a dynamic display unit, and an interaction unit. The microcontroller unit generates and outputs control signals to the dynamic display unit in real time based on data from the attitude sensing unit and input from the interaction unit, presenting dynamic visual feedback related to the attitude action logic. This invention aims to solve the problems of disconnect between interaction and display, fixed user experience, high hardware costs, and insufficient performance on low-resource platforms in existing technologies. By optimizing the hardware architecture and innovating control algorithms, it achieves intelligent mapping of action, physical logic, and dynamic lighting effects on an 8-bit MCU platform, balancing cost-effectiveness and interactive experience.

The application relates to the field of artificial intelligence and hardware acceleration technology, in particular to a model migration method and system, an electronic device and a computer storage medium, the method comprising the following steps: determining a mapping operator and a replacement operator of a to-be-migrated model based on hardware characteristic description information of a target platform, wherein the to-be-migrated model is a model to be migrated to the target platform; obtaining a task type of a calculation task, determining a network structure based on the task type and the hardware characteristic description information, wherein the calculation task is a to-be-executed task input by the to-be-migrated model, and the network structure is used for adapting the to-be-migrated model to the target platform; and deploying the mapping operator and the replacement operator to the target platform through the network structure and the hardware characteristic description information, so as to obtain an executable model adapted to the target platform. The application solves the technical problem of insufficient operator adaptation caused by hardware architecture difference when a model is migrated to an NPU.

This invention relates to the field of embroidery machine control technology, specifically to a method and related equipment for full preloading and motion isolation control of an embroidery machine. The method includes: the HMI (Hardware Management Interface) preloading the pattern file to the hardware data storage layer via a general-purpose slow bus; the motion execution layer connecting to the read port of a dual-port large-capacity memory via a dedicated high-speed parallel interface; the motion execution layer sending a data request by pulling up the data request signal line through the hardware interface; the DMA controller automatically triggering data block transfer upon detecting the rising edge; returning a response via the data response signal line after the transfer is completed; and locking the progress pointer to a non-volatile storage area when an HMI communication interruption is detected, allowing the motion execution layer to continue independently completing the embroidery operation. This invention, by constructing a three-level distributed hardware architecture with storage-computation separation and motion isolation, eliminates the impact of HMI non-real-time nature on motion control stability, achieving smooth operation and fault immunity for ultra-large patterns.

A model-as-a-service (MaaS) platform includes an intelligence layer that tracks modality-specific token utilization for a select customer assigned to use a first instance of a multimodal model. The first instance is instantiated within a supporting hardware architecture that allocates dedicated groups of processing resources to support different modality-specific processing pipelines. The intelligence layer uses the tracked utilization data to generate a predicted token ensemble ratio for the select customer and compares the predicted token ensemble to a compute ensemble ratio determined for each of two or more of other instances of the multimodal model. The intelligence layer re-assigns the select customer to a second instance of the multimodal model in response to determining that the predicted token ensemble ratio is more similar to the compute ensemble ratio of the second instance of the multimodal model than to the compute ensemble ratio of the first instance of the multimodal model.

This disclosure relates to a dynamic scheduling method, apparatus, device, and storage medium based on CiM. The method includes: extracting modality information and task information of an input task; dynamically determining an allocation and migration scheme for the input task from a reconfigurable mapping table based on the modality information and the task information; the reconfigurable mapping table integrating allocation and migration schemes for CiM levels corresponding to different multimodal task scenarios; allocating and migrating the input task to a target CiM level according to the allocation and migration scheme; and executing the input task in the target CiM level. This addresses the limitations of traditional fixed-mapping hardware architectures, further improves the flexibility and throughput efficiency of hierarchical CiM architectures in multimodal inference scenarios, and promotes the deep application of multimodal technology in more complex scenarios.

This invention relates to the field of information security technology, specifically to a secure computation method for medical privacy data based on CKKS homomorphic encryption. The method involves initializing a polynomial multiplication module and a CKKS module; the user end collects medical data, performs CKKS encoding and encryption, and uploads the ciphertext to the cloud; the server end deploys a disease risk prediction model, performs homomorphic inference analysis based on the ciphertext, and obtains the ciphertext result; the user end decrypts and decodes the ciphertext result, outputs a disease risk score, and obtains health data. This method makes the computation process more compatible with the GPU hardware architecture and scheduling mechanism, directly manipulates registers using assembly language to improve bit reversal efficiency, and designs a resource pool so that threads can place data into the resource pool after processing the current stage. Idle threads can find the data needed for the next stage in the resource pool without waiting and can directly execute the next stage's computation, reducing synchronization time.

This invention discloses a hardware implementation network architecture for all-digital large-scale phased array multibeamforming, comprising: a subarray including multiple TR components and a primary DBF board connected to each of the multiple TR components; the primary DBF board is used to perform digital multibeamforming on the digital signals transmitted by the multiple TR components to obtain a primary beamforming digital downlink signal, and is also used to transmit digital uplink signals to the multiple TR components; a secondary DBF board is connected to the primary DBF board, used to process the received primary digital multibeamforming signals to obtain a third-level beamforming digital downlink signal and a beamforming analog signal, and is also used to transmit the baseband digital uplink signal to the primary DBF board. This invention features a modular board design and a clear hardware architecture.

Every major DAO governance failure traces to a common root cause: governance logic, voting, and treasury access reside in software that adversaries can reach. The disclosed invention provides a hardware-anchored DAO governance architecture defeating five adversary classes. A supply-chain attestation layer verifies firmware integrity against a public transparency log at node initialization. A Silicon Root-of-Trust Anchor Layer binds governance to processor-embedded cryptographic keys. A Heterogeneous TEE Orchestration Layer enforces Byzantine fault-tolerant canonical quorum through threshold BLS signatures across independent hardware architecture families. An Atomic Governance Transition Engine executes indivisible state changes: record incorporation, key destruction, counter advancement, and IOMMU treasury isolation. A Quantum-Resistant Governance Key Lifecycle Engine performs CRYSTALS-Kyber (ML-KEM, FIPS 203) key rotation with cryptographic agility. A Cross-Chain Governance Attestation Bridge publishes TEE-signed proofs to multiple blockchains. A Deterministic Governance Replay Engine reconstructs governance decisions in isolated sandboxes. An Automated Governance Incident Response Engine and Governance Regulator Verification Network provide hardware-enforced, independently auditable compliance enforcement.

The present invention provides an efficient hardware architecture for an ORAN compliant thermal management module for a combined centralized unit and a distributed unit (CCDU) for a 5G basement application required for processing L1, L2 and L3 scheduling of the network. The CCDU design may provide the functionality of a CU and a DU with single unit and can operate over wide temperature range. A single board approach of the CCDU make the CCDU more reliable and less costly. The CCDU can support different kinds of synchronization and can provide site alarms over dry contacts to equip with external alarm device.

A model-as-a-service (MaaS) platform includes an intelligence layer that tracks modality-specific token utilization for a select customer assigned to use a first instance of a multimodal model. The first instance is instantiated within a supporting hardware architecture that allocates dedicated groups of processing resources to support different modality-specific processing pipelines. The intelligence layer uses the tracked utilization data to generate a predicted token ensemble ratio for the select customer and compares the predicted token ensemble to a compute ensemble ratio determined for each of two or more of other instances of the multimodal model. The intelligence layer re-assigns the select customer to a second instance of the multimodal model in response to determining that the predicted token ensemble ratio is more similar to the compute ensemble ratio of the second instance of the multimodal model than to the compute ensemble ratio of the first instance of the multimodal model.

This application relates to a unified cross-template matrix multiplication automatic tuning method, apparatus, computer device, and storage medium for heterogeneous accelerators. The method acquires the hardware architecture information of the target heterogeneous accelerator and the geometric dimensions of the target matrix multiplication task. It maps raw tuning parameters from various matrix multiplication template libraries to a unified parameter semantic space, orthogonally decomposing the raw tuning parameters into a shared geometric layer parameter set and a specialized adaptation layer parameter set. A first-stage search is performed in the shared geometric layer parameter set to select a preset number of preferred geometric configurations. For each preferred geometric configuration, a second-stage search is performed in the corresponding specialized adaptation layer parameter set to obtain the corresponding optimal specialized parameter combination. The preferred geometric configurations and the corresponding optimal specialized parameter combinations are fused to generate the target parameter configuration. Based on the target parameter configuration, executable matrix multiplication kernel code adapted to the target heterogeneous accelerator is generated, improving automatic tuning efficiency.

This utility model discloses a multi-system, multi-channel digital TR synchronization circuit, comprising a GPS / BD timing module, a system clock source, a multi-channel digital TR board, and a system lead generation device. The rubidium clock and second pulse of the GPS / BD timing module are respectively connected to the system clock source and the lead generation device. The sampling clock and lead clock of the system clock source, and the lead signal of the system lead generation device are respectively connected to each multi-channel digital TR board. The system lead clock of the system clock source is also connected to the lead generation device. This scheme uses the rubidium clock and second pulse of the GPS / BD timing module as a reference, and the accuracy of the lead clock determines the synchronization accuracy (e.g., a 20MHz lead clock synchronization error ≤50ns). Multi-system expansion can be achieved by adding timing modules without refactoring the hardware architecture. Its hardware and software integration reduces FPGA logic complexity, reduces hardware costs by relying on chip synchronization functions and equal-length wiring design, and ensures multi-channel synchronization stability through same-source clock allocation and equal-length signal design.

The application discloses a kind of based on localization FPGA implementation self-controllable flow table forwarding method and equipment, its method includes: based on domestic SOC type FPGA platform constructs self-controllable switching equipment supporting flow table forwarding, its hardware architecture includes control end and switch end, central processing unit is used as forwarding control layer, FPGA logic processor is used as data forwarding layer to execute high-speed parallel processing;Control end and switch end communicate by self-defined flow table interaction protocol;The software architecture of equipment includes interface adaptation layer, for realizing the mutual conversion of interface data and internal forwarding data packet;Data forwarding layer is used to execute mixed forwarding operation;Forwarding control layer is used to issue, modify or delete flow table rule to switch end by self-defined flow table interaction protocol.The application realizes the self-controllable of switching equipment software and hardware, can flexibly realize the forwarding of service data between different channels, satisfies the demand of military small network switching equipment.

The application discloses a processing method and device of attention operation, equipment and storage medium, and relates to the technical field of artificial intelligence chip hardware architecture. The method comprises the following steps: determining each query data block, each key data block and each value data block matched with to-be-processed data; determining each target attention sub-block based on each target query data block and each target key data block; in response to a generation completion instruction of the attention sub-blocks of all computing units, reading the data of a target query row in all attention sub-blocks respectively; loading the value data block corresponding to the target query row to generate a calculation result of the target attention sub-block; and in response to a processing completion instruction of all attention sub-blocks, determining an attention calculation result of the to-be-processed data based on each calculation result. The scheme of the application can avoid the block-by-block updating operation in the attention operation process, reduce calculation redundancy, fully utilize the on-chip shared cache, and improve the hardware resource utilization rate.

This invention discloses a method and system for handling emergency events displayed on a head-up display (HUD). The method uses multi-source data fusion to predictively assess driving risks and driver intentions, and calculates an urgency coefficient. It employs a dual-core MCU hardware architecture and a resource preemptive scheduling strategy. When an emergency event is determined, the high-performance main core, dedicated to emergency tasks, immediately preempts the regular display resources managed by the auxiliary core through inter-core communication, ensuring that emergency alerts are rendered with a deterministic delay of microseconds. Simultaneously, the solution introduces dynamic visual enhancement technology, enabling warning icons to move dynamically according to the direction of danger, change their shape and flashing frequency according to the risk level, and adapt their brightness according to the driver's attention level, thereby actively guiding the driver's gaze and enhancing risk perception. This invention upgrades the HUD from a passive information display to an active safety assistant, significantly improving driving safety.

This invention relates to the field of satellite telemetry, tracking, and command (TT&C) technology, specifically a rapid switching relay tracking method for densely packed satellite formations. Applied to the antenna servo embedded system of ground-based TT&C equipment for densely packed satellite formations, it solves the problems of response lag, high computational overhead, and low pointing accuracy inherent in traditional methods for tracking densely packed satellite formations. This method generates acceleration / deceleration planning sequences through ephemeris analysis, combines link indicators and preset times to achieve dual-trigger judgment for acceleration and deceleration, preloads dedicated parameter templates and adapts to the FPGA+MCU dual-core hardware architecture, employs a simplified three-stage acceleration / deceleration execution to compensate for orbital drift, verifies the status after motion and dynamically adapts parameters, and activates a backup plan in case of anomalies. This invention achieves proactive predictive planning, significantly reducing the computational overhead of the embedded system, achieving satellite switching tracking time ≤20s, controllable pointing accuracy, and constructing a complete acceleration / deceleration control system without requiring large-scale hardware modifications, making it highly practical for engineering applications.

The application discloses a server system applied to the technical field of hardware architecture, and comprises a bottom plate for connecting mainboards, N mainboards connected with the bottom plate, and one CPU arranged on each mainboard; N is a positive integer not less than 2; when the server system is a full-interconnected server system, UPI interface modules of the CPUs of the N mainboards are connected into a communication loop through UPI connectors and cables to form N CPU systems; when the server system is a non-interconnected server system, the N mainboards work independently to form N single-path CPU systems. The application can improve the flexibility of the server system, realize flexible partition processing, and enable the N mainboards to form N CPU systems or N single-path CPU systems.

This invention discloses an interval iterative calculation method and a robust scientific device supporting breakthroughs in fundamental mathematics, belonging to the field of fundamental mathematics and scientific computing equipment technology. This method abandons the traditional discrete single-point iterative logic, constructing a dynamic interval iterative benchmark based on the fundamental philosophy of proportion and the unified theory of continuous intervals. Through adaptive step size decay and inverse verification of the fundamental proportion, it achieves extremely accurate calculations without error accumulation. The device includes a continuous interval fundamental definition unit, an adaptive interval iterative calculation unit, a precision self-calibration unit, and a domestically produced hardware architecture. This invention eliminates sampling errors through interval integration and utilizes the golden ratio for interval convergence control, effectively supporting original theoretical breakthroughs in fundamental mathematics. The iterative accuracy is improved by more than 99.9% compared to traditional methods, achieving full-stack domestic independent control, and can be widely applied in high-precision scientific computing, AI large-model inference, and fundamental mathematical verification.