57 results about "Program compilation" patented technology

The invention discloses an RISC-V vector register pressure-oriented dynamic management method and system, and relates to the technical field of computer processor architecture and compiler optimizing.The method comprises the steps that in the program compiling or executing process, the use state of an RISC-V vector register is monitored in real time, and when it is monitored that the vector register pressure exceeds the limit, the RISC-V vector register pressure is monitored; if yes, selecting a target register and triggering a management strategy; identifying a source instruction of a vector value in the target register, executing heavy materialization validity verification, and dividing the vector value into a heavy materialization type and a non-heavy materialization type according to a verification result; according to a division result, dynamically estimating the heavy materialization cost and the register overflow cost; comparing the two types of costs, and if the heavy material cost is higher, deciding to adopt a register overflow strategy and executing the strategy; and if the overflow cost of the register is higher, a decision is made to adopt a heavy matter strategy and is executed. The computing performance of the processor can be improved, and the problem of performance loss caused by high register pressure is solved.

The invention discloses a program compiling device and method, and belongs to the technical field of computers. The device comprises a receiving module used for receiving a log collected by an instrumentation program in the running process of a target program, the instrumentation program is a part of the target program, and the log comprises popularity data of at least one function in the target program; and the compiling module is used for performing biased compiling on the target program based on the popularity data of the at least one function to obtain an updated target program, and the biased compiling comprises compiling of a biased performance optimization operation or compiling of a biased code area compression operation. In this way, the program can be optimized and upgraded better, and user requirements are met.

This application relates to the field of computer technology and discloses a method for exception handling in WebAssembly modules. The method includes: determining an exception operation tag located at the position where an exception operation needs to be performed; obtaining a program to be compiled including the exception operation tag, and compiling the program into a corresponding WebAssembly module; converting the exception operation tag in the WebAssembly module into exception handling mechanism instructions to obtain an optimized WebAssembly module for handling runtime exceptions in the optimized WebAssembly module. This method, through the obtained optimized WebAssembly module, can provide a runtime exception handling mechanism for lower-level structured programming languages, enabling exception capture and handling during the runtime of the structured program. Simultaneously, by adding an exception handling mechanism, the robustness and security of the program at runtime can be improved. This application also discloses another method for exception handling in WebAssembly modules, a device for exception handling in WebAssembly modules, and an electronic device for exception handling in WebAssembly modules.

A program compilation method and apparatus operate by: obtaining a first expression and a second expression of a program, where the first expression and the second expression generate a dependency relationship based on a first variable, and operation types of the first variable in the first expression and the second expression are different, and updating an operation type of the first variable; so that the first variable has no differential result or a result is zero after encountering a differential operation; separately processing the first expression and the second expression according to the updated operation type of the first variable, to obtain a corresponding derivative function expression; and; combining, based on a chain rule, derivative function expressions respectively corresponding to the first expression and the second expression, to obtain a compilation result of the program.

The embodiment of the present application provides a program compiling and loading method. In the embodiment of the present application, when an application program is compiled, on one hand, the code section and the data section of a plurality of object files compiled from application source code are subjected to merging processing to obtain a target code section and a target data section, thereby reducing table header information; on the other hand, only a symbol table corresponding to a relocation table required when the application is loaded is retained, thereby reducing the space consumption of the symbol table; therefore, the size of an executable file of the application generated according to the target code section, the target data section, the relocation table and the symbol table corresponding to the relocation table is reduced, and the memory consumption when the application is loaded is reduced.

The invention provides a program compiling method. The program compiling method comprises the steps that a P4 program is converted into a first control flow diagram; edges in the first control flow graph comprise control edges for representing control relations, and node attributes in the first control flow graph comprise definition variables and use variables; according to a matching relationship between the definition variable and the use variable, constructing a data dependence edge in the first control flow diagram to obtain a second control flow diagram; and converting the second control flow graph into a program corresponding to the target compiling language according to a translation rule, a control edge and a data dependence edge between the elements of the P4 language and the corresponding elements of the target language. The disclosure also provides an electronic device and a computer program product.

The application provides a program compiling method and device, equipment and storage medium, and relates to the field of computers. The method comprises the following steps: compiling a host, generating a host program package, and including a manifest file of the host in the host program package; obtaining a manifest file and plug-in information of a target plug-in, the target plug-in being a plug-in obtained after compiling a program package; verifying the host and the target plug-in according to preset conditions according to the plug-in information, and determining whether the host and the target plug-in conflict; if the host and the target plug-in do not conflict, merging the manifest files of the host and the target plug-in, generating a total manifest file, and replacing the manifest file in the host program package with the total manifest file; and integrating the plug-in information into the host program package. The method can realize independent development and compilation of the plug-in and the host, decouples the plug-in and the host, and the plug-in can be applied to any host.

The invention discloses a front end side JS code intelligent compiling method and device and a medium, and relates to the technical field of computer program compilation, the method comprises the following steps: parsing a target function corresponding to a service request, and obtaining a plurality of to-be-compiled code blocks according to a pre-constructed code splitting index; the method comprises the following steps: acquiring runtime environment data of a client in real time, and generating compiling priority information; generating a compiling instruction sequence according to the compiling priority information through a preset compiling scheduler; performing real-time compiling through an end side compiling engine to generate a corresponding executable code; when it is detected that the source code of any to-be-compiled code block is changed, determining a change influence range; and performing incremental compiling on the recompiled atomic code blocks in the change influence range to generate corresponding new executable codes. Through end-side on-demand compilation and change of an influence range tracking mechanism, dynamic on-demand compilation and accurate incremental updating of front-end JS codes are realized, and the application loading efficiency and the resource utilization rate are remarkably improved.

The application discloses a high-precision flow control protocol simulation system and method for large-scale networks, and relates to the field of network operation simulation services.In the system, a user flow control protocol integration module automatically converts a congestion control protocol algorithm or a flow control protocol provided by a user into a BPF program; a congestion control protocol simulation module compiles the BPF program into bytecode capable of being run by a Linux kernel and mounts the bytecode at a hook function.A flow generator generates flow by using the mounted congestion control algorithm or flow control protocol; a data collection and processing module collects and processes the flow of the flow control protocol simulation experiment by using a database; and an experimental network topology management tool generates a network topology and performs a simulation experiment based on the flow generated by the flow generator.The application can reduce simulation overhead, completely and truly reflect complex conditions in an actual network, and thus does not limit the applicability and authenticity of simulation results.

The invention provides a CUDA (Compute Unified Device Architecture) source program compiling method and related equipment based on a universal compiler, and the method comprises the following steps: executing preprocessing operation on source codes of a CUDA source program, and respectively generating a first intermediate file and a second intermediate file; scanning a host side code in the first intermediate file to identify a target function identifier representing equipment side execution semantics, and executing a reconstruction operation on a function containing the target function identifier to generate a proxy function used for triggering equipment side execution; scanning a device side code in the second intermediate file to identify a target function identifier, and performing semantic removal processing on the target function identifier to generate a device side executable function code; generating a host side target file, generating a device side target file, and further generating a device side dynamic link file; and forming a target file. By the adoption of the scheme, the CUDA program can be converted into the target program capable of running on the CPU, and the running environment construction cost is reduced.

The application provides an interpreter of a reconfigurable cryptographic algorithm based on a customized high-level C language, and belongs to the technical field of information security. The interpreter comprises an input program of a cryptographic algorithm customization language, a compiling optimization module, a generation module of an intermediate file and a data flow graph, a mapping module and an array generation configuration code module. The application provides an automatic mapping tool for a reconfigurable processor, which can take the customized high-level C language as input. The interpreter arranges and connects computing units such as operators according to the program setting mode, so as to complete the mapping of the whole computing function. This mode can not only shorten the development cycle of the reconfigurable system, but also reduce the need for the user's hardware mastering degree, so that the computing function units of each part are mapped to the reconfigurable processor in a more optimized mode, and the performance of the reconfigurable processor is further effectively improved.

This application relates to the field of computer technology, and in particular to a compilation method, electronic device, and medium for masked vector instructions. The method is applied to an electronic device equipped with a compiler; and the method includes: the compiler acquiring a program to be compiled; the compiler determining that the program to be compiled includes first program code, and that the code form of the first program code conforms to the form of a preset conditional operator expression; the compiler generating a first vector instruction based on a first mask and a vector operation expression of the first program code; and the compiler determining that the operation mode of the first program code is a zeroing mode, then generating a second vector instruction. The compilation method for masked vector instructions provided in this application eliminates the need for users to remember and call built-in interfaces related to operation modes during programming, improving the versatility of program code and ease of use, and increasing programming efficiency.

The present application relates to the technical field of software compiling installation, and provides a kind of many-core hybrid compiling method and system, comprising: obtaining the source program after function insertion of the first principle software is inserted;Compiling the source program inserted, and the master-slave core intermediate function and slave core function written, and the target program file generated after the source program is compiled, the master-slave core intermediate function target program file and the slave core function target program file are linked into executable program;And the call logic between source program, master-slave core intermediate function and slave core function is specified.The first principle software can be run on slave core to exert the computing power of slave core, and the problem of hybrid compiling, incremental compiling of first principle software programming language and many-core programming language is solved.

A computer-implemented technique for compiling program code includes receiving first program code, generating a first dependence graph based on the first program code, removing one or more parallel loops in the first dependence graph to generate a second dependence graph, removing one or more copy operations from the second dependence graph to generate a third dependence graph, allocating memory to one or more data objects in the third dependence graph, assigning one or more sub-graphs of the third dependence graph to one or more corresponding warps, and generating second program code based on the one or more sub-graphs of the third dependence graph.

The invention relates to the technical field of multi-party cooperative work, in particular to a multi-party cooperative process control and guidance method and device, and the method comprises the steps: compiling a script file for describing a target complex task according to a preset description model of the multi-party cooperative process; performing interpretation, task process visualization, state updating and task sequence control on the script file by utilizing a multi-party collaborative process control and guidance tool; based on a data transponder mechanism, task commands and variable settings are sent to multiple parties in related directions according to a multi-party collaborative process control and guidance tool and received collaborative requests of all parties, so that the state is updated, task progress is coordinated, and multiple parties are guided to collaboratively complete a target complex task. Therefore, the problems that an existing multi-party cooperative working method lacks real-time guidance and control on the cooperative process, has high requirements on program understanding, manual coordination and recording, is affected by programming quality and the like are solved.

The invention provides a ZYNQ chip solidification program verification method and system and a readable storage medium, and relates to the technical field of chip program verification. According to the method, by fully utilizing the program compiling characteristic of the chip solidification program and the characteristic that the program and the overall state of related program codes can be represented, only the actual program and value associated with the processor system are measured and calculated for the currently loaded chip solidification program after the ZYNQ chip is powered on; according to the method, information matching verification is carried out on an original processor system program and a value of a recorded solidification program version, and the whole chip solidification program does not need to be subjected to overall program and measurement and calculation by consuming more initialization time, so that the product initialization time is saved, the verification result of the corresponding solidification program is ensured to have relatively high reliability, and the verification efficiency is improved. Product research and development personnel or delivered product auditing personnel can conveniently and quickly confirm the correctness condition of the current chip solidification program and the adaptation condition between the current chip solidification program and the recorded solidification program version number.

The invention relates to the technical field of industrial control, in particular to a program robustness test method, a computer readable storage medium and a program product.The method comprises the steps that a target program is compiled in multiple compiling modes, and program files of multiple versions are obtained; acquiring operation data of the PLC equipment when the PLC equipment operates the program file of each version; and determining the robustness of the target program according to the running data. The invention provides a program robustness test method based on multi-core execution and compilation optimization, which comprises the following steps: using different execution core numbers and compilation options in a program compilation stage, programming compiled programs into PLCs (Programmable Logic Controller) of the same type and the same batch, and monitoring the running states of the PLCs under different working conditions by using a test instrument, so as to test the robustness of the PLCs. And through KPI waveform clustering analysis, potential problems of the program are identified and positioned, and the method has important significance for guaranteeing stable operation of the PLC control system under various complex working conditions.

The invention discloses a register allocation method and device, a computer program product and a readable storage medium, belongs to the field of program compiling, is used for allocating registers for variables during program compiling, and solves the problem that registers cannot be allocated to a large number of variables in a program. Considering that if a node of which the degree is greater than the total number of registers exists in the conflict graph, part of neighbor nodes of the node need to be overflowed to a memory; the neighborhood node area (the node and the adjacent nodes thereof) of one node has divisibility; the method comprises the following steps: determining a target node of which the degree is greater than the total number of registers in a conflict graph, dividing a neighborhood node region of the target node into a plurality of node sub-regions, and meeting the following conditions: each node sub-region comprises the target node, and the degree of the target node in the node sub-region is less than the total number of registers; therefore, the situation that part of neighbor nodes of the target node cannot be allocated to the register and are overflowed to the memory is avoided, and the running efficiency of the executable program obtained through final compiling can be improved.

The embodiment of the invention provides a compiling optimization method and device and related equipment, and the method comprises the steps: in a program compiling process, based on a loop nested structure of a program, determining a write operation statement meeting a non-temporary storage condition, and marking non-temporary storage; aligning the write operation statements marked with non-temporary storage according to the vector width; cancelling the non-temporary storage mark of the write operation statement, traversing the intermediate representation of the program, determining the write operation statement meeting the non-temporary storage condition again, and marking the target non-temporary storage; and according to the write operation statement marked with the target non-temporary storage, a vector non-temporary storage instruction is generated, so that cache pollution is reduced, and the memory bandwidth utilization rate is improved.

The application discloses a crosstalk-aware quantum program compiling framework system, which comprises a parameter optimization module, a crosstalk-aware mapping module and a quantum logic gate scheduling module which are connected in communication, wherein the parameter optimization module is used for optimizing the parameters of quantum logic gates in a quantum program to be executed, the crosstalk-aware mapping module is used for receiving the parameter optimization result of the parameter optimization module, determining an optimal mapping scheme of the quantum program to be executed by constructing a cost function, and the quantum logic gate scheduling module is used for determining the maximum independent set between quantum bits in the quantum program to be executed and a parallel quantum logic gate scheduling scheme of the maximum independent set according to the optimal mapping scheme, so as to realize the compilation of the quantum program to be executed. Through the crosstalk-aware quantum program compiling framework system, the crosstalk noise is perceived, and the quantum circuit mapping scheme is comprehensively optimized, so that the quantum program compiling process is accurate and efficient.

This disclosure provides a multi-tasking program compilation method and apparatus, and a multi-core chip. The method includes: determining the initial synchronization instruction insertion point for each task; generating initial program segments within each synchronization segment corresponding to each initial synchronization instruction insertion point; calculating the program storage area required for each initial program segment; reallocating all initial program segments among the computing cores of a computing core group based on the required program storage area size for each initial program segment, so that the occupied space of each computing core is balanced after reallocation; generating new program segments and final synchronization instruction insertion points for each computing core based on the reallocation result; and inserting synchronization instructions into the corresponding new program segments according to each final synchronization instruction insertion point to generate the final program segments of the computing core group. Multiple tasks can run in the same computing core group, which can save the number of chips in a multi-tasking system and reduce costs.

The application relates to the computer technical field, in particular to a compiling method for register overflow, an electronic device and a medium. The method is applied to the electronic device, and the method comprises the following steps: a compiler acquires a program to be compiled; the compiler compiles the program to be compiled to obtain an execution instruction; wherein the compiling of the program to be compiled by the compiler comprises the following steps: in response to register overflow of a first variable corresponding to a first register included in the program to be compiled, a variable part overflowing from the first register is allocated to a first storage unit corresponding to the first register; in response to register overflow of a second variable corresponding to a second register included in the program to be compiled, a variable part overflowing from the second register is allocated to a second storage unit corresponding to the second register. The method provided in the application can reduce time consumption caused by register overflow and improve program performance.

The invention relates to the technical field of data governance and data elementalization, and discloses a multi-modal data scene compiling method and system based on a meta-part architecture. The method comprises the steps of 1, business scene registration and demand analysis; step 2, carrying out collaborative analysis on multi-modal data; step 3, formulating a part-oriented hybrid compiling strategy; 4, performing parallel collaborative compiling execution; 5, unified packaging and cross validation are carried out; step 6, data part registration and state synchronization; according to the method, meta-parts are introduced as basic elements of data parts, and a double-layer data element model is constructed, so that the data management granularity is finer, the multiplexing mode is more flexible, the packaged data parts can be directly used, the core thought in the program compiling field is creatively introduced into the data element field, and the data element model is more flexible. The method aims to compile original and heterogeneous multi-modal data into standardized, reusable and circulatory data parts.

The application relates to the technical field of industrial automation control, in particular to a control program compiling method, an electronic device and a storage medium. According to the control program compiling method, a ladder program to be compiled is acquired first; the ladder program contains multiple types of element representation graphs; a structural analysis is performed on the logical connection relationship between the element representation graphs in the ladder program, so that tree program structure data is obtained; a program instruction mapping operation is performed based on the tree program structure data, so that multiple program assembly codes corresponding to the tree program structure data are obtained; and the multiple program assembly codes are translated and interpreted, so that a binary executable program is obtained. In this way, the operation efficiency, real-time performance and compilation process can be improved in the process of industrial automation control.

The application discloses a register allocation method, device, computer program product and readable storage medium, belongs to the field of program compilation, and is used for allocating registers for variables during program compilation, and solves the problem that a large number of variables in a program cannot be allocated registers; considering that if there is a node with a degree greater than the total number of registers in a conflict graph, part of neighbor nodes of the node need to be overflowed to a memory; and a neighbor node area (a node and adjacent nodes) of a node has divisibility; the application determines a target node with a degree greater than the total number of registers in the conflict graph, divides the neighbor node area of the target node into a plurality of node sub-areas, and meets that the node sub-areas all include the target node, and the degree of the target node in the node sub-areas is less than the total number of registers, so that part of neighbor nodes of the target node cannot be allocated to registers and are overflowed to the memory, and the running efficiency of an executable program obtained through final compilation is improved.

The application program compiling method comprises the steps that in response to a first installation operation on a first target application, the electronic equipment installs the first target application through a first compiling mode under the conditions that the first target application is not a long keep-alive application and the load state is a high load; the first compiling mode does not execute compiling optimization; and after the first target application is installed, if the load state is changed from the high load state to the low load state, the electronic equipment compiles and optimizes the first target application in a second compiling mode. The embodiment of the invention can be used for avoiding overload operation of the equipment and ensuring the operation efficiency of the first application.

The invention discloses a hot patch file generation method and device of an application program, equipment and a medium, and belongs to the technical field of software development. Acquiring a software source code packet and a patch source code file of the application program; the software source code packet comprises a construction description file of the application program; generating a patch code position table according to the patch source code file; determining a compiling framework type of the application program according to the construction description file, and determining an instrumentation program corresponding to the application program according to the compiling framework type; compiling an instrumentation program corresponding to the application program, and generating an intermediate temporary file according to a compiling path of the instrumentation program and the patch code position table; after the instrumentation program is compiled, generating a hot patch file of the application program according to the intermediate temporary file; after the security vulnerability is found, the hot patch file can be quickly generated based on the patch source code, the whole application program does not need to be recompiled or the service does not need to be restarted, the vulnerability exposure window period is effectively shortened, and the system security and the service continuity are improved.

The present disclosure provides a multi-task program compiling method and device, and a multi-core chip. The method comprises: determining an initial synchronization instruction insertion point of each task respectively; generating an initial program segment in each synchronization segment corresponding to each initial synchronization instruction insertion point respectively; calculating the required calculation amount of each initial program segment respectively; re-distributing all initial program segments in each calculation core of the calculation core group according to the required calculation amount of each initial program segment, so that each calculation core performs the same calculation amount; generating a new program segment and a final synchronization instruction insertion point of each calculation core based on the re-distribution result; and inserting a synchronization instruction in the corresponding new program segment according to each final synchronization instruction insertion point to generate a final program segment of the calculation core group. The present disclosure can save the number of chips in the multi-task system, reduce the cost, optimize the computing power resources, maximize the effective computing power of each calculation core, speed up the task completion, save the power consumption, and greatly reduce the programming difficulty.

The invention relates to the technical field of real-time systems, in particular to a WCET estimation method based on model detection. Comprising the following steps: compiling a C source program into an executable file of a corresponding target architecture; calculating the running time of each basic block in the executable code, and performing static analysis by using a time measurement tool Bound-T; mapping the source code and the corresponding machine code, and marking the running time information of the basic block into the source code; the source code is simplified, and code segments irrelevant to time measurement are trimmed; the CBMC tool is operated, and the WCET of the program is searched; verifying whether the WCET meets the precision requirement of the system, and outputting a result if the WCET meets the precision requirement of the system; otherwise, the analysis option is adjusted, and the CBMC tool is operated again until the WCET meeting the precision requirement is obtained. According to the technical scheme, the efficiency and accuracy of WCET estimation can be improved.

A system for computer security includes a signature of a signed library embedded in a program along with a set of transformations that were made during compiling and linking of the program. Computer security software periodically runs and opens the program (all programs) and when the program includes transformations, the computer security software rolls back the transformations to create a copy of the program then the computer security software calculates a check value on the copy and if the check value matches the signature, the program is allowed, otherwise the libraries / program has been compromised and the program is blocked and quarantined.