1719 results about "Embedded processing" patented technology

An embedded user interface incorporated into a gaming device, the gaming device including a gaming presentation of a base game and a gaming processor for controlling the base game. The embedded user interface includes: a player tracking interface and an embedded processor. The player tracking interface includes (or is associated with) a display screen and enables display of a system game to a user, presentation of information to the user, and reception of information from the user. The embedded processor employs an internal operating system and communicates with the gaming processor, enables control of the system game, control of player tracking information, and control of non-gaming information. In one embodiment, the embedded user interface enables control of a system game of which at least a portion of the system game is presented physically external to the embedded user interface. In another embodiment, the embedded user interface enables control of a system gaming indicator that is physically external to the embedded user interface. In still another embodiment, communication between a game processor and an embedded user interface is only enabled through the gaming network and is not direct enabled via a direct connection.

An apparent network interface permits one processor such as a processor embedded within a larger processing system (an embedded processor) to communicate to a host processor or other processors and devices on the network to which the embedded processor is attached, using standard network communication mechanisms/protocols such as TCP/IP, NFS, FTP, HTTP, etc. The web server protocol HTTP is particularly useful because it permits the embedded computer to publish a user interface for remote monitoring and remote control using a standard web browser application. The invention provides the host computer with an apparent network interface that appears to be a standard network device, such as an Ethernet interface card. This apparent interface communicates directly with the embedded processor, which appears to be a device on this apparent network. Significant cost savings and performance enhancements are realized by implementing the communication directly over the host computer's peripheral bus rather than using standard network hardware such as Ethernet hardware.

A service management system for devices with embedded processor systems manages use of memory by programs implementing the services by assigning services to classes and limiting the number of services per class that can be loaded into memory. Classes enable achieving predictable and stable system behavior, defining the services and service classes in a manifest that is downloaded to embedded devices operating on a network, such as a cable or satellite television network, telephone or computer network, and permit a system operator, administrator, or manager to manage the operation of the embedded devices while deploying new services implemented with applications downloaded from the network when the service is requested by a user.

A reconfigurable test system including a host computer coupled to a reconfigurable test instrument. The reconfigurable test instrument includes reconfigurable hardware-i.e. a reconfigurable hardware module with one or more programmable elements such as Field Programmable Gate Arrays for realizing an arbitrary hardware architecture and a reconfigurable front end with programmable transceivers for interfacing with any desired physical medium-and optionally, an embedded processor. A user specifies system features with a software configuration utility which directs a component selector to select a set of software modules and hardware configuration files from a series of libraries. The modules are embedded in a host software driver or downloaded for execution on the embedded CPU. The configuration files are downloaded to the reconfigurable hardware. The entire selection process is performed in real-time and can be changed whenever the user deems necessary. Alternatively, the user may create a graphical program in a graphical programming environment and compile the program into various software modules and configuration files for host execution, embedded processor execution, or programming the reconfigurable hardware.

A hardware virtual machine instruction processor directly executes virtual machine instructions that are processor architecture independent. The hardware processor has high performance; is low cost; and exhibits low power consumption. The hardware processor is well suited for portable applications. These applications include, for example, an Internet chip for network appliances, a cellular telephone processor, other telecommunications integrated circuits, or other low-power, low-cost applications such as embedded processors, and portable devices.

A programmable logic integrated circuit has an embedded processor with a watchdog timer circuit. The watchdog timer circuit is used to detect software or hardware failures. In one implementation, the watchdog timer circuit includes a counter register that advances (e.g., incremented or decremented) with each clock. To prevent the watchdog timer circuit from becoming triggered, the watchdog timer circuit should be reset or reloaded by software. For example, the count register may be reset to a value to start the count over. If the count register is allowed to count to a final or maximum value, the watchdog timer circuit will become triggered, generating a triggered signal that causes the programmable logic integrated circuit to be reset. A reset causes a reloading of the configuration data used to program the programmable logic and embedded processor portions of the integrated data. The configuration data may be stored in an external nonvolatile storage memory.

First (embedded) and second (non-embedded) processors are energized by an energy source in a hand-held device. The second processor performs functions requiring more power than those performed by the first processor. The second processor is normally asleep and is awakened by the first processor and is empowered, when awakened, to perform functions. Only the portions of the second processor required to perform these functions are activated. Protocols for functions to be performed by the second processor are provided initially to the second processor and are processed in the second processor. They are then transferred to the first processor for storage. When the second processor is activated to perform functions represented by a protocol, the protocol is transferred to the second processor and the functions are performed by the second processor.

A system including at least two processing units embedded on a chip able to communicate with each other and to generally independently control access to data from memory on the chip.

A system and method for enabling multithreading in a embedded processor, invoking zero-time context switching in a multithreading environment, scheduling multiple threads to permit numerous hard-real time and non-real time priority levels, fetching data and instructions from multiple memory blocks in a multithreading environment, and enabling a particular thread to modify the multiple states of the multiple threads in the processor core.

An embedded additional user interface 10 includes a web page display screen 20 and an embedded processor 30, and is incorporated into a gaming machine 40 that in turn includes a gaming screen 50 and a gaming processor 60. The embedded processor 30 employs an internal operating system and communicates with the gaming processor 60. The embedded processor reads incoming data, translates the data into a web authoring language, and maps the data to the web page display screen. The display screen 20 presents web page information to a user via the display screen, thereby increasing user excitement by providing a richer gaming experience. This provides a dramatic improvement over traditional system components 70 (input/output peripherals) that have been used in the past to access service and system information, such as a 2-line, 20-character VF display and a 12-digit keypad.

The invention provides a high speed data storing or reading method and device based on FPGA, the method and device belong to the computer field and the storage field. The device comprises an RAID controller (1), an SATA controller group (2), a multi-port memory controller group (3), an input output module (4), a RocketIO (5), an embedded processor (6), a memory controller module (7), a memory cell _1 (8), a memory cell _2 (9), a disk array (10) and an FPGA loading and configuring module (11). The modules 1-7 are realized in FPGA, and the modules 1-4 are connected with the embedded processor by a PLB bus. The embedded processor is taken as a core processing unit and coordinates and controls the entire system to operate. The device can simultaneously control a plurality of hard disks, and RAID0 and RAID1 can be realized by software configuration. The device is provided with a camlink interface, a PCIE interface and a fiber interface. The device reduces peripheral ASIC chip and PCB area and has the advantages of miniaturization, low power consumption and wide application.

An embodiment of the present invention provides an apparatus, comprising an RFID tag interfaced with the apparatus, the RFID tag enables wireless provisioning and configuration of the apparatus and may be a passive read/write RFID tag. The apparatus may be, in one embodiment, a platform such as a client or server and the passive RFID tag may be interfaced with the platform such that the tag's EEPROM can also be read from or written to by the platform using a wired serial connection. The apparatus may further comprise a host processor with an operating system (OS) and an embedded microcontroller, the embedded microcontroller may have access to dynamic and non-volatile memory capable of operating independently of the host processor and OS and with direct access to a network interface, wherein the RFID tag may be read from or written to by either a RFID reader or the platform via a direct connection to the embedded processor.

Functional testing of an embedded system is performed by a test control system that implements a peripheral emulation module to interface with an externally accessible port of the embedded system. The test control system implements a test generation processor that operates to autonomously resolve abstracted component templates and embedded system description data, specific to the embedded system, to produce a corresponding specific test program. The test control system executes the test program to drive operation of the embedded processor unit to cause transfer of test data through the external interface, which is then autonomously compared to reference data derived through the execution of the test program and specific to the embedded system, whereby the comparison results reflect the correct operation of the embedded system.

A system and method for producing cryptographic keys for use by an embedded processing device within a manufactured product. A pseudo random number generator is seeded with entropy data gathered by the embedded device, and the result is used to generate a public-private key pair. The process can be carried out during manufacturing so that the public key of each manufactured product can be stored in a database along with a unique identifier for the embedded device associated with the key. In one particular example, a vehicle having an installed telematics unit uses the key generating process to self-generate keys using entropy data available to the vehicle.

Architecture for efficient processing of the evolving OTN transmission technology, standardized under ITU-T G.709, in conjunction with existing and emerging SONET/SDH protocol signals, standardized under ANSI T1.105/ITU-T G.707. The new architecture allows processing the SONET/SDH signals, and/or OTN signals, and/or SONET/SDH mapped into OTN signals more efficiently. The architecture further allows processing and multiplexing of lower order signals into a higher order signal such as quad OC-192 into OC-768 or quad OC-192 into OPU3 and OTU3. This architecture uses an embedded processor to process some of the signals' overhead in software, contributing to an additional level of flexibility in the processing. This architecture enables customization and allowing for future standard updates and upgrades. The architecture can be upgraded to SONET OC-3072, SDH STM-1024 and OTU4, which currently are not standardized. The architecture can also be used for the implementation of SONET OC-192 with OTN OTU2.

The invention provides a high-performance low-power-consumption embedded processor based on command dual-transmission, comprising a command fetching unit, a two-way decoding unit, a transmitting unit, a command dispatch execution control unit, a command executing unit and a loading/storing unit; wherein the command fetching unit is used for pre-fetching two commands in a single clock cycle and sending the commands into an assembly line; the two-way decoding unit is used for parallelly decoding the two commands in the single clock cycle; the transmitting unit is used for parallelly transmitting the two commands in the single clock cycle; the command dispatch execution control unit is used for dynamically adjusting the command dispatch according to the computing load and controlling execution according to an out-of-order execution mechanism; the command executing unit is used for computing the results of the commands; and the loading/storing unit is used for ensuring that when the commands are absent, sequent commands can successfully occupy the assembly line and visit the data memory on the disc and the data memory outside the disc. The invention can improve the performance of the embedded processor and reduce the cost under the precondition of low power consumption.

A parallel processing architecture comprising a cluster of embedded processors that share a common code distribution bus. Pages or blocks of code are concurrently loaded into respective program memories of some or all of these processors (typically all processors assigned to a particular task) over the code distribution bus, and are executed in parallel by these processors. A task control processor determines when all of the processors assigned to a particular task have finished executing the current code page, and then loads a new code page (e.g., the next sequential code page within a task) into the program memories of these processors for execution. The processors within the cluster preferably share a common memory (1 per cluster) that is used to receive data inputs from, and to provide data outputs to, a higher level processor. Multiple interconnected clusters may be integrated within a common integrated circuit device.

A microcontroller provides a flexible architecture to readily support both general embedded applications and communications applications. The microcontroller includes an embedded processor, a relatively low-speed general purpose peripheral bus controller, a relatively high-speed peripheral bus host bridge, a primary memory controller, and a secondary memory controller, each coupled to a processor bus. The general purpose peripheral bus controller is coupled to a relatively low-speed general purpose peripheral bus which is coupled to a plurality of integrated general purpose peripherals. The relatively high-speed peripheral bus host bridge is coupled to a relatively high-speed peripheral bus capable of supporting a plurality of communication-oriented peripherals. The secondary memory controller shares an address bus with the general purpose peripheral bus controller and shares a data bus with either the primary memory controller or the general purpose peripheral bus controller. The control timing of the secondary memory controller is independent of the control timing of the general purpose peripheral bus controller. Also, a processor arbiter is coupled to the embedded processor, and a relatively high-speed peripheral bus arbiter is coupled to the peripheral bus host bridge. Aside from the microcontroller, an embedded system can include a relatively low-speed general purpose peripheral bus and a relatively high-speed peripheral bus, both external to the microcontroller. The external relatively lowspeed general purpose bus can be coupled to the relatively low-speed general purpose peripheral bus controller, and the external relatively high-speed peripheral bus can be coupled to the relatively high-speed peripheral bus host bridge.

A combination EEPROM, NOR-type Flash and NAND-type Flash nonvolatile memory contains memory cells in which a floating gate transistor forms a NAND-type Flash nonvolatile memory cell, forms a NOR-type Flash nonvolatile memory cells and with one or two select transistors forms a two and three transistor EEPROM cell. The nonvolatile memory cells use a large positive programming voltage (+18V) applied to the word lines or select gating lines for programming the memory cells and a large negative erasing voltage (−18V) applied to the word lines or select gating lines for erasing the memory cells. The NOR-type Flash nonvolatile memory array is used to store code of embedded processor programs or application programs for smart cards. The EEPROM array is preferably used to store byte alterable data and NAND-type Flash nonvolatile memory array is used to store personalized biometric data such as Iris, DNA, facial picture and finger prints.