575 results about "Multithreading" patented technology

The invention relates to the technical field of computer video processing, and discloses a low-delay video stream real-time processing method and device, and the method comprises the steps: obtaining original video stream data, and processing the original video stream data through employing a lightweight motion prediction method; processing the macro block data set and the predicted coding configuration parameter by adopting multi-thread assembly line coding to obtain a coded data block; establishing a data transmission mechanism to perform data flow control on the unified memory access interface; a heterogeneous task scheduling strategy is adopted to distribute task division results; a lightweight neural network is adopted to carry out parameter adaptive adjustment, and an optimized video stream processing result is obtained; according to the method, a zero-copy data transmission technology is adopted, and optimal configuration and efficient utilization of computing resources are achieved.

The invention relates to the technical field of intelligent monitoring, in particular to a multi-thread low-power-consumption intelligent monitoring system based on an AI processor. The method has the advantages that aiming at the problems of unbalanced computing power and power consumption, high multi-task processing delay and strong hardware dependence in the prior art, the NPU module of the RK3588 processor is combined with the INT8 quantitative model, so that the power consumption is lower than 10W under the 6TOPS computing power; a dynamic multi-thread scheduling mechanism is designed, parallel processing of more than eight paths of video streams is supported through binding of a priority queue and an NPU core, and end-to-end delay is compressed to be within 200 ms; a zero-copy video stream architecture is constructed, data transfer is eliminated through memory mapping, and preprocessing time consumption is reduced by 90%; an energy efficiency control module is integrated, the NPU voltage frequency is dynamically adjusted according to the load, and the energy efficiency ratio reaches 0.83 TOPS / W; space-time alignment of multi-model reasoning results is realized by adopting a frame ID synchronization technology, and the mismatching rate is lower than 0.1%.

The invention relates to the technical field of enterprise data management, in particular to a lightweight-based enterprise data dynamic integrated management system, which is characterized in that an acquisition module is used for deploying edge computing nodes, receiving multi-source heterogeneous information streams from manufacturing execution systems and equipment logs, dynamically analyzing and standardizing the information streams, and adding metadata tags; uploading is carried out in a batch processing mode; the map construction module is used for constructing a semiconductor blood relationship map by taking the standardized key information as a blood relationship clue; a graph database is used for efficient storage, and a RESTful API interface is configured to support batch import, so that data storage and relevance expression are more flexible and efficient; the prediction module performs reasoning on the atlas by adopting a graph neural network to generate predictive risk distribution, and a correlation analysis set generated by the prediction module is stored back to the atlas in a structured manner; by introducing a multi-thread concurrent write-in and lock mechanism, the atlas supports complex combination query based on a Cypher query language, and supports multi-level and traceability query.

The invention discloses a cross-system full-link metadata processing method and device.According to the method, a separated metadata storage architecture is adopted, entity attributes are stored in a JSON document form, relationships between entities are stored in an independent relationship table in a quintuple structure, and efficient storage and rapid query are achieved; through a topology driving processing framework, depth-first traversal is carried out based on a hierarchical structure of a directed acyclic graph, and multi-thread concurrent processing is started at a mode level, so that the processing efficiency of large-scale heterogeneous metadata is improved; the entity life cycle event scheduler is used for monitoring entity change events, triggering index updating, relation maintenance and other operations, and real-time response of metadata change is ensured. Meanwhile, in combination with a search index synchronization mechanism, a hierarchical entity association model, a connector abstraction factory and a fingerprint cache optimization mechanism, efficient management, real-time synchronization and deep association analysis of cross-system metadata are realized. According to the method, the storage efficiency, the real-time performance, the concurrent processing capability and the expansibility are remarkably improved.

The invention relates to the technical field of message pushing, in particular to an SaaS (Software as a Service) intelligent concurrent pushing system which comprises a tenant flow monitoring module, a resource binding module, a lock-free object writing module, a handle layout construction module and a cache prefetching delivery module. According to the method, the high-frequency business object is identified by monitoring the flow characteristics of the tenants, and the complete Slab page is dynamically applied and bound to the thread exclusive local allocation buffer area, so that physical isolation of bottom layer resources is realized to eliminate global lock competition and context switching overhead in a multi-thread environment; lock-free memory writing is executed based on a privatized pointer, the object construction efficiency is greatly improved, a compact storage structure in which a bitmap is adjacent to a connection handle is constructed, a hardware cache prefetching mechanism is triggered by utilizing bitmap reading, connection data is loaded to a CPU cache line in advance, and the connection data is stored in the cache line. And the cache miss rate is reduced and the concurrent delivery performance of massive messages is remarkably improved by utilizing a memory locality principle.

The invention relates to a distributed storage access method initiated by a GPU (Graphics Processing Unit) in an AI (Artificial Intelligence) scene. The method comprises the following steps: S100: constructing a software cache module and an I / O (Input / Output) queue module in a GPU memory; s200, the GPU thread queries the target data through the software cache module, reads the target data if the target data is hit, and enters the next step if the target data is not hit; s300, when the I / O request is not hit, the repeated I / O requests initiated by multiple threads are automatically combined to generate a single effective I / O request, and the request is written into an I / O queue module; s400, the user mode distributed storage client monitors the written submission queue, reads the target data and then transmits the target data to the software cache module, and a completion queue of the I / O queue module is updated; and S500, the GPU thread polls the updated completion queue, and updates the reference count of the software cache module after reading the data. The main purpose of the invention is to realize high-throughput and low-delay data transmission without the participation of a CPU (Central Processing Unit).

The invention provides a cross-platform video decoding method and device, computing equipment and a computer readable storage medium, and the method is combined with a factory mode to completely package bottom layer differences of all platform types, and an application layer developer does not need to care about the bottom layer platform differences. The optimal implementation can be automatically selected on different engines and platforms through a uniform API (Application Program Interface); during rendering, a single-frame memory management strategy is used, and only one frame which is currently displayed is reserved in a memory; and in the aspect of performance, the advantages of a multi-thread platform and the parallel computing characteristics of the GPU are fully utilized. According to the embodiment of the invention, through deep fusion of a cross-platform soft decoding architecture, single-frame memory optimization, multi-thread parallel, GPU acceleration and other technologies, perfect balance of cross-platform, high performance and low memory is realized, and the development efficiency of the whole project is improved.

The invention discloses a dual-channel adaptive network stability testing method and system, and belongs to the technical field of computer network testing. The system adopts a dual-channel asynchronous communication architecture in which a control channel and a data channel are physically separated, instructions and state information are transmitted through an independent TCP control channel, and high-speed test data streams are transmitted through a UDP or TCP data channel. The method comprises the following steps: dynamically and adaptively adjusting a timeout parameter based on real-time network delay detection; nanosecond constant interval packet sending control is realized by using a high-precision monotonic clock source and busy waiting compensation mechanism; a packet loss detection, positioning and ACK confirmation mechanism based on the serial number is realized in an application layer; and real-time statistical display and idle detection automatic termination are realized through multi-thread parallel processing. According to the invention, the precision, the stability and the adaptive capability of network testing are remarkably improved, and the method is suitable for long-time stability testing in various scenes such as a high-speed Ethernet, a satellite link, an industrial Internet of Things gateway and the like.

The invention provides an instruction-level simulation and performance modeling system for a parallel computing architecture, and belongs to the technical field of computer architecture and simulation verification, and the system comprises an instruction modeling layer which is used for analyzing and executing an intermediate instruction set defined by the architecture; the scheduling execution layer is used for simulating a multi-thread and multi-core parallel execution process; the storage access layer is used for constructing a hierarchical storage access and bandwidth and delay model; and the performance analysis layer is used for collecting and counting key indexes such as an execution period, an instruction utilization rate and memory access delay, and realizing accurate performance modeling of the parallel architecture. According to the method, the performance bottleneck of the design scheme can be rapidly evaluated in the early stage of architecture design, the simulation speed is high, the module configurability is high, the modeling precision is adjustable, and the method is suitable for functional verification, micro-architecture exploration and compiler performance analysis of parallel computing architectures, accelerator chips, heterogeneous multi-core processors and the like.

The invention provides a semiconductor SPC system data multi-thread rendering display device and method, and belongs to the field of semiconductor manufacturing, and the method specifically comprises the steps: obtaining sampling point data; displaying an interactive interface of the interactive operation to enable a user to select to-be-displayed interface content, and determining a rendering task according to the business operation corresponding to the selected interface content; performing service calculation on the sampling point data by adopting a multi-task concurrent mode, and outputting a task processing result; based on the data volume of the sampling point data and the business operation corresponding to the selected interface content, determining a rendering mode of the task processing result, and generating a to-be-rendered result; decomposing the rendering task into a plurality of stage tasks of framing rendering based on the to-be-rendered result; and performing framing rendering on a task processing result according to the stage task, and displaying a rendered page. By means of the processing scheme, the mass semiconductor production data can be dynamically rendered, and efficient self-adaptive display of the mass semiconductor monitoring data is achieved.

The invention discloses a mainboard function automatic detection method and device, and relates to the technical field of computer hardware detection. The method comprises: receiving a user instruction through a graphical interface to generate a test queue; distributing an independent thread for each test item to execute hardware detection, and dynamically mapping the position of a physical port; analyzing a test state in real time and updating interface feedback; comparing the actual hardware parameters with preset parameters; and hot update of the test script is supported. The device comprises a graphical interface module, a multi-thread execution engine, a scripted hardware detection module and the like. The mainboard function detection device can perform efficient, automatic and visual detection on the mainboard function, and is suitable for quality control of mainboard production, maintenance and research and development links.

The invention provides a database concurrency control and memory access optimization method which can be applied to the technical field of computer system software performance optimization. According to the method, multi-level instruction-level reconstruction is carried out on an execution path of a database kernel through the characteristics of an underlying hardware instruction set of a collaborative application processor platform, and the method comprises the following collaborative implementation optimization dimensions: based on a register file and a cache hierarchical structure of the processor platform, an access mode of a database core data structure is optimized; the number of memory access instructions is reduced; the data locality is improved; on the basis of atomic instruction set extension of a processor platform, instruction-level reconstruction is carried out on key primitives in a database multi-thread synchronization mechanism so as to reduce the overhead and contention of synchronization operation; on the basis of single-instruction multi-data-stream extension of a processor platform and a vector atomic operation instruction of the single-instruction multi-data-stream extension, parallel acceleration is carried out on batch life cycle management operation of objects in a database.

The invention discloses a cryptographic algorithm adaptation and hardware encryption and decryption acceleration method suitable for a gateway protocol, deep integration of a cryptographic algorithm is realized through protocol stack-level native transformation, software and hardware collaborative design is adopted, and through innovative mechanisms such as multi-thread concurrent encryption, asynchronous interrupt processing and DMA data interaction, the hardware encryption and decryption acceleration of the cryptographic algorithm is realized. The processing capability in a high throughput scene is improved; an intelligent strategy engine is introduced to realize data packet dynamic classification and encrypted resource optimization scheduling, and the system performance is maximized while the security is ensured; according to the technical scheme, key full-life-cycle management and control are achieved through the HSM, the requirement for equal insurance 2.0 is met, multi-platform deployment is supported by adopting modular design, and compared with the prior art, the method can be flexibly adapted to various application scenes such as various domestic chip architectures, embedded devices, security gateways and industrial controllers, and the method is suitable for large-scale popularization and application. The problems of high platform dependence, difficulty in transplantation and the like existing in national secret IPSec implementation are solved, and a better secure communication solution is provided for a localized environment.

Apparatuses, systems, and techniques to perform multi-threaded memory allocation in parallel by one or more software programs being performed on a parallel processing unit (PPU), such as a graphics processing unit (GPU), or any other processing unit capable of supporting multi-threaded software execution. In at least one embodiment, one or more software programs expressed in part by code using an application programming interface for parallel computing, such as CUDA, perform allocation, search, and deallocation of memory efficiently and in parallel on a GPU.

The embodiment of the invention provides a big data storage optimization method based on a zero-copy collaboration technology and related equipment, and belongs to the technical field of big data storage. The method comprises a zero-copy data transmission module used for directly writing a data stream into a front-end buffer area of an annular structure through a direct memory access technology, and adopting a zero-copy algorithm based on pointer offset to parallelly separate data of each channel in a multi-thread environment; the intelligent data reduction module is used for deleting duplicated data from the data and then compressing the duplicated data; and the hybrid storage management module is used for managing the hybrid partition storage architecture and dynamically adjusting the distribution of the data in the hybrid partition storage architecture according to the data access mode. The CPU copy frequency is reduced through the zero copy technology, the data transmission efficiency is remarkably improved by combining the data reduction and intelligent layering strategies, the occupied storage space is reduced, and meanwhile the data safety and compliance are guaranteed.

The invention discloses a memory synchronization method and system in a virtualization fault-tolerant environment, and relates to the technical field of data processing. The method comprises the following steps: capturing a memory write-in operation of a main node of a virtual machine, and generating a memory write-in log; dividing the memory write-in log into a plurality of memory data blocks through multi-thread processing; synchronizing the memory data block into the memory of the virtual machine standby node, and maintaining heartbeat detection between the virtual machine master node and the virtual machine standby node; and when detecting that the heartbeat of the main node of the virtual machine is abnormal, triggering the standby node of the virtual machine to carry out rollback takeover by utilizing the synchronous memory data. The technical problems that in the prior art, in the virtualized fault-tolerant environment, the memory data synchronization efficiency of main and standby virtual machines is low, the data consistency guarantee is insufficient, and the main node fault takeover delay is large are solved, and the technical effects that the memory synchronization real-time performance and accuracy are improved, rapid seamless takeover of the standby node is guaranteed, and service continuity is ensured are achieved.

A first set of threads having a same address corresponding to the shared memory is identified from a group of active threads associated with an instruction to update a shared memory. A first thread of the first set of threads is selected. The instruction is executed for the first thread using the same address to access the shared memory. Attempts to execute the instruction for remaining threads of the first set of threads are delayed until after the first thread is executed and until at least one of the remaining threads of the first set of threads is not guaranteed to fail execution of the instruction.

Hardware processor-based data compression includes subdividing source data into a plurality of partitions. A partition size for the subdividing is selected based on a search window size of a compression technique and a cache size of the hardware processor. A number of the plurality of partitions is selected based, at least in part, on a size of the source data and the partition size. Compressed data is generated by the hardware processor by performing multi-threaded compression in which a plurality of threads execute the compression technique on the plurality of partitions in parallel. Some aspects include prepending a random-access point (RAP) metadata frame by multi-threaded compression at a start of the plurality of partitions to enable the multi-threaded and parallel decompression. The RAP metadata frame is interpretable to enable single-threaded decompression by legacy decompressors.

The invention discloses a virtual power plant rapid frequency modulation control system and control method, and the method comprises the steps: adaptively adjusting a sampling period through a dynamic sampling algorithm based on a sliding window variance; low-delay calculation of high-frequency data is realized by adopting a multi-thread queue communication technology; a multi-core ARM processor running a real-time operating system is used for executing a multi-thread control model, and data acquisition, algorithm control, fault diagnosis and communication tasks are processed in parallel; according to the control algorithm, frequency prediction feedforward signals based on an AI model and SOC state feedback are fused, and dynamic optimization of PID parameters is achieved. According to the method, millisecond-level frequency modulation response can be realized, the instruction response delay is less than 80ms, the frequency adjustment error is less than + / -0.01 Hz, the frequency modulation performance of a virtual power plant and the stability of a power grid are remarkably improved, and meanwhile, the service life of energy storage equipment is prolonged through SOC collaborative optimization. The invention aims to solve the problems of slow response and low precision of the existing frequency modulation technology.

The invention provides an RDMA-based big data transmission and storage system and method and a semiconductor detection device.The big data transmission and storage system comprises a hardware layer and a software layer, the hardware layer comprises an NVMe SSD storage array, an NVMe RAID acceleration card based on a GPU architecture and an RDMA network card, and the software layer comprises an NVMe SSD storage array, an NVMe RAID acceleration card based on the GPU architecture and an RDMA network card; the software layer comprises a multi-thread transmission module, a self-adaptive memory pool module, a transmission control module, a data verification and retransmission module, a scheduling and optimizing module and a disk falling and storage management module. According to the method, multi-channel transmission parallelization is achieved through data direct connection, zero copy transmission, RAID acceleration and multi-thread parallel RDMA transmission in a hardware link, data is directly connected and transmitted from a memory to the NVMe SSD storage array, data receiving and disk falling thread decoupling directly access the NVMe SSD storage array through asynchronous writing, network overload or storage blockage is avoided, and the data transmission efficiency is improved. The data transmission efficiency and reliability are high, and popularization and application in scenes needing large-scale image transmission processing such as semiconductor detection are facilitated.

The invention provides a file co-processing method and system based on distributed multithreading and dynamic sub-libraries, and relates to the technical field of file data processing, and the method comprises the steps: obtaining a to-be-processed file, and generating a file list according to batch information; a production-consumer model is adopted, a producer main thread scans a file list, a task queue is generated, a consumer thread pool concurrently executes downloading tasks, and the maximum concurrency number is controlled through semaphore; file data are uniformly distributed to a plurality of physical storage nodes on the basis of a fragment routing algorithm, real-time updating of a mapping relation between fragments and instances is managed by utilizing a dynamic routing table, resources are preferentially allocated to high-priority file tasks on the basis of a service routing strategy, and the tasks are dynamically allocated to specified database fragments; multi-file parallel processing on a processing node is realized through a three-stage parallel model, dynamic Feign calling is carried out on a service instance dynamic route and a weight load, multi-state table state synchronous updating is carried out based on a two-stage state machine, and a processing log is saved.

The invention relates to the technical field of artificial intelligence, and provides an attention mechanism calculation method, electronic equipment and a storage medium, and the method comprises the steps: configuring a plurality of thread beam groups which share the same group of thread local registers; the calculation process of the attention mechanism is divided into a plurality of calculation sub-steps, the calculation sub-steps are distributed to a plurality of thread beam groups respectively, and each thread beam group is configured to execute the corresponding distributed calculation sub-steps; and controlling the plurality of thread bundle groups to execute the plurality of calculation sub-steps in parallel in an assembly line mode through a read-write shared thread local register to obtain a calculation result of the attention mechanism. According to the method, the shared thread local register is utilized to construct a multi-thread bundle group cooperative pipeline calculation mode, efficient copy transmission of data and deep parallelism of different calculation units in the attention mechanism calculation process are achieved, and the method has the advantages of being low in communication overhead, high in hardware resource utilization rate, high in operator execution performance and the like.

The invention discloses a high-concurrency time series data processing method and device for an anti-unmanned aerial vehicle system. According to the method, a lock-free hash table is adopted in a cache space to cache time sequence data, lock overhead is reduced through lock-free cache design and CAS atomic operation, the batch writing throughput is high, the conflict probability is low, multi-thread high-concurrency reading and writing are supported, thread competition and blocking caused by a traditional cache mechanism are thoroughly eliminated, and the concurrent processing capacity is improved; meanwhile, the expenditure of dynamic memory allocation is reduced through batch writing, and the memory utilization rate is increased; through quick positioning of a compound key, priority query of a hotspot data index structure and a lock-free reading mechanism, the query delay of hotspot data is extremely low, the delay of related query in the future is further reduced through a data preloading mechanism, and the real-time response capability is improved; based on a dynamic elimination mechanism of an elimination score, hotspot / recent data can be reserved preferentially, the resource utilization rate is ensured, the cache hit rate is remarkably improved, and the access frequency of the TSDB is greatly reduced.

The invention discloses a medical data increment synchronization method based on an HL7 protocol, and the method comprises the following steps: S1, a hospital internal system sends an HL7 message to a data receiving and processing module, and the data receiving and processing module carries out the following processing. According to the method, data transmission integrity is guaranteed through MLLP packaging verification and CRC verification, multi-message type dynamic analysis and heterogeneous data standardization are achieved through a high-performance HL7 analysis engine, data safety and compliance are guaranteed through TLS / SSL encryption, bidirectional authentication and the like, efficient increment synchronization of ten millions of data is achieved by means of a unique identifier and Redis cache, resource overhead is reduced, and data transmission efficiency is improved. Meanwhile, batch asynchronous processing and multi-thread parallelism are supported, high-concurrency scenes are adapted, analysis rule configuration management is matched, new requirements can be quickly adapted, the maintenance cost is reduced, and the requirements of medical informatization for data synchronization safety, real-time performance, high efficiency and extensibility are comprehensively met.

The invention discloses a metering detection intelligent glasses system integrating artificial intelligence visual identification and a cloud platform, and relates to the technical field of computer software, the metering detection intelligent glasses system comprises an intelligent glasses driving module and adaptive hardware, and has the functions of dynamic scheduling, multi-thread processing, communication self-adaption and non-lagging AR rendering; the AI visual identification module supports batch identification, fine defect detection, off-line operation and incremental learning by using a lightweight model; the cloud platform software framework module adopts a distributed micro-service framework to realize data partition storage, real-time parallel analysis and the like and elastic capacity expansion and contraction; the interaction control module develops a multi-mode program and supports batch instructions and the like; and the system collaboration module realizes multi-module scheduling based on event driving, and ensures efficient collaboration of the whole detection process. According to the method, the precision, efficiency and environmental adaptability of measurement detection are remarkably improved, the batch processing capacity and the network fluctuation coping capacity are greatly enhanced, and efficient and reliable software support is provided for measurement detection.

The invention provides an intelligent equipment control system and method for multi-thread asynchronous communication and self-adaptive analysis. The intelligent equipment control system comprises a hardware layer interface module, a multi-thread asynchronous communication module, a self-adaptive data analysis module, a data processing and storage module and an intelligent diagnosis module. A multi-thread asynchronous communication architecture is constructed through the multi-thread asynchronous communication module to realize concurrent data interaction of multiple intelligent devices, communication protocols of different types of intelligent devices are compatible through the adaptive data analysis module, and an intelligent diagnosis function is integrated. The problems that a traditional upper computer is high in communication delay, poor in protocol compatibility, low in multi-device cooperative control efficiency and the like are solved, the real-time performance and reliability of industrial field device monitoring are improved, and the method is suitable for multi-device cooperative scenes such as intelligent manufacturing and intelligent storage.

According to the IO speed limiting method and device under multiple threads, the electronic equipment and the storage medium provided by the embodiment of the invention, the technology realizes speed limiting of the IO request through a quota isolation and critical point synchronization mechanism, and effectively avoids frequent scrambling of a lock at the same time. The core process of the method comprises the following steps: when a client issues an IO request, reading a current value of a speed limit counter, and calculating an available space in combination with a preset speed limit quota and an instantaneous issuing space; when the request quantity does not exceed the available space, directly releasing the request to disk equipment and updating a statistical value; and if the request quantity exceeds the available space, safely accessing the quota management pool through the thread lock, obtaining a target speed limit quota from the global IO request speed limit quota, and temporarily improving the instantaneous issuing space to process the excess request. According to the design, the threads can operate autonomously within the quota through quota independent distribution, lock competition is not needed, meanwhile, synchronous operation is strictly limited in a critical scene of quota application, the lock scrambling frequency is greatly reduced, and therefore IO performance is remarkably improved.

The invention discloses a secure data transmission method based on multi-thread control, and relates to the technical field of network information security, and the method comprises the following steps: extracting a sensitivity identifier from a data packet header, adopting a lookup algorithm to match a preset sensitivity grading table, dividing data into a high-sensitivity type, a medium-sensitivity type and a low-sensitivity type, determining a priority queue distribution proportion according to the sensitivity, obtaining an initial flow shaping parameter, obtaining current network flow data according to the initial flow shaping parameter, analyzing a preset congestion detection threshold value and a historical transmission record, judging a network congestion degree by adopting a token bucket algorithm, and if the congestion degree is higher than the preset congestion detection threshold value, sending the current network flow data to the priority queue; if yes, the token generation rate of the high-sensitivity data is adjusted, and an adjusted traffic shaping strategy is obtained; according to the secure data transmission method based on multi-thread control, the network transmission efficiency can be effectively improved while the data security is ensured, and the method is particularly suitable for a complex network environment in which data with different sensitivities needs to be processed at the same time.

The embodiment of the invention provides a multi-node parallel acceleration method, device and equipment based on a high-performance computing platform and an RoCE network and a medium, and relates to the technical field of cluster computing, and the method comprises the following steps: constructing a communication stack based on the RoCE network, and realizing an interconnection transmission network between nodes from a sending end to a receiving end; a computing task and a communication transmission task of the high-performance computing platform are executed through a CPU core binding technology of the high-performance computing platform; based on the transparent large page function, processing a memory allocation request initiated by an application program of an operating system and a request of the application program of the operating system for accessing a memory through a virtual address; before a main computing task of the high-performance computing platform starts, pre-processing is executed through multiple threads, open type multi-processing threads are started, the main computing task is executed through the multiple open type multi-processing threads, and a next round of pre-processing task is started in parallel. According to the scheme, parallel acceleration of multiple nodes in cluster calculation is realized.

The present disclosure provides a file execution method and device, wherein the method first detects whether a target code object corresponding to a target file is created in response to an execution instruction for the target file; then, in the case that the target code object is created, the target code object is acquired; finally, an execution container is created under a current thread, and the target code object is executed by using the execution container. The present disclosure creates an execution container under the current thread, executes the target code object directly under the execution container of the current thread, does not need the main thread to allocate tasks, reduces the number of data transmission in the multi-thread concurrent scenario, and reuses the target code object, so that each thread does not need to perform bytecode of the file, and the execution efficiency of the multi-thread concurrent scenario is effectively improved.