27 results about "FLAGS register" patented technology

The invention provides a secure execution environment construction method and system, a chip and a storage medium. The method comprises the following steps: creating an encrypted memory area; distributing an independent security data space in the encrypted memory area for each thread; storing the key encryption key and the security parameter in a locking register, and setting an access control strategy of the locking register by using a flag bit register; and monitoring illegal access to the locked register in real time by using an exception handling instruction. According to the secure execution environment construction method and system, the chip and the storage medium provided by the embodiment of the invention, a reliable hardware-level security mechanism is realized through physical isolation, thread-level encryption container, register locking and the like, and the capability of preventing side channel attacks is improved by introducing random elements of power disturbance according to the security level of the locked register.

The invention discloses an instruction processing method and related equipment, and the instruction processing method comprises the steps: detecting whether a plurality of source flag bit architecture registers of a target instruction are mapped to the same physical register or not in a renaming stage of the target instruction; if the detection result is yes, only one part of information of the source flag bit architecture register and the mapped physical register is stored in the renaming stage, the execution stage and the quit stage of the target instruction respectively, and the target instruction is stored in the execution stage of the target instruction. And according to the stored information of the source flag bit architecture register and the mapped physical register, reading values of the plurality of source flag bits corresponding to the target instruction from the corresponding physical register at one time. According to the technical scheme provided by the embodiment of the invention, when the processor processes the instruction, the storage overhead and the reading overhead of the source flag bit register can be reduced.

The invention discloses a fault-tolerant method for firmware updating, electronic equipment, a storage medium and a program product, when the equipment is started, the state of a flag register is firstly read, if the state of the flag register is a preset first value, old firmware is loaded from a flash memory, and the equipment is started based on the old firmware; wherein the old firmware is firmware applied when the device is successfully started last time, if the state of the flag register is a preset second value, loading new firmware from the storage unit, starting the device by using the new firmware, then obtaining a starting result when the new firmware starts the device, and if the starting result indicates that the device fails to start, starting the device by using the new firmware. The state of the flag register is set to a first value. By adopting the method and the device, when the firmware burning error occurs, the starting path can be switched through the flag register, and the accurate old firmware in the flash memory can be read, so that the normal starting logic can be recovered after the equipment is restarted, the continuous failure of PCIe interface initialization caused by the error firmware is avoided, and the reliability of firmware online updating is improved.

The present disclosure provides a digital shaping filter with a dynamically reconfigurable folding circuit structure and a design method. The digital shaping filter includes: a data redefinition logic unit for performing bit width conversion; a data shift register unit for storing output data of the data redefinition logic unit; a first adder unit for performing addition operations according to the folding circuit structure; an impulse response coefficient register stack unit for writing impulse response coefficients; a reconstruction completion flag register unit for issuing a reconstruction completion signal; a multiplier unit for performing multiplication operations and receiving the output signal of the reconstruction completion flag register unit; a second adder unit for performing addition operations on the output data of the multiplier unit; an order reconstruction register unit for writing the order of the digital shaping filter; a timing control logic unit for selecting result data; and a selection output logic unit for outputting the result data.

A clock stabilization circuit includes a shift register configured to output one or more shifting signals by shifting data and an inversion flag based on a clock signal, a comparison circuit configured to output one or more comparison signals by comparing the one or more shifting signals with one or more keys, respectively, a stable flag register configured to enable a stable flag based on a first-delayed clock signal and the one or more comparison signals, the first-delayed clock signal generated by delaying the clock signal, and a mask circuit configured to output an internal clock signal by masking a second-delayed clock signal based on the stable flag, the second-delayed clock signal generated by delaying the first-delayed clock signal.

The embodiment of the invention discloses an instruction processing method and system, electronic equipment and a storage medium, relates to the technical field of computer processor design, and can save write port resources of a register file. The method comprises the following steps of: analyzing a read-write dependency relationship of each instruction in a current instruction group on a flag bit register so as to establish a flag bit data stream dependency chain; according to the read-write dependency relationship and a preset elimination rule, judging whether each instruction indicating to be written into the flag bit register in the current instruction group needs to be written into the flag bit register or not; and if the judgment result shows that the instructions indicating to be written into the flag bit register in the current instruction group do not need to be written into the flag bit register, canceling the operation of writing the instructions indicating not to be written into the flag bit register back to the flag bit register. The method and the device are suitable for eliminating invalid flag bit registers.

The application discloses an MCM-GPU adaptive last-level cache structure arranged in a GPU module, comprising a Tag Array and a Date Array, wherein the Date Array is used for storing data, and the Tag Array is used for checking whether the data corresponding to an address is in the cache; the application further comprises a local memory access queue used for storing a memory access request of the current GPU module, a remote memory access queue used for storing a memory access request of other GPU modules, an LLC architecture change flag register used for storing an LLC architecture change flag indicating whether the architecture organization mode of the current last-level cache needs to be changed, and an LLC architecture flag register used for storing an LLC architecture flag indicating whether the current last-level cache is switched to a private last-level cache design or a shared last-level cache design. The application can support the dynamic switching of the shared last-level cache and the private last-level cache, can adaptively select the last-level cache architecture organization mode according to the configuration during program running, can meet the program memory access requirement, and can improve the performance of the MCM-GPU.

The purpose is to enhance the enjoyment of the game. [Solution] In a gaming machine, the game control microprocessor comprises a CPU, a program executed by the CPU, a ROM storing information referenced by the program, a RAM capable of storing information updated by the program, a general-purpose register, a data register, and a flag register. The CPU writes first information to the RAM at the start of a variation performance indicating the result of a lottery. When the power to the gaming machine is cut off during the execution of the variation performance and then power is turned on to the gaming machine, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor. When the variation performance resumes after the machine has entered a waiting state for customers, the CPU reads the first information from the RAM and transmits it to the performance control microprocessor.

The present application relates to the technical field of memory, and discloses a method for memory access, including: determining a memory access request to be executed among a number of memory access requests cached in a command pipeline; determining whether a target memory pointed to by a target memory address in the memory access request to be executed is in an idle state; determining whether a programming operation instruction is included in the memory access instruction to be executed; triggering the command pipeline to send the programming operation instruction to the target memory when the target memory is in an idle state and the memory access request to be executed includes a programming operation instruction; determining whether a flag register is included in a preset storage space; triggering the target memory to send an interrupt signal to the CPU corresponding to the memory access to be executed when the flag register is included in the preset storage space. In this way, an interrupt signal can be sent to the corresponding CPU every time a memory access request is issued. The present application also discloses a device, an electronic device and a storage medium for memory access.

The application provides a BMC reset method, a BMC and a BMC reset system. The method comprises the following steps: in response to receiving a reset instruction, resetting a reset flag bit of a reset flag register to zero; performing a logical AND operation on the reset reset flag bit and a target bit of a command register of a PCIe endpoint device to clear the target bit, and the target bit being zero is used to make the PCIe endpoint device intercept a host access request; and in response to completion of the logical AND operation, performing a reset. The application adds a reset flag register, resets a reset flag bit of the reset flag register to zero before resetting the BMC, and performs a logical AND operation on the reset flag bit and a target bit of a command register of a PCIe endpoint device to forcibly clear the target bit, so that all access requests of the host are intercepted during the reset, and problems such as a host read request timeout, a device being mistakenly removed or a system hanging due to BMC memory initialization are avoided, and the stability and reliability of a server system are improved.

The invention discloses an address allocation and memory recovery system, solves the problem that the existing hardware cache management technology needs to consume relatively large storage resources, and belongs to the crossing field of integrated circuit design and data storage technology. Comprising a free space management module used for updating and recording addresses and lengths of all free spaces in the RAM in real time through a register array and an effective marker register; the memory recovery and space merging module is used for driving memory recovery, detecting adjacent free spaces in parallel, merging the adjacent free spaces and the recovery space and managing the address and the length of the corresponding free space by using the free space management module after the data is read out and the space in the RAM is released; and the maximum space matching module is used for carrying out parallel comparison on all free spaces and carrying out address dynamic allocation when a data writing request is received. The method is applied to a high-concurrency cache system.

The present application discloses a memory chip. The memory chip includes a nonvolatile status register and a control circuit. The nonvolatile status register includes a plurality of groups of registers, each group of the registers includes a flag register and at least one data register, the control circuit is connected to the nonvolatile status register, and is configured to control writing times of the nonvolatile status register being greater than erasing times of the nonvolatile status register.

A method includes asserting a field of an event flag mask register configured to inhibit an event handler. The method also includes, responsive to an event that corresponds to the field of the event flag mask register being triggered: asserting a field of an event flag register associated with the event; and based the field in the event flag register being asserted, taking an action by a task being executed by the data processor core.

The application discloses a storage chip, which comprises a non-volatile state register and a control circuit. The non-volatile state register comprises a plurality of register groups, each register group comprising a flag register and at least one register. The control circuit is connected with the non-volatile state register and is used for controlling the number of write operations of the non-volatile state register to be greater than the number of erase operations of the non-volatile state register. Through the control of the control circuit, each register group in the non-volatile state register is controlled to perform at least one write operation and then perform one erase operation, so that the number of write operations of the plurality of register groups is greater than the number of erase operations. In this way, the number of erase operations can be reduced under the condition that the number of write operations is unchanged, and the reliability of the non-volatile state register can be improved.

A computer system and a mode switching method thereof are provided. The computer system includes a processor, a plurality of peripheral components, and a switch. The switch is coupled to the processor via a first transmission interface link and respectively coupled to the plurality of peripheral components via second transmission interface links. The switch includes a first flag register and a second flag register. When a first target peripheral component in the peripheral components is to be entered into a low power consumption mode, the processor sets a low power consumption flag bit corresponding to the first target peripheral component in the first flag register. When a second target peripheral component in the low power consumption mode in the peripheral components transmits a wake-up signal to the switch, the switch sets a wake-up flag bit corresponding to the second target peripheral component in the second flag register.

A processor includes a register file, a context controller that, in response to a target interrupt occurring, is configured to determine, a target register that stores new data acquired through each of commands for executing an interrupt service routine (ISR) among the plurality of registers, a write buffer configured to transmit pre-data stored in the target register to a memory, and a flag register configured to store set data including set values indicating whether the new data is stored in each of the registers. The context controller is configured to determine whether to transfer the pre-data to the memory through the write buffer based on the set data.

The invention discloses a hardware maintenance system and method for sampling message integrity in an airborne network, a sampling message receiving buffer area and a buffer area management register group are connected to a host interface management unit, and an address mark register group is connected to a receiving management unit and a receiving frame counting management unit. The receiving management unit is connected to a sampling message receiving buffer area through a data buffering and shunting controller; the receiving management unit is further connected to the msgID logic position management unit, the frame new / old state management unit and the buffer area effective state management unit, the frame new / old state management unit and the buffer area effective state management unit are connected to the buffer area management register set, and the host interface management unit is connected to the msgID logic position management unit.

The application discloses a first failure determination method, which is suitable for a PLC processor, wherein the PLC processor comprises n fault data storage sub-areas, n fault flag registers and an output state register; the first failure determination method comprises the following steps: acquiring a fault signal and storing fault information corresponding to the fault signal into a target fault data storage sub-area; when a change of the target fault data storage sub-area is monitored, refreshing (n-1) fault flag registers associated with the target fault data storage sub-area, so that the state value of the corresponding fault flag bit is changed; generating a control signal by the output state register according to the state value of each fault flag bit received; comparing the control signal with a preset first failure control signal to determine the first failure. The application is advantageous in improving the fault processing efficiency of after-sales maintenance personnel by determining the first failure.

The invention provides an integrated conditional execution flag register, a computing control method and a processor architecture. A bit width mode control bit, a security policy control bit and a floating point rounding mode control bit are integrated into a single register; when a bit width mode is changed, integrated joint updating of a bit width mode control bit, a security policy control bit and a floating point rounding mode control bit is supported, access delay is eliminated, state atomic updating is realized by utilizing a hardware automatic triggering rule, and control complexity is reduced by adopting operation code direct-writing mapping, so that on the premise that the security is ensured, the control efficiency is improved. A more efficient and more flexible calculation control strategy is realized, and through hardware-level state integration, the risk of software configuration delay and state inconsistency in a traditional scheme is eliminated, so that the processor has higher reliability when facing tasks with mixing precision, high security, floating point density and the like. Execution state management can be completed with fewer clock cycles, lower switching cost and higher strategy consistency.

The invention discloses a master device access method and device for an AXI bus, terminal equipment and a storage medium. The method comprises the steps of obtaining a request ID number sent to the AXI bus by a master device to be accessed; according to the request ID number and a register ID number in an ID register, judging whether an accessed master device exists or not; if not, controlling the to-be-accessed master device to access a first slave device based on the request ID number; wherein the first slave device is a slave device corresponding to the request ID number in a plurality of first candidate slave devices; if yes, controlling the to-be-accessed master device to access a second slave device or a third slave device based on the state of the ID flag register; according to the invention, the access efficiency of the plurality of main devices through the AXI bus is improved.

The invention belongs to the field of chip verification, and relates to a software and verification environment high-speed interaction method and system based on backdoor access, and the system comprises a C language printing function, other C language functions, a monitor and a printer; a C language printing function or other functions of the C language are called on a software side, an embedded sink writes an interaction mark to a mark register in a CPU, a printing data pre-storage SoC and a monitor backdoor obtain a register state, identify interaction and trigger a printer, and the printer obtains printing information from a target register in the CPU, analyzes the printing information and outputs the printing information to a simulation log. According to the method, the simulation performance and the interaction efficiency are qualitatively improved, the obvious advantages are shown in the aspects of compatibility, expandability and engineering practicability, and efficient, stable and low-overhead operation of a modern SoC chip in the large-scale system-level verification stage can be effectively supported.

The invention relates to a clock stabilization circuit, a memory system and an operation method of the memory system. The clock stabilization circuit includes: a shift register configured to output one or more shift signals by shifting data and an inversion flag based on a clock signal; a comparison circuit configured to output one or more comparison signals by comparing the one or more shift signals with the one or more keys, respectively; a stabilization flag register configured to enable a stabilization flag based on a first delayed clock signal and the one or more comparison signals, the first delayed clock signal being generated by delaying the clock signal; and a shielding circuit configured to output the internal clock signal by shielding a second delayed clock signal based on the stabilization flag, the second delayed clock signal being generated by delaying the first delayed clock signal.

The invention discloses an I2C (Inter-Integrated Circuit) bus expansion method supporting a dynamic address, the expansion method is used for a system for realizing communication through an I2C bus, the system comprises a host and a plurality of expansion modules, communication connection is established between the host and the expansion modules through the I2C bus, an address bus, a power line and a ground line, and communication connection is established between every two adjacent expansion modules through the I2C bus, the address bus, the power line and the ground line. The extension module is used for connecting different external devices; the extension method comprises the following steps: a host accesses a flag register of the last extension module at regular time through an I2C bus, judges whether the numerical value of the flag register is 0 * 01 or not so as to judge whether a new extension module is accessed or not, and decides whether the address of each extension module needs to be adjusted or not; and after all the extension modules are adjusted to effective addresses, the host communicates with each extension module through the I2C bus. Dynamic address adjustment of the external equipment is realized through the address bus, so that expansion of the external equipment is more convenient, control is simple and flexible, and deployment cost is reduced.

Addition instructions with independent carry chains are disclosed. A plurality of addition instructions are provided that have no data dependencies between each other. A first addition instruction stores its carry output in a first flag of a flags register and does not modify a second flag in the flags register. A second addition instruction stores its carry output in the second flag of the flags register and does not modify the first flag in the flags register.

The application discloses a fault-tolerant method for firmware updating, an electronic device, a storage medium and a program product. When the device is started, the state of a flag register is read first. If the state of the flag register is a preset first value, an old firmware is loaded from a flash memory, and the device is started based on the old firmware. The old firmware is the firmware applied by the device when the device is last successfully started. If the state of the flag register is a preset second value, a new firmware is loaded from a storage unit, and the device is started by using the new firmware. Then, a starting result when the device is started by using the new firmware is acquired. If the starting result indicates that the device fails to start, the state of the flag register is set to the first value. According to the embodiment of the application, when firmware programming is wrong, the starting path is switched by using the flag register, the accurate old firmware in the flash memory is read, the device is restarted to restore the normal starting logic, the PCIe interface initialization continuously fails due to the wrong firmware is avoided, and the reliability of the firmware online updating is improved.

A computer system and a mode switching method thereof are provided. The computer system includes a processor, a plurality of peripheral components, and a switch. The switch is coupled to the processor via a first transmission interface link and respectively coupled to the plurality of peripheral components via second transmission interface links. The switch includes a first flag register and a second flag register. When a first target peripheral component in the peripheral components is to be entered into a low power consumption mode, the processor sets a low power consumption flag bit corresponding to the first target peripheral component in the first flag register. When a second target peripheral component in the low power consumption mode in the peripheral components transmits a wake-up signal to the switch, the switch sets a wake-up flag bit corresponding to the second target peripheral component in the second flag register.

The application discloses a device for detecting a Loran C key signal, which comprises an input circuit, a counter, a state flag register and an abnormality detecting circuit, and provides a method for detecting the Loran C key signal. The rising edge of a serial data signal SERDA is detected by the input circuit to control the counter and the abnormality detecting circuit. The abnormality detecting circuit detects the count value output by the counter to detect whether the serial data signal SERDA comprises four single pulses, i.e. a start pulse STP, a charge trigger pulse Charge, a discharge trigger pulse DC_Trig and a magnetic pulse reference pulse MEG_REF in sequence, and the count values of the four single pulses correspond to the time intervals in the count value threshold interval of each single pulse, so that the integrity of the serial data signal SERDA is judged. The application effectively solves the monitoring problem of the SERDA signal in a Loran wave emission control system, and guarantees the normal operation of the emission control system.