284 results about "Condition Code" patented technology

A method and apparatus are disclosed for transmitting advertising information to a mobile terminal over a first connection during a synchronization session and storing the advertising information in a local memory of the mobile terminal. A rich text document is transmitted to the mobile terminal over a second connection, wherein the rich text document comprises conditional code comprising advertising display criteria including a first identifier for retrieving selected advertising information stored in the local memory of the mobile terminal and a second identifier for downloading the selected advertising information from the Internet.

A scalable pipelined pixel shader that processes packets of data and preserves the format of each packet at each processing stage. Each packet is an ordered array of data values, at least one of which is an instruction pointer. Each member of the ordered array can be indicative of any type of data. As a packet progresses through the pixel shader during processing, each member of the ordered array can be replaced by a sequence of data values indicative of different types of data (e.g., an address of a texel, a texel, or a partially or fully processed color value). Information required for the pixel shader to process each packet is contained in the packet, and thus the pixel shader is scalable in the sense that it can be implemented in modular fashion to include any number of identical pipelined processing stages and can execute the same program regardless of the number of stages. Preferably, each processing stage is itself scalable, can be implemented to include an arbitrary number of identical pipelined instruction execution stages known as microblenders, and can execute the same program regardless of the number of microblenders. The current value of the instruction pointer (IP) in a packet determines the next instruction to be executed on the data contained in the packet. Any processing unit can change the instruction that will be executed by a subsequent processing unit by modifying the IP (and/or condition codes) of a packet that it asserts to the subsequent processing unit. Other aspects of the invention include graphics processors (each including a pixel shader configured in accordance with the invention), methods and systems for generating packets of data for processing in accordance with the invention, and methods for pipelined processing of packets of data.

An added information encoding part repeatedly arranges two kinds of copy inhibition code arrays of the unit two-dimensional arrays to which copy inhibition codes are assigned, and condition code arrays of the unit two-dimensional arrays to which codes for removing the copy inhibition are assigned, into a two-dimensional array according to given rules. A background image formation part generates a background image in which copy inhibition pattern image areas and condition pattern image areas are repeatedly and two-dimensionally arranged according to given rules, while referring to this array, and the pattern images corresponding to respective codes stored in the background image formation part, and stores the generated background image into a background image buffer. An image composing part reads out document images from a document image buffer, and the background image from the background image buffer, and superimposes them into a composite image.

An image, in which a pattern image is arranged so as to express a control information for inhibiting copying or for removing the inhibition, is defined as an image to be read. A copy inhibition code or a condition code for removing the inhibition is assigned for the pattern image. In a "normal copy mode" of a copier, a copy inhibition information detecting part detects the copy inhibition code in an obtained image, and a controller halts the copying when the copy inhibition code is detected. A condition information detecting part detects the condition code in the obtained image. A copy mode is provided in which the copying operation is permitted when the condition matches. The controller permits copying when a condition, such as permitting a specific user to perform copying or the elapse of a predetermined day and time delimited period, is established.

A dual-instruction set central processing unit (CPU) is capable of executing instructions from a reduced instruction set computer (RISC) instruction set and from a complex instruction set computer (CISC) instruction set. Data and address information may be to transferred from a CISC program to a RISC program running on the CPU by using shared registers. The architecturally-defined registers in the CISC instruction set are merged or folded into some of the architecturally-defined registers in the RISC architecture so that these merged registers are shared by the two instructions sets. In particular, the flags or condition code registers defined by each architecture are merged together so that CISC instructions and RISC instructions will implicitly update the same merged flags register when performing computational instructions. The RISC and CISC registers are folded together so that the CISC flags are at one end of the register while the frequently used RISC flags are at the other end, but the RISC instructions can read or write any bit in the merged register. The CISC code segment base address is stored in the RISC branch count register, while the CISC floating point instruction address is stored in the RISC branch link register. The general-purpose registers (GPR's) are also merged together, allowing a CISC program to pass data to a RISC program merely by writing one of its GPR's, switching control to the RISC program, and the RISC program reading one of its GPR's that is merged with and corresponds to the CISC GPR that was written to by the CISC program.

A processor that promotes accelerated resolution of conditional branch instructions includes an instruction sequencer that fetches a plurality of instructions and a detector that detects, among the plurality of fetched instructions, a condition-setting instruction and a conditional branch instruction that depends upon the condition-setting instruction. The processor further includes a decoder that decodes the conditional branch instruction to produce a decoded condition type and an execution unit. In response to the detection of the condition-setting instruction and the conditional branch instruction, the execution unit resolves the conditional branch instruction by evaluating the condition-setting instruction and the decoded condition type in a single operation. Because the condition code bits are not computed or stored as an intermediate result as in prior art processors, branch resolution is accelerated.

A memory block with any source alignment is streamed into general-purpose registers (GPRs) as aligned data using a streaming load instruction. A streaming store instruction reads the aligned data from the GPRs and writes the data into memory with any destination alignment. Data is streamed from any source alignment to any destination alignment. Memory accesses are aligned to memory lines. The data is rotated using the offset within a memory line of the base address. The rotated data is stored in a scratch register for use by the next streaming load instruction. Rotated data just read from memory is combined with rotated data in the scratch register read by the last streaming load instruction to generate result data to load into the destination GPR. Streaming condition codes are set when the block's end is detected to disable future streaming instructions. Aligned memory accesses at full bandwidth read the un-aligned block.

A method, system and computer program product for issuing one or more software initiated operations for creating a checkpoint of a register file and memory, and for restoring a register file and memory to the checkpointed state. At the execution of a checkpoint operation, the system returns a condition code indicating success or failure. When the condition code is set equal to one, one or more checkpoints are initiated. Contents of the register file and gated store buffer are stored each time the one or more checkpoints are initiated. When the checkpoint is created, the system notifies software when a hardware checkpoint capacity has been reached. One or more of the software checkpoint, hardware checkpoint, and handler checkpoint are utilized to provide a more precise point of restoration. During software execution, the register file and gated store buffer can be restored as defined by the one or more previous checkpoints.

Apparatus and methods for integrated circuit (IC) design, including the configuration and addition of extensions to the design. In one exemplary embodiment, a computer program rendered in an object-oriented language implementing the aforementioned methods for automatically adding user-customized extensions to digital processors is disclosed. The program comprises an extension tool which is adapted for varying levels of abstraction, and to significantly automate the creation and generation of various different extension types including for example ALUs, condition codes, and registers. A markup language (e.g., XML) database of abstracted extension components is utilized to permit ready addition and modification of extensions, as well as applicability of the extensions across different target architectures.

A processor device is disclosed that includes a register file with a combined condition code register for scalar and vector operations. The processor device utilizes the combined condition code register for scalar and vector operations. Further, a compare operation can store resulting bits in the combined condition code register and a conditional operation can utilize the combined condition code register bits for evaluating a condition.

An atomic compare and branch instruction is executed that combines the function of a compare instruction having an option field with a conditional branch or jump instruction such that condition codes are preserved rather than setting condition codes to a value representative of the compare results. One comparand is obtained from any one of a memory location or an immediate field and the other comparand is obtained from a register field.

A Load/Store Disjoint instruction, when executed by a CPU, accesses operands from two disjoint memory locations and sets condition code indicators to indicate whether or not the two operands appeared to be accessed atomically by means of block-concurrent interlocked fetch with no intervening stores to the operands from other CPUs. In a Load Pair Disjoint form of the instruction, the accesses are loads and the disjoint data is stored in general registers.

Disclosed herein is an arithmetic decoding apparatus including an instruction decoder configured to decode an arithmetically encoded data decoding instruction to be executed for carrying out an arithmetic-decoding process of arithmetically decoding arithmetically encoded data into a binary signal; an execution condition code holding section configured to hold the binary signal obtained as a result of an immediately preceding arithmetic-decoding process as an execution condition code; and an arithmetic decoding execution section configured to determine whether a context number specified by the arithmetically encoded data decoding instruction is to be used as a context index as it is or the specified context number incremented by 1 is to be used as the context index in accordance with the execution condition code, and carry out the arithmetic decoding process by making use of the determined context index.

The invention provides an out-of-order execution micro-processor, comprising a temporary memory surname watch for generating a first indication for indicating whether one command depends on a condition code result of a shift command or not. A micro-processor also comprises a first execution unit for executing the shift command and generating a second indication and the second indication indicateswhether one shift amount of the shift command is zero or not. The micro-processor also comprises a second execution unit for receiving the first indication and the second indication and generating a return signal, thus when the first indication indicates that the command depends on the condition code result of the shift command and the second indication indicates that the shift amount of the shift command is zero, the command is returned.

This invention relates to a method for monitoring software use, especially for finding out the flow and controlling high speed download software based on P2P, to overcome the shortage of network band width resource illegal occupying, secret disclosing and virus spreading, said invention identifies condition code (keywords) of data package to affirm high speed downloaded software type, breaking off downloading through breaking (or dropping) its TCP handshaking protocol data package.

A system and process evaluate the presence and absence of particular quality measure codes in a set of patient records and provide a medical service provider with options for taking corrective action when a quality measure code that should be in a patient's record is missing. Patient records are selected based on specific medical condition code combinations along with specifications with age and gender criteria. A quality measure identifier uniquely identifies a set of specification criteria, medical condition criteria, and quality measure criteria.

One aspect of the present invention is a computer-implemented method for attributing applicable condition code(s) to a field claim. One preferred method includes inputting a text comment associated with the field claim, inputting a plurality of condition codes and at least four keyword combinations of at least two non-sequential keywords for each condition code, and for each condition code, attributing the condition code as an applicable condition code if at least one keyword combination for the condition code is included in the text comment. The applicable condition code(s) can be relied upon by individuals to at least identify failure mode(s) associated with field claims.

A TRANSACTION ABORT instruction is used to abort a transaction that is executing in a computing environment. The TRANSACTION ABORT instruction includes at least one field used to specify a user-defined abort code that indicates the specific reason for aborting the transaction. Based on executing the TRANSACTION ABORT instruction, a condition code is provided that indicates whether re-execution of the transaction is recommended.

Systems and methods for dynamically canceling texture fetches may improve texture mapping performance. A shader program compiler inserts condition code writes and condition code comparison operations for shader program instructions that contribute to a texture read instruction and do not need to be executed if certain conditions are met. During execution of the shader program, the inserted condition codes are used to compute a dynamic writemask that indicates if the texture data resulting from the texture read is unnecessary. The dynamic writemask is used to cancel unnecessary texture fetches during execution of the shader program.