76 results about "Graphics processing unit" patented technology

This invention discloses a method, device, medium, and system for generating and using 3D character culling data in computer graphics, belonging to the field of computer graphics. The method includes the following steps: pre-generating frame-level cluster bounding box data corresponding to sampled animation frames; submitting the frame-level cluster bounding box data to the graphics processing unit of the graphics card during initialization; updating the current animation frame using an animation state machine during runtime; during the culling operation, searching for the bounding box data of the cluster in the current animation frame based on the current animation frame and the cluster index, and culling it; if the current animation frame does not match the sampled animation frame, interpolating and calculating the bounding box data corresponding to the current animation frame based on the pre-generated frame-level cluster bounding box data of the animation frames before and after the current animation frame. This invention has advantages such as low overhead, good dynamics, and high culling performance.

Apparatuses, systems, and techniques to perform multi-threaded processing in parallel by one or more software programs on a parallel processing unit (PPU), such as a graphics processing unit (GPU), or any other processing unit capable of supporting multi-threaded software execution. In at least one embodiment, processors, systems, and techniques, during execution of two or more software threads in parallel, identify, using at least one software thread of the two or more software threads, a child node of a parent node in a shared hierarchical data structure stored in memory as a candidate for a state-modifying operation, lock the parent node of the child node to indicate that an operation involving the child node is in progress, and perform, by the at least one software thread, a state-modifying operation on data associated with the child node when the parent node is locked.

Disclosed in the present invention are a self-supervised image denoising method and system. The method comprises: by means of an input interface, acquiring a noise image and transmitting same to a memory; configuring, in the memory, a search space based on a U-Net framework; a graphics processing unit reading configuration information, executing coarse-grained population initialization on the basis of a decimal modular encoding strategy, and writing population data into the memory as a contiguous memory block; the graphics processing unit executing distance-guided parent selection and modular crossover and mutation operations in parallel; decoding offspring individuals into network structures, then executing self-supervised denoising processing in parallel, and calculating PSNR values; and a central processing unit executing environment selection and controlling an iteration process, finally selecting an optimal network structure, and outputting a denoised image. By means of the optimization of search space design and the collaboration of heterogeneous computing architectures, the present invention simultaneously realizes high-quality image detail restoration and efficient denoising processing, without requiring paired data.

This invention provides a semiconductor package and a method for manufacturing the same. The package includes: a base substrate; an intermediate substrate disposed on the base substrate; a plurality of first conductive blocks sandwiched between the base substrate and the intermediate substrate and electrically connected to both; a graphics processing unit disposed on the intermediate substrate; and a plurality of second conductive blocks sandwiched between the intermediate substrate and the graphics processing unit and electrically connected to both. The plurality of second conductive blocks are electrically connected to the plurality of first conductive blocks through the intermediate substrate.

Techniques are disclosed for end-to-end assurance of application workloads. For example, a computing system receive time series data comprising performance indicators for elements of layers of a system having host computing devices executing application workloads. The computing system creates, based on mapping, using the time series data, Graphics Processing Units (GPUs) of a compute layer to network devices of a network layer, a dependency graph representing cross-layer relationships between elements of different layers of the layers. The computing system determines an anomaly in the performance of one of the application workloads. The computing system determines, based on a dependency within the dependency graph of the application workload on an element of the network layer, an issue with the element as a root cause of the anomaly in the performance of the workload, and performs a remedial action for the issue with the element of the network layer.

Techniques relating to graphics processing units (GPUs) that support ray tracing are disclosed. Specifically, shader switching logic can be configured to adjust the scheduling priority of a single-instruction multiple-data (SIMD) group of a shader program based on an indication that the SIMD group has an upcoming ray-cutting instruction for the ray-cutting accelerator switching logic, and based on a resource consumption indicator from the ray-cutting accelerator switching logic. This can be advantageous for reducing cache thrashing, for example, when shaders allocate memory for ray-cutting instructions and fill a shared cache faster than the ray-cutting accelerator switching logic can process the rays.

The present invention relates to a system and method for real-time screening of Attention Deficit Hyperactivity Disorder using electroencephalographic signals processed through a GPU-accelerated time-frequency inference architecture. The invention enables continuous acquisition of multi-channel electroencephalographic data, adaptive preprocessing for artifact suppression and signal stabilization, and parallel execution of time-frequency transformations to extract neurologically relevant features in real time. Extracted features are analyzed using an inference process configured to identify neurological patterns associated with Attention Deficit Hyperactivity Disorder, while continuous validation of signal quality and temporal consistency ensures diagnostic reliability. The system dynamically adapts analytical parameters based on evolving signal characteristics and regulates computational workload to achieve energy-efficient operation during prolonged monitoring. The invention provides a technically integrated, machine-implemented screening solution capable of delivering reliable, real-time neurological assessment suitable for clinical environments.

A graphics processing unit (GPU) and a ray tracing processing method, terminal device, and medium are disclosed. The GPU includes: a ray generation unit that generates rays and outputs them to a ray tracing unit; a ray tracing unit that, during the traversal of primitives within a bounding box, sends a target request corresponding to the target primitive to a shader execution management unit in response to detecting a target primitive of a target type, and continues traversing other primitives within the bounding box; and updates a minimum distance parameter in response to receiving the execution result corresponding to the target request; a shader execution management unit that invokes a thread bundle in response to receiving the target request; and a shader execution unit that executes the target request based on the thread bundle, obtains the execution result corresponding to each target primitive, and outputs it to the ray tracing unit. This solution can reduce the processing latency of the ray tracing unit and improve the execution efficiency of the GPU.

This invention provides a method and apparatus for acquiring memory access characteristic data of a graphics processing unit (GPU), relating to the field of computer technology. The method includes: intercepting call parameters of application programming interfaces (APIs) in the GPU runtime library; constructing a memory region tree structure based on the call parameters; inserting a preset function into the execution instruction stream of the GPU kernel to acquire instruction-level execution data; and generating GPU memory access characteristic data based on the memory region tree structure and the instruction-level execution data. The GPU memory access characteristic data acquisition method and apparatus provided by this invention correlate macroscopic memory and communication semantics with microscopic instruction-level execution data to generate global, fine-grained memory access characteristic data, improving the comprehensiveness and accuracy of acquiring GPU memory access characteristic data in cloud-edge-device architectures.

Apparatuses, systems, methods, and techniques to perform graphics processing unit (GPU) initiated networking (GIN). In at least one embodiment, generation of a work queue element (WQE) is offloaded from the GPU to separate hardware (e.g., an accelerator or processor in a network interface controller). In at least one embodiment, the GPU generates a GPU-friendly descriptor (GFD), instead of a WQE, that contains information to create a WQE and transfers the GFD to the separate hardware, which performs the creation of the WQE, processes a completion queue entry (CQE), and provides a notification to the GPU that processing the WQE has been completed.

The application discloses a ray tracing method and device, a graphics processing unit and electronic equipment, relates to the field of graphics processing technology, and is used for reducing the calculation load of intersection calculation of ray information in an acceleration structure, improving the efficiency of ray tracing, and reducing the power consumption of a ray tracing device. The ray tracing method is applied to a ray tracing device, and the method comprises the following steps: acquiring image information from a shader, wherein the image information comprises ray information and identification information, the identification information is used for indicating a starting node of intersection calculation of the ray information in the acceleration structure, the acceleration structure is created based on a scene where the ray information is located, and the starting node is any one node in the acceleration structure; starting from the starting node indicated by the identification information, performing intersection calculation on the ray information in the acceleration structure to obtain an intersection result; and sending the intersection result to the shader, wherein the intersection result is used for generating a target image under the scene.

A neural network graph partitioning system and method are disclosed. The graph partitioning system is used to partition a neural network graph into a series of subgraphs and allows multiple subgraphs to be executed in available hardware subsystems. The system estimates the computation time and memory bandwidth of the partitioned subgraphs based on a cost function. The graph partitioning system is a hardware cycle estimation model that can be run quickly and implements parameterization of memory latency. The graph partitioning system supports heterogeneous partitioning for different types of accelerators, such as central processing units, graphics processing units, application specific integrated circuits, etc. A method of partitioning a neural network graph into a series of subgraphs is also disclosed.

The embodiment of the disclosure provides a construction method of an inference simulation model, a data processing method and related products, which relate to the technical field of model inference, and specifically comprises: obtaining operator running resources required by a plurality of operator units in a to-be-deployed model respectively in a model inference stage; obtaining a hardware performance baseline of a target graphics processing unit (GPU); determining a performance discount factor of the to-be-deployed model under a target parallel strategy; and constructing an inference simulation model for evaluating inference performance of the to-be-deployed model based on the operator running resources required by the plurality of operator units respectively in the model inference stage, the hardware performance baseline and the performance discount factor. In this way, the inference simulation model for evaluating the inference performance of the large-scale language model under the specific hardware configuration is accurately constructed.

The present disclosure provides a model inference method and device and electronic equipment, relates to the technical field of computers, in particular to the technical fields of artificial intelligence, large models, front ends, data processing, memory and video memory resource management, and the like. The specific implementation scheme is as follows: in response to an inference request, model data of an inference model is obtained, and the model data is loaded into a memory buffer; wherein the model data includes model structure metadata and weight data; according to the model structure metadata that has been loaded into the memory buffer, video memory resources required by the inference model are created, and the weight data loaded into the memory buffer is written into the video memory resources; the weight data in the video memory resources is read by a graphics processing unit, and the calculation logic of the inference model is executed to obtain an inference result.

Systems and methods in accordance with the present disclosure can implement a parallel processing system, such as a graphics processing unit (GPU)-based system, to generate solutions to complex computational problems. Aspects of this technical solution can retrieve a plurality of solutions each representing a plurality of values in a multi-dimensional space, allocate, to one or more processing units associated with the one or more circuits and having a parallelized configuration, one or more of the plurality of solutions, modify, by the one or more processing units according to the parallelized configuration, at least one value of the one or more solutions allocated to the one or more processing units, to determine a plurality of modified solutions, and output, from the plurality of modified solutions, according to one or more criteria indicating a diversity among the plurality of modified solutions, a selected solution.

The application discloses a virtual terrain landscape generation method and system, an electronic device and a storage medium, and relates to the technical field of computers. The method comprises the following steps: generating original block models with different inner surface detail levels; each original block model is square in shape, and the number of surfaces of the outermost layer is the same; the number of surfaces of the inner surfaces of the original block models with different inner surface detail levels is different; a central processing unit generates a terrain height map, a target ground map array, a target normal map array, a ground control map and a void model; a graphics processing unit performs seamless connection on the original block models with different inner surface detail levels according to the terrain height map to obtain a terrain model; a ground map is rendered according to the ground control map, the target ground map array and the target normal map array to obtain a ground map model; and the ground map model, the terrain model and the void model are combined to obtain a target virtual terrain landscape. The performance consumption can be reduced in the process of generating the virtual terrain landscape.

Technology to program graphics processing unit (GPU) command buffers can include a processor and memory storing instructions which, when executed, cause the processor to compile a source file to generate a command list, where the command list includes hardware-specific executable commands for a GPU, and dispatch the command list to a command buffer for execution by the GPU. The command list can be dispatched via an application programming interface (API) call to a graphics driver, where the API call bypasses generating GPU commands for the command list and the graphics driver bypasses encoding the hardware-specific executable commands in the command list. Source files can include function calls specific to GPU hardware blocks, where the command list includes executable commands directed to the GPU hardware blocks based on the function calls. The command list can include an executable loop command, an executable conditional branch command, and / or an executable jump command.

Embodiments provide a fast multi-agent reinforcement learning (RL) pipeline that runs the full RL workflow end-to-end on a single GPU, using a single store of data for simulation roll-outs, inference, and training. Specifically, simulations and agents in each simulation are run in tandem, taking advantage of the parallel capabilities of the GPU. This way, the costly GPU-CPU communication and copying is significantly reduced, and simulation sampling and learning rates are in turn improved. In this way, a large number of simulations may be concurrently run on the GPU, thus largely improving efficiency of the RL training.

This disclosure relates to the field of graphics processing units (GPUs), and proposes a tile filling device, method, GPU, and electronic device. The tile is used to store attribute information generated when a geometry processing pipeline implements the function of a shader. The device includes: a control module for determining the position of a vertex within the tile; wherein, when the shader is a mesh shader and the attribute information includes primitive attribute information, for each vertex that triggers a primitive, the position corresponding to the vertex is incremented by one, and the newly added position is used to store the primitive's attribute information; and a filling module for writing attribute information to the positions corresponding to the vertices within the tile. When the GPU implements a mesh shader, this device can reduce hardware storage costs and bandwidth usage, lower power consumption, and improve GPU performance and throughput.

Techniques related to ray tracing and motion blur in graphics processing units are disclosed. In some embodiments, a ray intersection accelerator circuit is configured to perform a traversal operation on an accelerated data structure (ADS) including a hierarchical bounding volume, wherein the ADS includes a first node specifying: a first coordinate of the bounding volume at a first motion blur time and a second coordinate of the bounding volume at a second motion blur time. The ray accelerator can determine a ray time interval representation indicating an upper and lower bound of an error bound representing a quantized ray time value. An interpolation circuit can operate on the first coordinate, the second coordinate, and the ray time interval representation to generate interpolated coordinates of the bounding volume. A box test circuit can determine whether a ray intersects with the bounding volume based on the interpolated coordinates and the ray coordinates.

An exemplary device includes an interface circuit arrangement, machine-readable instructions, and at least one processor circuit arrangement programmed by the machine-readable instructions to distribute a computational task based on a stack dimension to one or more cores, to perform a row pooling operation to generate a first intermediate data output based on the stack dimension and a first pool size, to perform a column pooling operation to generate a second intermediate data output based on the stack dimension and a second pool size, and to generate a final output based on the first intermediate data output and the second intermediate data output.

The application relates to the technical field of image processing, and discloses a real-time image breaking special effect implementation method and device and a storage medium, which comprises the following steps: calculating vertex positions of image breaking according to different requirements, then determining vertex indexes of each piece of fragment based on the vertex positions and a fragment thickness, calculating a motion state of each piece of fragment by exerting an external force, and finally updating the state of the fragment and real-time rendering the result, so that the breaking special effect of the image can be real-time rendered, the modern programmable pipeline of a graphic processing unit (GPU) is used to accelerate the calculation and rendering of the image, the processing efficiency of the image breaking special effect is greatly improved, the real-time processing can be realized in a mobile device, the shape and quantity of the fragment can be selected, the content of the breaking effect is more abundant, the breaking special effect generation process is fast and smooth, the effect is real, and the physical feeling is strong.

A system that includes a graphics processing unit (GPU) comprising at least one processor and circuitry. In some examples, the circuitry is to load one or more compressed boot image files from a storage device over an interface, wherein the circuitry is to decompress portions of the one or more compressed boot image files and store the decompressed portions of the one or more compressed boot image files for access by a boot processor.

This application relates to an operator accuracy testing method, apparatus, device, medium, and program product, applied to a graphics processing unit (GPU). The method includes: acquiring a test instruction for an operator to be tested; if the test instruction is a first test instruction, then using a reference operator and the operator to be tested stored in the GPU to perform an accuracy test on the operator to be tested, and determining the accuracy test result. The first test instruction instructs the GPU to test the accuracy of the operator to be tested. This method enables parallel computation of the reference operator and the operator to be tested by the GPU, achieving accuracy testing of the operator to be tested, reducing data migration and scheduling interactions between the CPU and the GPU, and thus improving the efficiency of operator accuracy testing.

The present disclosure proposes a method, apparatus, and computer-readable medium for model checkpoint saving based on multi-tier storage. During a training of a machine learning model performed through a Graphics Processing Unit (GPU) in a target node, a checkpoint to be saved of the machine learning model may be identified from a GPU memory that directly exchanges data with the GPU. The checkpoint may be saved from the GPU memory to a central processing unit (CPU) memory that directly exchange data with a CPU in the target node. The checkpoint may be saved from the CPU memory to a non-transitory memory, the non-transitory memory including at least one of: a local non-transitory memory in the target node, a neighbor non-transitory memory in a neighbor node of the target node, and a remote non-transitory memory located remotely from the target node.

This disclosure provides systems, devices, apparatus, and methods, including computer programs encoded on storage media, for determining a bounding box for geometric correction. A bounding box engine may obtain an indication of a set of reprojection distortions. The bounding box engine may obtain an indication of a set of bounding box instructions. The bounding box engine may obtain either indication from at least one of a central processing unit (CPU) or a digital signal processor (DSP). The bounding box engine may determine a bounding box based on the set of reprojection distortions and the set of bounding box instructions. The bounding box engine may output an indication of the determined bounding box. The bounding box engine may output the indication to at least one of a graphics processing unit (GPU) or a geometric correction engine.

This invention discloses a data transmission and processing method and medium for distributed scenarios. The method involves acquiring and parsing the current data transmission task to obtain the raw transmission data; performing low-precision quantization based on the task accuracy requirements and data quantization type of the raw transmission data to obtain each current low-precision quantized group transmission data; acquiring the bit width of each data bit and generating each current low-precision quantized packet transmission data using a transmission data packaging method; using a communication topology optimization method, transmitting the packet transmission data using multiple graphics processing units (GPUs); and combining a transmission data unpacking method with dequantization calculations and broadcast operations based on the computational tasks corresponding to each GPU to obtain the target data processing result. This method solves the problems of accuracy loss and poor versatility caused by fixed low-bit quantization in existing technologies, improves data transmission efficiency and computational accuracy, and reduces bandwidth pressure.

The embodiments of the disclosure provide an image quality adjusting method and a host. The method includes: providing, by a host, a visual content, wherein the visual content comprises a pass-through image; obtaining, by the host, a frame rate of the visual content and a loading of a graphic processing unit of the host; and dynamically adjusting, by the host, an image quality of the pass-through image based on the frame rate and the loading of the graphic processing unit of the host.

This application discloses a high-performance computing module and data processing method, which adopts a standard 6U VPX architecture. The module includes: a Tengrui D3000 central processing unit (CPU), a DDR5 memory module, a complex programmable logic device (CLP) module, a baseboard management controller, at least one graphics processing unit (GPU) module, a storage module, multiple network controllers, a universal serial bus (USB) controller, at least one serial high-speed input / output (HSI) chip, and a peripheral component interconnect standard high-speed channel (PSC) bridge. The CPU serves as the core and is connected to each functional module via a high-speed bus. By integrating a high-performance processor, a GPU, and multiple high-speed data interfaces within a standardized VPX architecture, this application solves the technical problem in existing technologies where computing modules struggle to balance computing power density, interface bandwidth, and architectural flexibility, achieving high-density heterogeneous computing and high-throughput data exchange capabilities within a compact physical space.

This application proposes an image processing method, apparatus, electronic device, and storage medium. The method includes: obtaining a first layer of a target interface to be displayed by a target application, wherein the first layer is determined based on an initial layer of the target interface rendered by a graphics processing unit (GPU) in the electronic device; performing color compensation on the first layer according to color compensation information corresponding to the GPU; and displaying the target interface according to the color-compensated first layer. By performing color compensation on the first layer according to the color compensation information corresponding to the graphics processing unit, a color-compensated first layer corresponding to the target interface to be displayed on the electronic device is obtained, so that the color-compensated first layer has color consistency, thereby achieving color display consistency of the target interface on different electronic devices and improving the visual effect.