7 results about "Graphics pipeline" patented technology

This application provides a graphics processing apparatus, method, graphics processor, and computer device. The graphics processing apparatus includes a pixel processing pipeline, at least two graphics pipeline clusters, and cache units corresponding to each graphics pipeline cluster. The graphics pipeline clusters are configured to: divide a rendering task in a geometric data stream into multiple data segments; obtain a target data segment from among the multiple data segments; execute the geometric processing of the target data segment in parallel to obtain the corresponding data segment processing result; and store the data segment processing results belonging to the same subtask in the same cache unit. At least two data segments belonging to the same subtask in the geometric data stream are processed by all or part of the at least two graphics pipeline clusters. The pixel processing pipeline is configured to obtain all data segment processing results of the target subtask from the cache unit and perform the pixel processing of the target subtask. This application can reduce the probability of memory overflow.

A graphics pipeline includes a first shader that generates first wave groups, a shader processor input (SPI) that launches the first wave groups for execution by shaders, and a scan converter that generates second waves for execution on the shaders based on results of processing the first wave groups by the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.

The application provides a graphics processing device, a method, a graphics processor and a computer device, wherein the graphics processing device comprises a pixel processing pipeline, at least two graphics pipeline clusters and a cache unit corresponding to each graphics pipeline cluster, wherein: the graphics pipeline cluster is configured to cut a rendering task in a geometry data stream to obtain a plurality of data segments, obtain a target data segment from the plurality of data segments, perform a geometry processing process on the target data segment in parallel to obtain a corresponding data segment processing result, and store the data segment processing results belonging to a same subtask to the same cache unit; wherein at least two data segments belonging to the same subtask in the geometry data stream are processed by all or part of the at least two graphics pipeline clusters; the pixel processing pipeline is configured to obtain all data segment processing results of a target subtask from the cache unit and perform a pixel processing process on the target subtask. The application can reduce the probability of memory overflow.

This invention provides a method and system for application graphics interface redirection and hardware acceleration in a heterogeneous computing environment, relating to the field of computer technology. First, the initial graphics instruction stream generated by the target application, conforming to a first graphics interface specification, is intercepted at the source computing node. Next, relevant information about the target computing node is obtained, and the initial graphics instruction stream is semantically parsed to obtain a sequence of instruction stream semantic units. Based on this sequence of instruction stream semantic units, an intermediate representation structure of the graphics pipeline is constructed and translated to generate a target hardware-executable graphics instruction stream. The target hardware-executable graphics instruction stream is transmitted to the target computing node via a cross-node transmission channel. At the target computing node, the graphics processing of the target hardware-executable graphics instruction stream is invoked to obtain graphics rendering result frame data, which is then returned to the source computing node via a return channel. This invention achieves graphics interface redirection and hardware acceleration in a heterogeneous environment.

This invention discloses a multi-dimensional perceptual gaze-point rendering method, system, and medium. The multi-dimensional perceptual gaze-point rendering method is characterized by the following steps: S1, acquiring the user's eye-tracking data in real-time within a virtual reality environment; S2, dividing the rendering sequence into saccade windows, recovery windows, and stable gaze windows; S3, constructing a multi-dimensional visual perception model that integrates saccade sequence features; S4, acquiring the perception critical frequency and mapping it to a resolution scaling factor to guide rasterization operations in the graphics pipeline; S5, invoking the resolution scaling factor and performing dynamic resolution rendering in the graphics rendering pipeline based on the resolution scaling factor. The system includes a data acquisition module, an event detection module, a model calculation module, a rendering scheduling module, and a graphics drawing module. This invention is rationally designed, effectively utilizing computing resources, improving the rendering system's frame rate, and enhancing the user experience.

This application discloses a method, apparatus, and electronic device for creating a graphics pipeline, belonging to the field of computer technology. The method includes: obtaining graphics pipeline creation request information sent by a first application; the graphics pipeline creation request information is used to request the creation of a first graphics pipeline; obtaining pre-compiled binary data of the first graphics pipeline from the pipeline cache through the graphics card driver of the electronic device; the pipeline cache includes binary data after pre-compiling at least one graphics pipeline; and creating the first graphics pipeline based on the pre-compiled binary data.

This application discloses controlling a rough pixel size from stencil print buffers. Systems, apparatuses, and methods can provide techniques to determine a stencil print value and use the stencil print value to control a rough pixel size of a graphics pipeline through a stencil print buffer. Additionally, the stencil print value can include a first bit range defining a first dimension of the rough pixel size and a second bit range defining a second dimension of the rough pixel size. In one example, the rough pixel size is controlled pixel by pixel for a plurality of pixels.