49 results about "Graphics pipeline" patented technology

The invention discloses a graphic rendering system and method based on OpenGL SC and a related product. The system comprises a rendering interface module used for providing a high-order graphic rendering function interface for an application program to receive graphic modeling data; the data conversion module is used for converting the graphic modeling data into intermediate drawing data conforming to the OpenGL SC standard; the graphic processing module is used for executing graphic calculation and rendering logic based on the intermediate drawing data and generating a rendering instruction; and the graph drawing module is used for calling the underlying OpenGL SC function library to execute the rendering instruction so as to complete graph rendering. According to the graphic rendering system, the underlying graphic pipeline is packaged inside, the development threshold and complexity are reduced through the high-order graphic interface, and the development efficiency and reliability are improved. All the modules are standardized and coordinated to realize complete process packaging from data to rendering, so that optimization and maintenance are integrated inside, and the maintainability, expandability and stability of the system are enhanced.

An apparatus to facilitate hardware acceleration of resource barriers in a graphics environment is disclosed. The apparatus includes resource barrier hardware circuitry for processing cores and a graphics pipeline to: receive a resource barrier instruction to transition a resource utilized by the graphics pipeline from a first usage to a second usage; responsive to the resource barrier instruction, cause a draw group marker having a current draw group count to be sent to an end of the graphics pipeline to track completion of each stage of the graphics pipeline; increment the current draw group count to a new draw group count for each new draw group of the graphics pipeline; and determine that a current signal stage of the graphics pipeline is complete for a current draw group responsive to a done count for the current signal stage being less than or equal to the current draw group count.

The present disclosure relates to methods and systems for using the computer graphics pipeline to execute database query operations on a graphics processing unit (GPU). The methods and systems use the graphics pipeline to transform relational data into images of the relational data. The methods and systems use the graphics pipeline to perform relational database operations on the images in response to a query and output a query result for the database operations.

An apparatus and method for efficiently managing jobs of a workload performed among multiple integrated circuits in separate semiconductor chips. In various implementations, a computing system includes a first processing node and a second processing node that together render and present video frame data. The graphics application holds the start of processing the next video frame until the first processing node receives result data for the current video frame from the second processing node and presents the video frame data. To remove latency, once the result data is generated, the first processing node performs a mocked present job visible to the operating system scheduler but sends no data to the display controller. The rendering of the next video frame begins, and the first processing node later presents the result data to the display controller.

Data representing a 3D object to be rendered is obtained, the data comprising: a mesh structure defining 3D co-ordinates for each of a plurality of object vertices; and a feature vector encoding visual characteristics for at least one object surface defined by the plurality of object vertices. Motion information indicative of motion of the object in a scene is received. Based on the motion information, the mesh structure is deformed by adjusting the co-ordinates for one or more of the plurality of object vertices. The deformed mesh structure is processed using a graphics pipeline comprising a vertex shader and a fragment shader to generate a rendered image of the scene. The fragment shader comprises an artificial neural network trained to output pixel colour values for the at least one object surface on the basis of the visual characteristics encoded in the feature vector.

The system and method involve loading views of a multi-view image into memory. The views can be formatted as bitmaps defined by a pixel coordinate system. The distance between the view and the central viewpoint can be identified. Subsequently, the views can be rendered in the graphics pipeline as a sheared view based on a shear function applied along the axes of the pixel coordinate system. The shear strength of the shear function is related to the distance between the view and the central viewpoint.

The invention discloses a cross-application double-region real-time color contrast system and method based on dynamic region high-frequency sampling. According to the system disclosed by the invention, efficient operation is realized through cooperation of a modular hardware architecture and a data stream; the screen capture module transmits full-screen pixel data to the dynamic sampling module in real time through memory mapping and a hardware acceleration channel; the dynamic sampling module is combined with a boundary protection unit and a double-buffering technology to ensure data integrity; the high-frequency sampling controller drives an interrupt signal at the frequency of 60FPS to coordinate the time sequence of each module; the real-time comparison interface module dynamically updates an interface through a frame buffer and a graphic rendering pipeline; and the multi-DPI adaptive module realizes cross-screen accurate alignment through a configuration bus and an address decoder. According to the method, through hardware interruption, DMA transmission and graphic pipeline rendering, the color correction efficiency is further improved, and the method is suitable for film and television toning, game development and industrial simulation scenes.

Methods for real-time simulation of a physical environment and corresponding systems, devices, and computer-readable mediums. A method performed by a graphical processing unit (GPU) (200) of a computer system (100) includes reading (402) simulation parameters from a uniform buffer (216) for processing by a compute pipeline (302) of a GPU (200) and by a graphics pipeline (304) of the GPU (200). The method includes programming (404) a vertex buffer (220) in the graphics pipeline (304), based on the simulation parameters, to produce first vertex buffer contents. The method includes performing a simulation (406) in the compute pipeline (302), based on the parameters, the first vertex buffer contents, and first storage buffer contents to produce second storage buffer contents, storing (408) the second storage buffer content in a storage buffer (222), and writing (410) second vertex buffer contents to the vertex buffer (220) based on the second storage buffer contents. The method includes writing (414) data to a frame buffer (210) for display to a user, in the graphics pipeline (304), based on the second vertex buffer contents.

A method for updating information of a graphics pipeline includes: executing an application on a CPU in a first frame period to generate primitives of a scene of a first video frame. Receiving eye gaze tracking information of a user in a second frame period. Predicting a landing point on an HMD display at the CPU at least based on the gaze tracking information in the second frame period. Post-updating the predicted landing point to a buffer accessible by a GPU in the second frame period. Performing shader operations in the GPU in the second frame period to generate pixel data based on the primitives and based on the predicted landing point, wherein the pixel data is stored in a frame buffer. Scanning and outputting the pixel data from the frame buffer to the HMD in a third frame period.

This technology enhances the GPU computing model to provide data marshalling features provided by the system of the graphics pipeline, thereby improving efficiency and reducing overhead. A simple scheduling model based on scalar counters (e.g., semaphores) abstracts the availability of hardware resources. Resource release can be done programmatically, and the system scheduler only needs to track the status of such counters / semaphores to make work start decisions. The semantics of the counters / semaphores are defined by the application, and the application can use the counters / semaphores to represent the availability of available space in the memory buffer, the amount of cache pressure caused by data flow in the network, or the presence of work items to be processed.

Systems and techniques are provided for deferred attribute shading operations in a graphics pipeline (124). A set of primitives is received by one or more shader engines (300, 350) of a processing core (316) for rendering at least a portion of a scene. The shader engine(s) cull the received set of primitives by identifying a subset of the primitives that are potentially visible in the scene; generate intermediate data for the identified subset of primitives; generate attribute data values (235) based on the intermediate data for the identified subset of primitives; and rasterize the identified subset of primitives for rendering based on the generated attribute data values.

The application provides a video rendering method and system based on a computing shader and Xpixmap, compared with an opengl display and a graphics pipeline mode, the computing shader can fully call general computing resources of a GPU, as long as the computing resources are sufficient, high resolution and high frame rate video rendering can be supported, and the processing capacity is greatly improved compared with the graphics pipeline mode. Compared with the opengl display mode, the use of the Xpixmap display mode reduces the multiple copying of the video frame, and further improves the efficiency of the video rendering and display. The scheme fully calls the computing resources of the GPU, renders YUV into RGBA and directly stores in the buffer area corresponding to the Xpixmap, and then uses the X function to submit the display, compared with the opengl display and the graphics pipeline mode, the scheme has higher efficiency, stronger processing capacity and adaptability, and is especially suitable for a graphics processing pipeline with insufficient capacity but powerful general computing capacity.

The invention discloses an SOC-based camera data preview method and device, a medium and a chip, and belongs to the technical field of chips. Creating a streaming media processing pipeline in the Linux system; acquiring camera data acquired by the Ethernet camera by using the data receiving plug-in; the data processing plug-in is used for processing camera data, and obtained video coding data is sent to the decoding plug-in; decoding the video coding data by using a decoding plug-in, and sharing the obtained preview image to a display plug-in; and sharing the preview image to a graphic pipeline GPIPE layer in a display controller DC by using a display plug-in, so that the DC displays the preview image on a screen as an upper layer picture, and the DC is controlled by the RTOS. According to the application, the streaming media processing pipeline is used for interacting with the RTOS system to decode the camera data, and the streaming media processing pipeline is used for interacting with the RTOS system to display the preview image on the screen, so that the camera data can be quickly previewed.

Rendering uses a graphics processing unit which implements a tile-based graphics pipeline where a rendering space is sub-divided into tiles. Primitives are received that were processed by a geometry processing stage of the pipeline and these are grouped into one or more primitive blocks. Primitive block data is stored characterising the content of the one or more primitive blocks. For each tile, the primitives present in the tile are determined, the primitive blocks in which the included primitives are included are also determined, and for at least one selected tile it is determined whether the output of a previous render for the selected tile(s) can be used as an output for the render by determining 1104 whether the number of primitive blocks which contain primitives in that tile exceeds a predefined limit. If the predefined limit is not exceeded, the primitive block data is compared 1110 for the current and previous render. If the threshold is not exceeded, the current render of the tile is performed without comparing the current render to the previous render.

A computing system for preventing document sharing is provided. The computing system includes a processor having an associated memory, the processor configured to execute instructions using portions of the memory to cause the processor to implement a compliance portal in which a policy is established to encompass a plurality of documents, send the policy to a client device having a display screen, and execute the compliance portal using the portion of the memory. And in response to receiving an indication that the client device has triggered the policy, instructing the client device to modify the graphics pipeline to add the opaque watermark to the screen image displayed on the display screen.

According to the video rendering method and system based on the computing shader and the Xpixmap, compared with an opengl display and graph pipeline mode, the computing shader can fully call general computing resources of a GPU, high-resolution and high-frame-rate video rendering can be supported as long as the computing resources are sufficient, and compared with the graph pipeline mode, the processing capacity is greatly improved. Compared with an opengl display mode, the Xpixmap display mode has the advantages that multiple copies of the video frames are reduced, and the video rendering and display efficiency is further improved. According to the scheme, computing resources of the GPU are fully called, the YUV is rendered into RGBA to be directly stored in the buffer area corresponding to the Xpixmap, then the RGBA is submitted and displayed through the X function, compared with opengl display and a graphic pipeline mode, higher efficiency and higher processing capacity and adaptability are achieved, and the method is particularly suitable for a display card with insufficient graphic processing pipeline capacity but high general computing capacity.

In embodiments a graphics pipeline includes a logic that can assess whether to enable or disable tiled rendering for sets of graphics primitives. The logic applies one or more rules or heuristics to a set of graphics primitives associated with a frame, and determines whether to enable tiled rendering for that set of graphics primitives if the one or more rules or heuristics are satisfied. Otherwise, the logic determines to disable tiled rendering for that set of graphics primitives. As further graphics primitives are received for the frame, the logic may make additional decisions as to whether or not to render the further graphics primitives using tiled rendering.

The processing system [100] includes a graphics pipeline [200] that executes a first shader [226] of a first type and a second shader [234] of a second type. In some cases, the first shader is a geometry shader and the second shader is a pixel shader. The processing system includes a buffer [415] that holds primitives generated by the first shader and provides the primitives to the second shader. The processing system includes a primitive hub [325] that monitors the fullness of the buffer. The emission of waves from the first shader is throttled based on the fullness of the buffer. A shader processor input (SPI) [303] selectively throttles waves emitted by the geometry shader based on a signal from the primitive hub indicating fullness, an indicator of the relative resource usage of geometry waves and pixel waves in the graphics pipeline, or an indicator of the age of the geometry waves.

Systems and techniques are provided for deferred attribute shading operations in a graphics pipeline. A set of primitives is received by one or more shader engines of a processing core for rendering at least a portion of a scene. The shader engine(s) cull the received set of primitives by identifying a subset of the primitives that are potentially visible in the scene; generate intermediate data for the identified subset of primitives; generate attribute data values based on the intermediate data for the identified subset of primitives; and rasterize the identified subset of primitives for rendering based on the generated attribute data values.

Systems, apparatuses, and methods for implementing hierarchical scheduling in a fixed function graphics pipeline are disclosed. In various implementations, a processor includes a pipeline including a plurality of fixed function units, and a scheduler. The scheduler is configured to: in response to a first mode of operation, schedule a first operation by scheduling the first operation with a first unit of the pipeline for execution by one or more fixed function units of the pipeline; and in response to the second mode of operation, scheduling the second operation for execution by the selected fixed function unit of the pipeline by scheduling the second operation directly to the selected fixed function unit independent of the sequential arrangement of one or more fixed function units in the pipeline.

An eyewear device comprising (1) a graphics pipeline configured to output a digital representation of an image, (2) an image compensation component configured to shift the digital representation of the image in at least one direction in response to a head movement of a user, and (3) a display device configured to display a shifted version of the image to the user due at least in part to the digital representation having been shifted. Various other apparatuses, systems, and methods are also disclosed.

Provided is a computing system for protection against document sharing. The computing system includes a processor having associated memory, the processor being configured to execute instructions using portions of the memory to cause the processor to implement a compliance portal where a policy is established covering a plurality of documents, transmit the policy to a client device having a display screen, and in response to receiving an indication that the client device has triggered the policy, instruct the client device to modify a graphics pipeline to add an opaque watermark to a screen image displayed on the display screen.

This application provides a graphics processing apparatus, method, graphics processor, and computer device. The graphics processing apparatus includes a pixel processing pipeline, at least two graphics pipeline clusters, and cache units corresponding to each graphics pipeline cluster. The graphics pipeline clusters are configured to: divide a rendering task in a geometric data stream into multiple data segments; obtain a target data segment from among the multiple data segments; execute the geometric processing of the target data segment in parallel to obtain the corresponding data segment processing result; and store the data segment processing results belonging to the same subtask in the same cache unit. At least two data segments belonging to the same subtask in the geometric data stream are processed by all or part of the at least two graphics pipeline clusters. The pixel processing pipeline is configured to obtain all data segment processing results of the target subtask from the cache unit and perform the pixel processing of the target subtask. This application can reduce the probability of memory overflow.

A graphics pipeline reduces the number of tessellation factors written to and read from graphics memory. A hull shader stage detects whether tessellation factors for at least a threshold percentage of a thread group of patches are the same, and whether tessellation factors for a threshold percentage of the thread group of patches have the same value that indicates that the plurality of patches are to be culled or that the plurality of patches are to be passed to a tessellator stage of the graphics pipeline. In response to detecting that tessellation factors for at least the threshold percentage of the thread group are the same, the hull shader stage bypasses writing at least a subset of the tessellation factors for the thread group of patches to graphics memory, thus reducing bandwidth and improving efficiency of the graphics pipeline.

A graphics pipeline includes a first shader that generates first wave groups, a shader processor input (SPI) that launches the first wave groups for execution by shaders, and a scan converter that generates second waves for execution on the shaders based on results of processing the first wave groups by the one or more shaders. The first wave groups are selectively throttled based on a comparison of in-flight first wave groups and second waves pending execution on the at least one second shader. A cache holds information that is written to the cache in response to the first wave groups finishing execution on the shaders. Information is read from the cache in response to read requests issued by the second waves. In some cases, the first wave groups are selectively throttled by comparing how many first wave groups are in-flight and how many read requests to the cache are pending.

The application provides a graphics processing device, a method, a graphics processor and a computer device, wherein the graphics processing device comprises a pixel processing pipeline, at least two graphics pipeline clusters and a cache unit corresponding to each graphics pipeline cluster, wherein: the graphics pipeline cluster is configured to cut a rendering task in a geometry data stream to obtain a plurality of data segments, obtain a target data segment from the plurality of data segments, perform a geometry processing process on the target data segment in parallel to obtain a corresponding data segment processing result, and store the data segment processing results belonging to a same subtask to the same cache unit; wherein at least two data segments belonging to the same subtask in the geometry data stream are processed by all or part of the at least two graphics pipeline clusters; the pixel processing pipeline is configured to obtain all data segment processing results of a target subtask from the cache unit and perform a pixel processing process on the target subtask. The application can reduce the probability of memory overflow.

This invention provides a method and system for application graphics interface redirection and hardware acceleration in a heterogeneous computing environment, relating to the field of computer technology. First, the initial graphics instruction stream generated by the target application, conforming to a first graphics interface specification, is intercepted at the source computing node. Next, relevant information about the target computing node is obtained, and the initial graphics instruction stream is semantically parsed to obtain a sequence of instruction stream semantic units. Based on this sequence of instruction stream semantic units, an intermediate representation structure of the graphics pipeline is constructed and translated to generate a target hardware-executable graphics instruction stream. The target hardware-executable graphics instruction stream is transmitted to the target computing node via a cross-node transmission channel. At the target computing node, the graphics processing of the target hardware-executable graphics instruction stream is invoked to obtain graphics rendering result frame data, which is then returned to the source computing node via a return channel. This invention achieves graphics interface redirection and hardware acceleration in a heterogeneous environment.

To implement a tile-based immediate mode renderer graphics pipeline, an acceleration unit (AU) partitions a frame to be rendered into two or more tiles. For each primitive of a batch of primitives, the AU then determines whether the primitive is at least partially visible in a tile. Based on a primitive being at least partially visible in a tile, the AU stores geometry data of the primitive in the tile in a corresponding per-tile queue allocated to the tile. For each tile and using the geometry data in the per-tile queue allocated to the tile, the AU renders attribute data of the primitives at least partially visible in the tile to one or more buffers. The AU next determines lighting data for the primitives at least partially visible in the tile based on the attribute data in the buffer and stores the results in a frame buffer for display.

An acceleration unit (AU) including instances of pixel circuitry first determines whether primitives in a frame to be rendered are at least partially visible in each tile of the frame. The AU then stores the geometry data of the primitives at least partially visible in each tile in a corresponding per-tile queue allocated to the tile and updates an available tile mask to indicate that the tile is available for rendering. Based on the available tile mask indicating that the first tile is available, a first instance of pixel circuitry uses the geometry data in the per-tile queue allocated to the first tile to attribute data of the primitives at least partially visible in the first tile to one or more buffers. The first instance of pixel circuitry then determines lighting data for the primitives based on the attribute data in the buffer.