27 results about "Memory coherence" patented technology

The present application relates to the technical field of data storage, and specifically discloses a data transmission method and device, a heterogeneous system, and a coherent interconnect processing component. The coherent interconnect processing component installed on a device enables corresponding coherent interconnect interfaces on the basis of the number of other devices to be interconnected in a heterogeneous system where said device is located, initializes physical communication links to obtain memory interconnect parameters, establishes memory coherent interconnect communication links between the devices on the basis of the memory interconnect parameters, allocates corresponding cache spaces from said device, and on the basis of the memory coherent interconnect communication links and the cache spaces, performs cache coherent transaction processing of said device and the other devices, so as to implement memory coherent interconnect transmission requests between said device and the other devices. Therefore, topologies can be dynamically sensed, and memory coherent interconnect communication links between devices in a heterogeneous system can be automatically established, thereby mitigating the problem that different device interconnect protocols need to be managed in the heterogeneous system, achieving inter-device cache coherence, and further improving the access performance.

A method of VM migration includes allocating a designated system memory for a guest VM on a target node and reserving a shared physical memory region on a transfer node that is part of a shared memory pool that is memory coherent and cache coherent with a source node and the target node. The VM system memory of the guest VM is re-mapped from a first physical memory region on a source node to the shared physical memory region on the transfer node and the system memory of the guest VM is copied from the first physical memory region on the source node to the shared physical memory region on the transfer node. The designated system memory on the target node is mapped to the shared physical memory region on the transfer node; the guest VM is stopped on the source node and then resumed on the target node.

Various embodiments include techniques for processing memory operations in a computing system. The computing system includes a central processing unit (CPU) and an auxiliary processor, such as a parallel processing unit (PPU). The PPU can be divided into multiple partitions. Although the partitions are included in a single PPU, the CPU can track the partitions as if the partitions are independent devices rather than different portions of a single device. When two different partitions generate memory operations that access the same memory address in CPU memory address space, the two partitions employ two different data paths. The CPU can use path information for the two different paths to identify which partition generated each memory operation. As a result, the CPU can maintain data consistency and memory coherency in a system where a PPU is divided into multiple partitions.

A system includes a first integrated circuit coupled to a printed circuit board (PCB) and a second integrated circuit coupled to the PCB. The system further includes a ground referenced signaling (GRS) link coupled between the first integrated circuit and the second integrated circuits through the PCB. Unencoded data is transmitted on the GRS link according to a memory coherence protocol.

This application discloses a system, server, method, medium, and program product for sharing a memory resource pool, relating to the field of artificial intelligence. The system includes: connecting multiple switching components of a switch to processors and a memory resource pool of multiple computer devices, with multiple computer devices sharing the memory resources of the memory resource pool through the switch to allocate different memory capacities based on the needs of the computer devices. This not only enables dynamic allocation and efficient sharing of memory resources, improving overall system memory utilization, but also reduces the latency of computer devices accessing memory, ensuring the consistency of shared memory across multiple computer devices, and meeting the needs of various computing scenarios. This solves technical problems in existing server collaborative computing methods based on RDMA (Remote Direct Memory Access) technology, such as high transmission latency, inability to meet the needs of various computing scenarios, inability to ensure the consistency of shared memory across multiple computer devices, and low resource utilization.

This application proposes a fuzzing method and system for CXL devices based on hierarchical state abstraction. While accurately capturing cross-layer state changes in CXL to effectively discover vulnerabilities, it reduces the amount of state data through hierarchical feature selection, reduces deduplication overhead through incremental hashing, and reuses intermediate state operation sequences through a shared state pool, thereby shortening the average execution time of each test case and improving the overall throughput of fuzzing. This application significantly shortens the average test cycle while maintaining a high vulnerability detection rate, especially demonstrating a significant improvement in coverage efficiency for multi-hop memory consistency protocol scenarios.

This invention provides a memory consistency optimization method for IoT edge computing, comprising: real-time acquisition of access operation data of storage units, analyzing and locating hot zones based on access count and average access duration; allocating dedicated buffer pools for the hot zones, redirecting high-concurrency write requests for the hot zones to the corresponding buffer pools, and encapsulating them as timestamped write operations for temporary storage; sorting the write operations in the buffer pools based on timestamps and thread priorities, generating a logically consistent operation sequence, and writing it to the main storage; restoring the physical continuity of data in the main storage through address shifting, and unifying the logical timing of each storage segment in the main storage; stitching the corrected image segments based on spatial topology, and outputting them to the terminal through a timestamp synchronization mechanism, thereby achieving cross-layer collaboration between the physical continuity and logical order of image data, eliminating 3D image stitching misalignment, and ensuring real-time synchronization accuracy.

The application relates to a processor based on a decoupled vector processing unit split by a data path, comprising a pointer taking unit, a decoding unit, a vector processing unit, a scalar processing unit, a memory access scheduling unit and a storage unit. In the processor, a separate path execution state management subunit is arranged in each data path of the vector processing unit, a more accurate scheduling reference is provided for the microinstruction splitting processing of the main scheduler, the difficulty of microinstruction tracking and management is reduced, the register reading request path is optimized, and the timing risk is reduced; and the architecture manages the sequence of scalar and vector memory access requests through a unified memory access scheduling unit, the management difficulty of memory consistency is reduced, and the reliability of the processor system is enhanced.

In an aspect, an apparatus comprises a writer agent, wherein the writer agent may obtain exclusive access to at least one coherence granule of shared memory with respect to one or more other agents. The writer agent may mark, at the writer agent, completion of a store of the at least one coherence granule prior to receipt of data for the at least one coherence granule from the shared memory. The writer agent may receive the data from the shared memory for the at least one coherence granule. The writer agent may store the data at a local cache of the writer agent. The writer agent may modify the data at the writer agent.

The application provides a multi-controller write data method and device, electronic equipment and a storage medium, wherein the method comprises: receiving a write data request, determining to-be-written data corresponding to the write data request and a target data stripe in a RAID to which the to-be-written data is to be written; accessing metadata in an associated memory to determine a target value of a bit corresponding to the target data stripe in the metadata; determining whether the target data stripe is occupied based on the target value, and determining whether to execute a write data operation corresponding to the to-be-written data. Through memory consistency interconnection between multiple storage controllers, memory resource sharing between the storage controllers is realized, the multiple storage controllers are directly associated together through the interconnection memory, and series connection at a physical layer is realized. Through a mode in which the multiple storage controllers jointly operate the same piece of metadata in the interconnection memory, a stripe lock mechanism is abolished, write IO processing delay is reduced, and write data efficiency is improved.

The invention provides an internet of things edge computing-oriented memory consistency optimization method, which comprises the following steps of: acquiring access operation data of a storage unit in real time, and analyzing and positioning a hot section based on access times and average access duration; distributing a special buffer pool for the hot section, redirecting a high-concurrency write-in request for the hot section to the corresponding buffer pool, and packaging the high-concurrency write-in request into a write-in operation with a timestamp for temporary storage; sorting the write-in operations in the buffer pool based on timestamps and thread priorities, generating an operation sequence with consistent logic, and writing the operation sequence into a main storage; repairing the physical continuity of data in the main storage through address translation, and unifying the logic time sequence of each storage segment in the main storage; and splicing the corrected image segments based on a spatial topological relation, and outputting the spliced image segments to a terminal through a timestamp synchronization mechanism, thereby realizing cross-layer collaboration of physical continuity and logic sequence of image data, eliminating three-dimensional image splicing dislocation and ensuring real-time synchronization precision.

A first virtual address is translated into a first physical address using a first translation agent associated with a first I / O device of a system. The first physical address is associated with an address space of the first I / O device. A first address translation request is sent to a second translation agent associated with a CPU of the system. The first address translation request includes the first physical address. A first address translation response is received from the second translation agent. The second address translation response includes a second physical address. the second physical address is associated with an address space of the system.

Method for disabling page replication entries in a data processing system with a plurality of processing elements, wherein the method comprises: Applying a delay (330) to a store reorder queue (SRQ) (229) cleanup cycle of a processing element; Clean up SRQ (229) during the delayed cleanup cycle; and Receiving a translation lookaside buffer invalidation (TLBI) instruction (302) from a connection linking the plurality of processing elements, wherein the TLBI instruction (302) is an instruction to invalidate an address lookaside buffer (TLB) entry (318, 328) corresponding to a virtual memory page and / or a physical memory section, wherein the TLBI instruction (302) is broadcast by another processing element, where by applying the delay (330) to the cleanup cycle of the SRQ (229) the amount of overlap between the cleanup cycle of the SRQ (229) and a deactivation cycle associated with the TLBI (302) is increased.

The invention provides a multi-node memory operation processing method, device and equipment. The method comprises the following steps: receiving memory access requests from at least two nodes; converting the memory access request into a target memory access request; determining a first memory consistency strategy, a second memory consistency strategy or a third memory consistency strategy according to the target memory access request; wherein the first memory consistency strategy enables multiple nodes to have consistent access to shared data through a cache consistency protocol; the second memory consistency strategy allows the nodes to perform memory reordering operation under a predetermined condition; a third memory consistency strategy automatically selects a consistency strategy; according to the memory consistency strategy and the operation type of the target memory access request, performing operation processing on the memory to obtain an operation processing result; and returning an operation processing result to the corresponding node. According to the method, the memory consistency efficiency, adaptability and utilization rate in the heterogeneous computing environment can be improved.

Aspects of the disclosed technology include techniques and mechanisms for dynamic snoop-filter allocation for large-scale memory coherent systems. A coherency manager on an interconnect manages a directory storing data that indicates a current state of each cache line stored within each caching agent on the interconnect and a number of caching agents that share a cache line. Based on receiving a request from a caching agent to access to a cache line, the coherency manager uses a capacity of the directory, such as the number of caching agents that share a cache line, to determine whether to change an operation mode of a memory from a first mode to a second mode.

A cache and memory coherence system includes a plurality of processing chips, each processing chip hosting a different subset of a shared memory space, and one or more routing tables defining access routes between logical addresses of the shared memory space and endpoints corresponding to selected ones of the plurality of processing chips. The system further includes a coherent mesh structure physically coupling each pair of processing chips in the plurality of processing chips, the coherent mesh structure configured to execute routing logic for updating the one or more routing tables in response to identifying a first processing chip in the plurality of processing chips that hosts a failed hardware component, the updating of the routing tables effectively removing all access routes having endpoints corresponding to the first processing chip.

In an aspect, an apparatus comprises a writer agent, wherein the writer agent may obtain exclusive access to at least one coherence granule of shared memory with respect to one or more other agents. The writer agent may mark, at the writer agent, completion of a store of the at least one coherence granule prior to receipt of data for the at least one coherence granule from the shared memory. The writer agent may receive the data from the shared memory for the at least one coherence granule. The writer agent may store the data at a local cache of the writer agent. The writer agent may modify the data at the writer agent.

The invention discloses a tight coupling system architecture and method for accelerating mixed quantum classical computation, and the system architecture comprises a hardware architecture which carries out the tight integration of a main processor and a quantum accelerator, and a software architecture which carries out the expansion of an instruction set architecture of the main processor. A uniform memory space shared by a main processor and a quantum accelerator is deployed on a hardware architecture, an efficient quantum controller and a multi-stage hardware pipeline are realized, an extended instruction set is constructed on a software architecture, and a dynamic incremental compiling mechanism, a fine-grained memory consistency synchronization mechanism and an efficient quantum-classical scheduling mechanism are realized. Through software and hardware collaborative design, the execution efficiency of the mixed quantum classical algorithm can be effectively improved.

In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.

Various embodiments include techniques for processing memory operations in a computing system. The computing system includes a central processing unit (CPU) and an auxiliary processor, such as a parallel processing unit (PPU). The PPU can be divided into multiple partitions. Although the partitions are included in a single PPU, the CPU can track the partitions as if the partitions are independent devices rather than different portions of a single device. When two different partitions generate memory operations that access the same memory address in CPU memory address space, the two partitions employ two different data paths. The CPU can use path information for the two different paths to identify which partition generated each memory operation. As a result, the CPU can maintain data consistency and memory coherency in a system where a PPU is divided into multiple partitions.

This application provides a method for migrating a virtual machine and an apparatus. The method is applied to a source-end physical host, the source-end physical host includes a host machine operating system and a source-end virtual machine running in the host machine operating system, and the host machine operating system includes a physical function (PF) driver. According to the technical solutions of this application, memory consistency, before and after a migration process, of a virtual machine configured with a pass-through device can be ensured.

A memory management method performed by a multi-node computing system includes: transmitting, by a first node, to a second node, first data stored in a first data space of memory of the first node; receiving, by the first node, a write request from the second node, the write request including first modified data and a node identifier identifying the second node, and the first modified data being generated by the second node modifying the first data; determining, by the first node, whether to activate multi-node coherence verification with respect to the first data space based on a bit value of a first verification activation bit; and determining whether to store, by the first node, the first modified data in the first data space without activating the multi-node coherence verification based on the bit value of the first verification activation bit.

The application discloses a distributed system shared memory consistency synchronization method and device, and the device comprises a distributed computing system composed of a plurality of host nodes; the internal hardware of the host node is configured with a storage unit, a processor unit, a communication interface, a host bottom plate and a memory mapping card; the memory mapping card is integrated with an address conversion module, a memory mapping interface module and a memory data transmission module; a memory mapping drive software is deployed on the host node, and the memory mapping drive software is integrated with a memory block mapping management module, a memory operation interception module and a memory data synchronization module. The application can guarantee the consistency of shared memory data between the host nodes of the distributed system; the method of updating after identifying the state can avoid the dead lock phenomenon of updating the memory; and the memory synchronization method distinguishing the read and write requests can improve the efficiency of the shared memory mechanism of the distributed system.

In various examples, when a bridge of a chip has received an eviction request from a client of the chip, the bridge may transmit a read request that corresponds to the same cache line to another chip without waiting for an inter-chip completion response for the eviction request. When the read request is received, the bridge may determine whether the eviction request has already been sent to the other chip and transmit the read request based at least on the eviction request being sent to the other chip using an ordered communication network to ensure the communications are received and / or processed by the other chip in an order that maintains memory coherency. Additionally, the chips may process read unique requests without using an inter-chip completion acknowledgement and may process copy back requests by transmitting corresponding copy back write data with the copy back requests.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

The invention relates to the technical field of multi-core processors, and provides a memory consistency verification method and device for a multi-core processor in a development stage, and the method comprises the steps: obtaining a constraint relation set of a program sequence of random verification excitation; monitoring memory access operation executed by a to-be-tested device in the random verification excitation, wherein the to-be-tested device comprises a module-level to-be-tested device; generating a forward instruction set corresponding to each memory access operation; judging whether each forward instruction set meets a corresponding constraint relationship subset in the constraint relationship set or not; and if yes, confirming that the to-be-tested device conforms to the memory consistency. According to the embodiment of the invention, memory consistency verification can be carried out on the multi-core processor in a development stage in advance.