15 results about "Memory coherence" patented technology

The present application relates to the technical field of data storage, and specifically discloses a data transmission method and device, a heterogeneous system, and a coherent interconnect processing component. The coherent interconnect processing component installed on a device enables corresponding coherent interconnect interfaces on the basis of the number of other devices to be interconnected in a heterogeneous system where said device is located, initializes physical communication links to obtain memory interconnect parameters, establishes memory coherent interconnect communication links between the devices on the basis of the memory interconnect parameters, allocates corresponding cache spaces from said device, and on the basis of the memory coherent interconnect communication links and the cache spaces, performs cache coherent transaction processing of said device and the other devices, so as to implement memory coherent interconnect transmission requests between said device and the other devices. Therefore, topologies can be dynamically sensed, and memory coherent interconnect communication links between devices in a heterogeneous system can be automatically established, thereby mitigating the problem that different device interconnect protocols need to be managed in the heterogeneous system, achieving inter-device cache coherence, and further improving the access performance.

This application proposes a fuzzing method and system for CXL devices based on hierarchical state abstraction. While accurately capturing cross-layer state changes in CXL to effectively discover vulnerabilities, it reduces the amount of state data through hierarchical feature selection, reduces deduplication overhead through incremental hashing, and reuses intermediate state operation sequences through a shared state pool, thereby shortening the average execution time of each test case and improving the overall throughput of fuzzing. This application significantly shortens the average test cycle while maintaining a high vulnerability detection rate, especially demonstrating a significant improvement in coverage efficiency for multi-hop memory consistency protocol scenarios.

This invention provides a memory consistency optimization method for IoT edge computing, comprising: real-time acquisition of access operation data of storage units, analyzing and locating hot zones based on access count and average access duration; allocating dedicated buffer pools for the hot zones, redirecting high-concurrency write requests for the hot zones to the corresponding buffer pools, and encapsulating them as timestamped write operations for temporary storage; sorting the write operations in the buffer pools based on timestamps and thread priorities, generating a logically consistent operation sequence, and writing it to the main storage; restoring the physical continuity of data in the main storage through address shifting, and unifying the logical timing of each storage segment in the main storage; stitching the corrected image segments based on spatial topology, and outputting them to the terminal through a timestamp synchronization mechanism, thereby achieving cross-layer collaboration between the physical continuity and logical order of image data, eliminating 3D image stitching misalignment, and ensuring real-time synchronization accuracy.

In an aspect, an apparatus comprises a writer agent, wherein the writer agent may obtain exclusive access to at least one coherence granule of shared memory with respect to one or more other agents. The writer agent may mark, at the writer agent, completion of a store of the at least one coherence granule prior to receipt of data for the at least one coherence granule from the shared memory. The writer agent may receive the data from the shared memory for the at least one coherence granule. The writer agent may store the data at a local cache of the writer agent. The writer agent may modify the data at the writer agent.

The application provides a multi-controller write data method and device, electronic equipment and a storage medium, wherein the method comprises: receiving a write data request, determining to-be-written data corresponding to the write data request and a target data stripe in a RAID to which the to-be-written data is to be written; accessing metadata in an associated memory to determine a target value of a bit corresponding to the target data stripe in the metadata; determining whether the target data stripe is occupied based on the target value, and determining whether to execute a write data operation corresponding to the to-be-written data. Through memory consistency interconnection between multiple storage controllers, memory resource sharing between the storage controllers is realized, the multiple storage controllers are directly associated together through the interconnection memory, and series connection at a physical layer is realized. Through a mode in which the multiple storage controllers jointly operate the same piece of metadata in the interconnection memory, a stripe lock mechanism is abolished, write IO processing delay is reduced, and write data efficiency is improved.

The invention provides a multi-node memory operation processing method, device and equipment. The method comprises the following steps: receiving memory access requests from at least two nodes; converting the memory access request into a target memory access request; determining a first memory consistency strategy, a second memory consistency strategy or a third memory consistency strategy according to the target memory access request; wherein the first memory consistency strategy enables multiple nodes to have consistent access to shared data through a cache consistency protocol; the second memory consistency strategy allows the nodes to perform memory reordering operation under a predetermined condition; a third memory consistency strategy automatically selects a consistency strategy; according to the memory consistency strategy and the operation type of the target memory access request, performing operation processing on the memory to obtain an operation processing result; and returning an operation processing result to the corresponding node. According to the method, the memory consistency efficiency, adaptability and utilization rate in the heterogeneous computing environment can be improved.

Aspects of the disclosed technology include techniques and mechanisms for dynamic snoop-filter allocation for large-scale memory coherent systems. A coherency manager on an interconnect manages a directory storing data that indicates a current state of each cache line stored within each caching agent on the interconnect and a number of caching agents that share a cache line. Based on receiving a request from a caching agent to access to a cache line, the coherency manager uses a capacity of the directory, such as the number of caching agents that share a cache line, to determine whether to change an operation mode of a memory from a first mode to a second mode.

In an aspect, an apparatus comprises a writer agent, wherein the writer agent may obtain exclusive access to at least one coherence granule of shared memory with respect to one or more other agents. The writer agent may mark, at the writer agent, completion of a store of the at least one coherence granule prior to receipt of data for the at least one coherence granule from the shared memory. The writer agent may receive the data from the shared memory for the at least one coherence granule. The writer agent may store the data at a local cache of the writer agent. The writer agent may modify the data at the writer agent.

In an embodiment, a processor implements a different atomicity size (for memory consistency order) than the operation size. More particularly, the processor may implement a smaller atomicity size than the operation size. For example, for multiple register loads, the atomicity size may be the register size. In another example, the vector element size may be the atomicity size for vector load instructions. In yet another example, multiple contiguous vector elements, but fewer than all the vector elements in a vector register, may be the atomicity size for vector load instructions.

This application provides a method for migrating a virtual machine and an apparatus. The method is applied to a source-end physical host, the source-end physical host includes a host machine operating system and a source-end virtual machine running in the host machine operating system, and the host machine operating system includes a physical function (PF) driver. According to the technical solutions of this application, memory consistency, before and after a migration process, of a virtual machine configured with a pass-through device can be ensured.

A memory management method performed by a multi-node computing system includes: transmitting, by a first node, to a second node, first data stored in a first data space of memory of the first node; receiving, by the first node, a write request from the second node, the write request including first modified data and a node identifier identifying the second node, and the first modified data being generated by the second node modifying the first data; determining, by the first node, whether to activate multi-node coherence verification with respect to the first data space based on a bit value of a first verification activation bit; and determining whether to store, by the first node, the first modified data in the first data space without activating the multi-node coherence verification based on the bit value of the first verification activation bit.

In various examples, when a bridge of a chip has received an eviction request from a client of the chip, the bridge may transmit a read request that corresponds to the same cache line to another chip without waiting for an inter-chip completion response for the eviction request. When the read request is received, the bridge may determine whether the eviction request has already been sent to the other chip and transmit the read request based at least on the eviction request being sent to the other chip using an ordered communication network to ensure the communications are received and / or processed by the other chip in an order that maintains memory coherency. Additionally, the chips may process read unique requests without using an inter-chip completion acknowledgement and may process copy back requests by transmitting corresponding copy back write data with the copy back requests.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

The invention relates to the technical field of multi-core processors, and provides a memory consistency verification method and device for a multi-core processor in a development stage, and the method comprises the steps: obtaining a constraint relation set of a program sequence of random verification excitation; monitoring memory access operation executed by a to-be-tested device in the random verification excitation, wherein the to-be-tested device comprises a module-level to-be-tested device; generating a forward instruction set corresponding to each memory access operation; judging whether each forward instruction set meets a corresponding constraint relationship subset in the constraint relationship set or not; and if yes, confirming that the to-be-tested device conforms to the memory consistency. According to the embodiment of the invention, memory consistency verification can be carried out on the multi-core processor in a development stage in advance.