22 results about "Custom hardware" patented technology

One embodiment illustrated herein includes a hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware processors include an opcode processing unit. The hardware processors further include a programmable state machine coupled to the opcode processing unit. The programmable state machine is configured to be programmed by the opcode processing unit using a low-level hardware programming language comprising opcodes having waveform processing specific semantics so as to configure the state machine for specific waveforms or specific network physical layer characteristics.

One embodiment illustrated herein includes a hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware processors include an opcode processing unit. The hardware processors further include a programmable state machine coupled to the opcode processing unit. The programmable state machine is configured to be programmed by the opcode processing unit using a low-level hardware programming language comprising opcodes having waveform processing specific semantics so as to configure the state machine for specific waveforms or specific network physical layer characteristics.

Provided in the present application is a digital twin system for a target controller, the system comprising a system operating layer, an environment construction layer, a test layer and an analysis layer, wherein the system operating layer is used for simulating the operating state of a digital twin target controller; the environment construction layer is used for building a system operating environment; the test layer is used for transmitting a test instruction to the system operating layer, so as to perform a simulated test in the system operating layer; and the analysis layer receives returned test data transmitted by the test layer, and performs fault cause analysis and recording on fault-related data in the returned test data. The digital twin system for a target controller in the present application virtualizes the operating state of the target controller on a host computer, so that embedded development no longer relies on customized hardware; the hardware design, software functionality and system performance of the system can be verified in advance before real hardware is manufactured; and timely optimization can be performed after design defects are found, so that the number of iterations of product research and development is reduced, and the research and development cost is saved on.

The invention discloses a sparse LU decomposition acceleration method for an FPGA (field programmable gate array) with a flow-sensing high-bandwidth memory, belongs to the technical field of LU decomposition hardware acceleration, and aims to solve the problem of performance bottleneck and efficiency challenge faced by sparse LU decomposition on the FPGA. The acceleration method comprises the following steps of data stream preprocessing, wherein matrix data and metadata are stored and packaged based on a sparse storage format; customizing an FPGA hardware accelerator: carrying out HBM channel allocation and collaborative design of a control unit and memory management; parallel data flow management and scheduling are carried out, and sparse LU decomposition is executed; timely data supply is ensured through a multi-stage pipeline prefetching mechanism; and transmitting the task flow and the data flow to a special parallel processing engine for MAC / DIV calculation in combination with a flow sensing synchronous scheduling strategy.

The invention discloses an edge intelligent computing platform device and a data processing method thereof, and belongs to the field of computers, and the device comprises a customized hardware layer and a system software layer. The hardware layer is integrated with a plurality of high-performance GPUs supporting full-precision calculation, a large-capacity memory and an NVMe flash disk to form a strong computing power and storage basis. A system software layer is integrated, such as a Ray distributed framework, and the key improvement of the system is that an NVMe flash disk is configured as overflow storage of a memory, when the memory is insufficient due to processing of mass data or large model reasoning tasks, intermediate data can be automatically overflowed to a high-speed flash memory, and system crash is avoided. Through deep collaborative optimization of hardware and software, the technical problem that a large model cannot be efficiently operated and big data cannot be processed due to resource limitation on an edge side is effectively solved, and full-stack AI reasoning and high-performance distributed data processing at the edge side are realized.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

A method, system, and device including a computer-readable medium are described for globally tuning and generating an ML hardware accelerator. The design system selects an architecture representing a baseline processor configuration. The system's ML cost model generates performance data for the architecture by modeling, at a minimum, how the architecture executes computations of a neural network comprising multiple layers. Based on the performance data, the architecture is dynamically tuned to meet performance objectives when implementing the neural network and executing machine learning computations for a target application. In response to the dynamic tuning of the architecture, the system generates an ML accelerator configuration that specifies a custom hardware configuration for implementing each of the multiple layers of the neural network.

AutoWrap Robotics is an AI-driven software platform enabling autonomous surface treatments—such as PPF, vinyl wraps, ceramic coatings, window tinting, and custom graphics—on vehicles, watercraft, and buildings. It integrates real-time 3D surface mapping, machine learning, and automated multi-tool switching to perform complex tasks with minimal human input. The system supports gantry robots, articulated arms, mobile platforms, and humanoid robots like Tesla Optimus and Figure AI, offering scalable, flexible control. Cloud-based intelligence powers fleet-wide optimization, allowing shared data to continuously improve motion paths, defect correction, and alignment. This ensures consistent quality and precision across high-volume applications, including branded fleets and commercial installations. By uniting AI-driven planning with robotic dexterity, AutoWrap Robotics delivers high-quality film and coating applications in both controlled and remote settings—without requiring custom hardware. This lowers deployment time, reduces operational costs, and positions the platform as a scalable solution for automated surface treatment at industrial scale.

Disclosed is a design process for high-performance specialized machine learning ASICs, optimized for given models and training or inference hardware end use. Modern Large Language Models (LLMs) and deep learning models can require trillions of parameters to be calculated, and the hardware currently used is not tailored for specific models or input datasets. A key tuneable parameter in custom hardware design is the encoding size of numbers. FPGA prototypes are used to test custom number encoding sizes, which informs the final fabricated design which is created with optimized RTL for the encoding size with attention to number register locations, and component sizes. By first analyzing specific machine learning models on prototype FPGA hardware with variable encoding sizes, the optimal number(s) for encoding size for both training and inference can be identified. By experimentally establishing an optimized encoding sizes for the specific computing use case wasted overhead in terms of physical registers is minimized. The approach herein minimizes research and development costs while optimizing encoding sizes for machine learning ASICS.

The invention discloses a design method of a network packet catcher, and belongs to the technical field of network security detection and monitoring. The method has the advantages that network data are obtained from an MAC layer of network transmission in a physical bus mode, software buffering and tedious forwarding processes are omitted, message obtaining delay is compressed to the nanosecond level, bottom layer logic obtained and captured in the physical bus mode does not need software participation, direct connection between a customized hardware circuit and a physical layer is relied on, and the network data are obtained through the network transmission MAC layer. According to the method, software defects are avoided, the stability and reliability of packet capturing operation are linearly improved, a real-time data direct transmission technology is utilized, local caching is not needed, hardware cost is reduced, the problems of low efficiency and data loss caused by caching are avoided, a single MCU is introduced to perform synchronous setting on a packet capturing device phy and a communication phy, and on the basis of clock synchronization and signal control functions integrated by the MCU, the reliability of the packet capturing operation is improved. An intelligent scheduling algorithm and a bottom-layer driving program are matched, the MCU controls the working states of the two in real time, and the rhythm and parameters are flexibly adjusted.

An object controller digital twin system includes a system running layer, an environment construction layer, a test layer and an analysis layer. The system running layer is used for simulating a running state of the digital twin object controller; the environment construction layer is used for implementing the construction of a system running environment; the test layer is used for transferring a test instruction to the system running layer so as to perform a simulation test in the system running layer; and the analysis layer receives test returned data transferred by the test layer, and performs fault cause analysis and recording on fault-related data in the test returned data. By simulating the running state of the object controller on a host computer, the object controller digital twin system enables embedded development work to no longer rely on customized hardware.

The application provides a zero-invasion computing power acceleration card information customization system and method, and belongs to the technical field of container cloud platforms. Information customization components are containerized and deployed on each node of the container cloud platform, and the information customization components actively listen to the creation or startup event of a business container. After listening to the event, a custom interception dynamic library, a dynamic library sequence control file, and a custom hardware information database are injected into the business container using an NRI mechanism. The technical solution combines the NRI mechanism with the dynamic link library loading mechanism, the custom hardware information database, and other technologies, so that different computing power acceleration card information acquisition technology paths with different sources and levels can obtain preset hidden information as a return result. Moreover, the solution can access the container cloud platform computing power acceleration card hidden or custom capabilities without modifying user business code or modifying the business container image, and has a wide range of application scenarios.

The invention discloses a trusted SDN (Software Defined Network) software switch control flow integrity protection method based on ARM (Advanced RISC Machines) CoreSight. A current control flow integrity protection scheme needs to depend on customized hardware or a simulation instruction set, and has the defects of poor deployment compatibility or large performance overhead, and the method utilizes an ARM CoreSight component widely existing in an ARM architecture chip, realizes non-intrusive acquisition of control flow information of a program under the condition of not influencing program operation in a switch, and improves the safety of the switch. Therefore, the integrity of the program control flow is protected. The control function of the ARM CoreSight component is configured to a trusted secure world, so that program control flow information recorded by the CoreSight component is not tampered by programs in an untrusted common world, meanwhile, the recorded control flow information is analyzed in the secure world, a program control flow diagram is rebuilt, and the program control flow diagram is compared with an expected control flow diagram in static analysis, so that the control flow information of the CoreSight component is determined. Therefore, the control flow integrity of the protected program in the software switch is ensured.

A microprocessor to execute instructions and functions (defined as a macroprocessor) comprises a configurable CPU pipeline. Interconnect structures for configurable CPU pipelines are disclosed. In a first aspect, a configurable data router in an interconnect structure comprises a signal generation unit comprising configuration memory to dynamically receives a bit-code, decode and program configuration memory elements to generate a plurality of control signals to alter data bus coupling for pipelining. In a second aspect, a bit-byte configurable interconnect fabric blends bus-architectures of CPUs with bit-architectures of FPGAs for efficient heterogeneous computing. A bit-byte configurable interconnect fabric facilitates bus data flow between logic-blocks as well as bit-computing within logic-blocks, dramatically reducing the configuration memory required. In a third aspect, a configurable interconnect structure provides bit-stream configurability (at boot time) for user define content to execute in hardware as complex functions, and bit-code configurability (dynamically at run-time) to allow flexible sequencing of a plurality of complex functions to construct concatenated macro functions. In summary, the configurable interconnect structures provide the capability to dynamically program configurable CPU pipelines for a user defined application software content to execute in a custom hardware image.

The invention discloses an I < O > modular configuration system of an upper computer, relates to the technical field of industrial customized upper computer systems, solves the problem that configuration information of traditional configuration software configuration needs to be manually aligned with configuration of a lower computer (actual hardware equipment), and can be automatically aligned with configuration configuration of the upper computer and the lower computer in a one-key manner. According to the invention, multiple configurations can be generated through one-time configuration under multiple redundant configurations (namely multiple master control MCUs), and different MCUs can be adapted. The new I O configuration is changed from traditional source code modification to configuration, and the development efficiency is greatly improved. Through channel-level optimization, the number of used modules is reduced, only required channels and attributes need to be configured, the bandwidth requirement in transmission is greatly reduced, and the data transmission amount is reduced. Different project customization hardware can be quickly realized through configuration, and hardware does not need to be modified. And the configuration file is modified online in real time and becomes effective in real time.

The invention relates to a neural network hardware circuit, a data selection method, a chip and electronic equipment, and belongs to the field of neural networks. The neural network hardware circuit comprises an input data selector, an actuator and an output data selector, wherein the actuator is positioned between the input data selector and the output data selector; the input data selector is used for selecting external input data or internal data of the neural network hardware circuit as an input data source according to a first selection control signal; the actuator comprises a customized hardware circuit corresponding to at least one layer in the neural network; and the output data selector is used for selecting to output the output data of the actuator as the external data or the internal data according to a second selection control signal. According to the invention, the circuit area and power consumption during hardware conversion of the neural network can be reduced.

The application discloses a kind of flow-aware high bandwidth memory FPGA sparse LU decomposition acceleration method, belong to LU decomposition hardware acceleration field, to solve the performance bottleneck and efficiency challenge faced by sparse LU decomposition on FPGA acceleration.The acceleration method includes the following steps: data stream preprocessing: based on sparse storage format, matrix data and metadata are stored and packaged;Custom FPGA hardware accelerator: HBM channel allocation, collaborative design of control unit and memory management are carried out;Parallel data stream management and scheduling, execute sparse LU decomposition: ensure timely supply of data through multi-stage pipeline prefetch mechanism;Combine flow-aware synchronous scheduling strategy to transmit task stream and data stream to dedicated parallel processing engine for MAC / DIV calculation.

The present invention discloses a method and device for automatic deployment of convolutional neural networks based on FPGA. By constructing an automated neural network compilation device, universal, hardware-oriented optimization processing is performed on various input convolutional neural network models to reduce network complexity. The custom hardware instructions obtained after compilation are used to configure the FPGA-based neural network hardware acceleration device that includes a series of universal acceleration modules to control its operations, thereby realizing the automatic and efficient deployment of different convolutional neural network models on the universal hardware acceleration device.

The invention provides a camera signal format conversion method and device based on configurable parameter mapping and a terminal, and the method comprises the steps: dynamically setting an input parameter and an output parameter according to a signal format supported by an accessed camera and a display screen; and analyzing an input signal transmitted by the camera interface based on the input parameter, extracting an effective component, recombining the effective component according to the output parameter, generating image data adaptive to the specification of the display screen, and outputting and displaying the image data. According to the method, cross-interface and multi-format conversion from any camera signal to the display screen format can be automatically completed by dynamically defining the input and output parameters and mapping the dynamic parameters, any display screen specification can be adapted without customizing hardware, the universality is high, the development period is short, and the problems that in the prior art, compatibility is poor, resources are wasted, and the function is single are solved.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

A hardware system for simulating a network physical layer for communication channels. The hardware system includes a plurality of hardware processors configurable to model a network physical layer and communication channels. The hardware system is further implemented where the hardware processors are configured such that a single set of hardware, including a single set of gates and registers, is used in a single simulation to model a plurality of virtual routers for different nodes.

The application discloses a high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering and belongs to the technical field of LU decomposition hardware acceleration, aiming at solving the performance bottleneck and efficiency challenge faced by sparse LU decomposition acceleration on an FPGA. The method comprises the following steps: data and dependency relationship preprocessing, generating a dependency degree list and a dependency trigger mapping list for FPGA runtime scheduling; customizing an FPGA hardware acceleration architecture; updating fine-grained dependency according to a runtime column completion signal; adopting a double-queue task distribution strategy, preferentially distributing high data affinity tasks to corresponding processing unit groups according to a predetermined data affinity mapping relationship; when a local task queue is unavailable, distributing tasks through global task queue rotation; each PEG receives triggered sparse segment tasks, asynchronously loads original matrix data and dependent L / U factors, and completes sparse LU numerical decomposition through parallel multiplication and accumulation and division calculation.