9 results about "Custom hardware" patented technology

The invention discloses a sparse LU decomposition acceleration method for an FPGA (field programmable gate array) with a flow-sensing high-bandwidth memory, belongs to the technical field of LU decomposition hardware acceleration, and aims to solve the problem of performance bottleneck and efficiency challenge faced by sparse LU decomposition on the FPGA. The acceleration method comprises the following steps of data stream preprocessing, wherein matrix data and metadata are stored and packaged based on a sparse storage format; customizing an FPGA hardware accelerator: carrying out HBM channel allocation and collaborative design of a control unit and memory management; parallel data flow management and scheduling are carried out, and sparse LU decomposition is executed; timely data supply is ensured through a multi-stage pipeline prefetching mechanism; and transmitting the task flow and the data flow to a special parallel processing engine for MAC / DIV calculation in combination with a flow sensing synchronous scheduling strategy.

The invention discloses an edge intelligent computing platform device and a data processing method thereof, and belongs to the field of computers, and the device comprises a customized hardware layer and a system software layer. The hardware layer is integrated with a plurality of high-performance GPUs supporting full-precision calculation, a large-capacity memory and an NVMe flash disk to form a strong computing power and storage basis. A system software layer is integrated, such as a Ray distributed framework, and the key improvement of the system is that an NVMe flash disk is configured as overflow storage of a memory, when the memory is insufficient due to processing of mass data or large model reasoning tasks, intermediate data can be automatically overflowed to a high-speed flash memory, and system crash is avoided. Through deep collaborative optimization of hardware and software, the technical problem that a large model cannot be efficiently operated and big data cannot be processed due to resource limitation on an edge side is effectively solved, and full-stack AI reasoning and high-performance distributed data processing at the edge side are realized.

AutoWrap Robotics is an AI-driven software platform enabling autonomous surface treatments—such as PPF, vinyl wraps, ceramic coatings, window tinting, and custom graphics—on vehicles, watercraft, and buildings. It integrates real-time 3D surface mapping, machine learning, and automated multi-tool switching to perform complex tasks with minimal human input. The system supports gantry robots, articulated arms, mobile platforms, and humanoid robots like Tesla Optimus and Figure AI, offering scalable, flexible control. Cloud-based intelligence powers fleet-wide optimization, allowing shared data to continuously improve motion paths, defect correction, and alignment. This ensures consistent quality and precision across high-volume applications, including branded fleets and commercial installations. By uniting AI-driven planning with robotic dexterity, AutoWrap Robotics delivers high-quality film and coating applications in both controlled and remote settings—without requiring custom hardware. This lowers deployment time, reduces operational costs, and positions the platform as a scalable solution for automated surface treatment at industrial scale.

Disclosed is a design process for high-performance specialized machine learning ASICs, optimized for given models and training or inference hardware end use. Modern Large Language Models (LLMs) and deep learning models can require trillions of parameters to be calculated, and the hardware currently used is not tailored for specific models or input datasets. A key tuneable parameter in custom hardware design is the encoding size of numbers. FPGA prototypes are used to test custom number encoding sizes, which informs the final fabricated design which is created with optimized RTL for the encoding size with attention to number register locations, and component sizes. By first analyzing specific machine learning models on prototype FPGA hardware with variable encoding sizes, the optimal number(s) for encoding size for both training and inference can be identified. By experimentally establishing an optimized encoding sizes for the specific computing use case wasted overhead in terms of physical registers is minimized. The approach herein minimizes research and development costs while optimizing encoding sizes for machine learning ASICS.

The application provides a zero-invasion computing power acceleration card information customization system and method, and belongs to the technical field of container cloud platforms. Information customization components are containerized and deployed on each node of the container cloud platform, and the information customization components actively listen to the creation or startup event of a business container. After listening to the event, a custom interception dynamic library, a dynamic library sequence control file, and a custom hardware information database are injected into the business container using an NRI mechanism. The technical solution combines the NRI mechanism with the dynamic link library loading mechanism, the custom hardware information database, and other technologies, so that different computing power acceleration card information acquisition technology paths with different sources and levels can obtain preset hidden information as a return result. Moreover, the solution can access the container cloud platform computing power acceleration card hidden or custom capabilities without modifying user business code or modifying the business container image, and has a wide range of application scenarios.

The invention discloses an I < O > modular configuration system of an upper computer, relates to the technical field of industrial customized upper computer systems, solves the problem that configuration information of traditional configuration software configuration needs to be manually aligned with configuration of a lower computer (actual hardware equipment), and can be automatically aligned with configuration configuration of the upper computer and the lower computer in a one-key manner. According to the invention, multiple configurations can be generated through one-time configuration under multiple redundant configurations (namely multiple master control MCUs), and different MCUs can be adapted. The new I O configuration is changed from traditional source code modification to configuration, and the development efficiency is greatly improved. Through channel-level optimization, the number of used modules is reduced, only required channels and attributes need to be configured, the bandwidth requirement in transmission is greatly reduced, and the data transmission amount is reduced. Different project customization hardware can be quickly realized through configuration, and hardware does not need to be modified. And the configuration file is modified online in real time and becomes effective in real time.

The application discloses a kind of flow-aware high bandwidth memory FPGA sparse LU decomposition acceleration method, belong to LU decomposition hardware acceleration field, to solve the performance bottleneck and efficiency challenge faced by sparse LU decomposition on FPGA acceleration.The acceleration method includes the following steps: data stream preprocessing: based on sparse storage format, matrix data and metadata are stored and packaged;Custom FPGA hardware accelerator: HBM channel allocation, collaborative design of control unit and memory management are carried out;Parallel data stream management and scheduling, execute sparse LU decomposition: ensure timely supply of data through multi-stage pipeline prefetch mechanism;Combine flow-aware synchronous scheduling strategy to transmit task stream and data stream to dedicated parallel processing engine for MAC / DIV calculation.

The invention comprises (i) a compilation method for automatically converting a single-threaded software program into an application-specific supercomputer, and (ii) the supercomputer system structure generated as a result of applying this method. The compilation method comprises: (a) Converting an arbitrary code fragment from the application into customized hardware whose execution is functionally equivalent to the software execution of the code fragment; and (b) Generating interfaces on the hardware and software parts of the application, which (i) Perform a software-to-hardware program state transfer at the entries of the code fragment; (ii) Perform a hardware-to-software program state transfer at the exits of the code fragment; and (iii) Maintain memory coherence between the software and hardware memories. If the resulting hardware design is large, it is divided into partitions such that each partition can fit into a single chip. Then, a single union chip is created which can realize any of the partitions.

The application discloses a high-bandwidth memory FPGA sparse LU decomposition acceleration method based on asynchronous task triggering and belongs to the technical field of LU decomposition hardware acceleration, aiming at solving the performance bottleneck and efficiency challenge faced by sparse LU decomposition acceleration on an FPGA. The method comprises the following steps: data and dependency relationship preprocessing, generating a dependency degree list and a dependency trigger mapping list for FPGA runtime scheduling; customizing an FPGA hardware acceleration architecture; updating fine-grained dependency according to a runtime column completion signal; adopting a double-queue task distribution strategy, preferentially distributing high data affinity tasks to corresponding processing unit groups according to a predetermined data affinity mapping relationship; when a local task queue is unavailable, distributing tasks through global task queue rotation; each PEG receives triggered sparse segment tasks, asynchronously loads original matrix data and dependent L / U factors, and completes sparse LU numerical decomposition through parallel multiplication and accumulation and division calculation.