The invention relates to the technical field of passwords, in particular to an Ascon
algorithm optimization implementation method based on an RISC-V processor, and the method comprises the steps: reconstructing S-box substitution logic through RISC-V
assembly; 64-bit
cyclic shift is optimized through a bit
interleaving technology; fully expanding
assembly codes to eliminate cycle overhead; the
intermediate state and the key are stored in a register. According to the method, the execution efficiency and performance of the Ascon
algorithm on an RISC-V platform are remarkably improved through multiple technical means, redundant bit operation is effectively reduced through reconstruction of S-box substitution logic, calculation
delay is reduced through optimization of bit operation sequences and
multiplexing of temporary variables, 64-bit
cyclic shift operation is decomposed through the bit
interleaving technology, and the calculation efficiency of the
algorithm is improved. The operation is more efficient, the overhead of
loop control is eliminated through an
assembly-level full-expansion technology, unnecessary jump instructions are avoided, the execution speed is further improved, and the problems of insufficient Ascon algorithm performance and resource waste caused by low
utilization rate of the RISC-V architecture are effectively solved.