1376 results about "Cyclic shift" patented technology

A wireless combination time, frequency and spectral shaping communications method that transmits data in convolution unit matrices (data frames) of N×N (N2), where generally either all N2 data symbols or elements are received over N spreading time intervals (each composed of N time slices), or none are. To transmit, each data element is assigned a unique waveform which is derived from a basic waveform of duration N time slices over one spreading time interval, where each basic waveform has a data element specific combination of a time and frequency cyclic shift. At the receiver, the received signal is correlated with the set of all N2 waveforms previously assigned to each data element by a transmitter for that specific time spreading interval, producing a unique correlation score for each one of the N2 data elements. The scores are summed over each data element, and this summation reproduces the data frame.

A low density parity check (LDPC) code that is particularly well adapted for hardware implementation of a belief propagation decoder circuit is disclose& The LDPC code is arranged as a macro matrix (H) whose rows and columns represent block columns and block rows of a corresponding parity check matrix (Hpc). Each non-zero entry corresponds to a permutation matrix, such as a cyclically shifted identity matrix, with the shift corresponding to the position of the permutation matrix entry in the macro matrix. The block columns of the macro matrix are grouped, so that only one column in the macro matrix group contributes to the parity check sum in any given row. The decoder circuitry includes a parity check value estimate memory which may be arranged in banks that can be logically connected in various data widths and depths. A parallel adder generates extrinsic estimates that are applied to parity check update circuitry for generating new parity check value estimates. These parity check value estimates are stored back into the memory, and are forwarded to bit update circuits for updating of probability values for the input nodes. Variations including parallelism, time-sequencing of ultrawide parity check rows, and pairing of circuitry to handle ultrawide code rows, are also disclosed.

A projection display system includes a projection lens assembly that has multiple projection lens elements that are configured to receive light imparted with display information by a pixelated display device. The projection lens elements project the light toward a display screen. A pixel-shifting element is included within the projection lens assembly to cyclically shift between at least two positions within the projection lens assembly to form at a display screen at least two interlaced arrays of pixels. An electromechanical transducer is coupled to the pixel-shifting element to impart on it the cyclic shifting between positions.