212 results about "Phase adjustment" patented technology

The invention relates to a motor encoder protocol real-time conversion device and a minimum delay method, and the method is characterized in that a high-precision clock is arranged in a protocol converter, and the following steps are executed: periodically reading position data from an encoder, recording a latching moment and a position value of the encoder, and calculating a real-time speed; and when a position reading request of the driver is received, recording a request moment, carrying out interpolation calculation by utilizing a set calculation formula, and returning a compensated real-time position to the driver. In order to minimize time delay, a phase-locked loop is adopted, the request time of the driver is taken as a reference, and the reading trigger time sequence of the encoder is synchronized and subjected to phase adjustment, so that the encoder can respond to the next request of the driver as soon as possible after data reading is completed, and the interpolation error is reduced to the minimum. The method effectively solves the problem of position transmission delay when encoders and drivers of different protocols are interconnected, and is suitable for high-precision servo control.

The invention discloses a dynamic balance adjusting device and method for a magnetic suspension fan rotor, and relates to the technical field of self-adaptive adjustment. The method comprises the steps of collecting a suspension bearing displacement signal, a magnetic suspension coil current signal, a machine body vibration acceleration signal, a motor end electromagnetic response signal and a rotor angular displacement parameter, and constructing a rotor operation signal set; performing preprocessing and feature extraction on each signal to obtain four types of feature data; inputting the comprehensive characteristic data into a rotor balance diagnosis model to identify the unbalance state of the rotor; based on an amplitude phase inversion algorithm, solving a virtual counterweight amplitude and a phase adjustment amount, and injecting into a suspension coil to execute adjustment; judging whether dynamic correction is needed or not according to the real-time comprehensive characteristic data, and if yes, generating a dynamic gain coefficient to correct the adjustment parameters and then injecting the adjustment parameters into the suspension coil again; according to the invention, real-time identification and self-adaptive adjustment are carried out on the mass unbalance vibration of the magnetic suspension fan rotor, the operation vibration of the rotor is effectively inhibited, and the balance stability and reliability of the system are improved.

The invention relates to the technical field of phase adjustment, and discloses a synchronous phase modifier phase modulation method adopting a digital twinborn model, and the method comprises the steps: carrying out the modularization processing of a synchronous phase modifier, and obtaining a system module; identifying a power grid topological structure of the power system, and collecting load data, generator data and line parameters of the power system to construct a simulation model of the power system; integrating the system module and the simulation model to obtain an integrated model; performing impedance adjustment on the module integration system to obtain an impedance adjustment model; collecting system data of the synchronous phase modifier, and analyzing control characteristics of the synchronous phase modifier; and executing the phase adjustment reference of the impedance adjustment model by using the control characteristics, obtaining a digital twin model when the model precision meets the preset model precision, analyzing the real-time power data by using the digital twin model, and performing phase adjustment on the power system based on the analysis result. The accuracy of phase adjustment of the synchronous phase modifier can be improved.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

Embodiments of the present invention provide a phase determination method, apparatus, device, and storage medium. The method includes: obtaining a reference phase value of an equidistant processing device; determining a first phase difference corresponding to the product production device when the product production device is operating at a uniform speed; wherein the first phase difference is the difference between the phase value of the product production device and the phase value of the equidistant processing device when the product production device is operating at a uniform speed; obtaining a real-time phase difference between the product production device and the equidistant processing device; and determining a target phase value for the equidistant processing device based on the reference phase value, the first phase difference, and the real-time phase difference. The present invention can adjust the phase of a product so that the product enters the equidistant processing device.

In some embodiments, the phase adjustment circuit includes a clock generator that is configured to generate a sinusoidal clock signal, and may include a variable amplifier that is configured to receive the clock signal output from the clock generator as an input, output an amplitude-adjusted sinusoidal differential clock signal, and output an amplitude-adjusted in-phase signal. The phase adjustment circuit may include an adder that is configured to output a differential signal obtained by adding the in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier, a differential transmission line that includes two transmission lines configured to transmit the differential signal output from the adder, and a terminal circuit that is configured to terminate the differential transmission line where a signal is output from a terminal of any one of the two transmission lines.

The invention discloses a multi-protocol self-adaptive management docking station core board control method and system, and belongs to the technical field of docking station core board monitoring control, and the method comprises the steps: analyzing the stability risk analysis necessity of a docking station core board, analyzing the stability risk score of the docking station core board, and determining the stability risk of the docking station core board; and performing control optimization adjustment on the docking station core board based on the stability risk score of the docking station core board, performing protocol layer clock recovery circuit sampling phase drift analysis, analyzing a protocol layer clock recovery circuit sampling phase drift characterization factor, and executing control adjustment of sampling phase drift. According to the method, the stability and reliability of system operation can be improved, the link retraining frequency is reduced, sampling phase adjustment is optimized, sampling point dislocation, inter-frame phase lock out-of-step and systematic communication faults are prevented under the condition of multi-protocol concurrent working, and long-term stable operation and multi-protocol compatibility of the docking station core board are guaranteed.

A voltage amplitude and phase adjustment apparatus and method, and a computer device and a storage medium. The apparatus comprises: a three-phase multi-winding transformer, a first winding switch and a second winding switch, wherein a primary side of each phase of the three-phase multi-winding transformer comprises a first split winding and a second split winding. A head end of the first split winding is connected to an input end of the present phase, and a tail end of the first split winding is connected to a head end of the second split winding of the present phase by means of the first winding switch, and is connected to the head end of the second split winding of an adjacent phase by means of the second winding switch. By means of controlling the operating states of the winding switches, the connection mode of the split windings is switched, thereby widening the adjustment range of a circuit.

To obtain a phasing processing system, etc., with which, while having the capability of suppressing a noise signal in either of orthogonal axis directions, it is possible to suppress a computing amount in adaptive phasing processing.SOLUTION: The present invention comprises: a subarray division processing device 10 that carries out the process of dividing a plurality of signals pertaining to the detection of a sensor array 200 which is composed by arraying a plurality of sensor 201 in a plurality of orthogonal axis directions and generating as a signal pertaining to the detection of a plurality of subarrays; an elevation phasing processing device 20 that carries out phasing processing on the basis of the signals processed by the subarray division processing device 10; and a horizontal phasing processing device 30 that carries out phasing processing on the basis of the results of phasing processing carried out by the elevation phasing processing device 20. The subarray division processing device 10 includes: a first subarray division processing unit 11 that divides a plurality of signals along some axis direction and generates a first subarray signal; and a second subarray division processing unit 12 that divides the first subarray signal into a plurality of second subarray signals and outputs these to the elevation phasing processing device 20.SELECTED DRAWING: Figure 1

This disclosure relates to a driving circuit, a driving chip, and a display device. The driving circuit includes a clock module and M channel modules. The clock module generates N first clock signals with a phase difference between each pair of signals. Each channel module includes a phase adjustment module, a PWM generation module, and a selection module. The phase adjustment module is connected to the clock module and is used to phase-shift the N first clock signals to obtain N second clock signals. The PWM generation module is connected to the clock module and the phase adjustment module and is used to generate a first PWM signal based on a reference clock signal and a PWM fundamental frequency, and to generate a second PWM signal based on the reference clock signal, a target clock signal, and the PWM fundamental frequency. The selection module is connected to the PWM generation module and is used to select either the first PWM signal or the second PWM signal for output based on a first selection signal, as the target PWM signal. This disclosure simplifies the circuit structure and reduces the circuit footprint.

An antenna array apparatus, and a phase-set configuration method, apparatus, and device. In the present application, the antenna array apparatus comprises a plurality of phase shifters and antenna elements respectively connected to the phase shifters. Each phase shifter is configured with a phase set, the phase set of each phase shifter comprises one or more phase values, and the phase sets of the respective phase shifters are not completely identical. Any one of the phase shifters is configured to adjust the phase of the connected antenna element on the basis of the phase set of the phase shifter. Because the phase values in the phase sets of the respective phase shifters are not completely identical, exhibiting a "non-uniform" characteristic, the phase adjustment made by each phase shifter to the antenna array connected thereto is not concentrated on several identical phase values. The antenna elements connected to the respective phase shifters have different phase values, so that the antenna array apparatus can flexibly adjust the phases of the antenna elements, thereby achieving improved beamforming performance and enhancing the beamforming capability of the antenna array apparatus.

The invention provides a clock synchronization circuit and system which can be applied to the technical field of signal transmission. The clock synchronization circuit comprises: a first node comprising: a first port unit configured to send downlink data to a second node via a downlink according to a first sending reference clock obtained based on an input reference clock, and obtain a first recovery clock according to uplink data returned by the second node via an uplink, performing phase adjustment on the first sending reference clock according to the first phase adjustment step length number; a second port unit configured to output a first measurement reference clock according to an input reference clock; the first phase measurement unit is configured to sample an input reference clock and a first recovery clock according to a first measurement reference clock and output a first phase adjustment step length number; and the second node is configured to obtain the second recovery clock according to the downlink data received by the downlink, and send the uplink data through the uplink according to the second sending reference clock.

Techniques and apparatus for wireless communication are provided. An example method generally includes: transmitting at least one transmit waveform via at least one transmit antenna; receiving a first receive waveform via a first receive antenna; receiving a second receive waveform via a second receive antenna, the first receive waveform and the second receive waveform corresponding to the at least one transmit waveform; determining at least one tuning parameter based on the first received waveform and the second received waveform, wherein the at least one tuning parameter is associated with at least one of a phase difference or a time delay between the first received waveform and the second received waveform; and configuring at least one of a phase adjustment element or a timing adjustment element of a transmit chain coupled to each of the at least one transmit antenna based on the at least one tuning parameter.

The invention discloses a programmable logic chip supporting single-ended clock input and electronic equipment. The chip comprises a function module and a clock module, and the clock module comprises a first clock source used for generating a first single-ended clock signal; the clock selection unit is used for selecting the first single-ended clock signal or the second single-ended clock signal to be output according to a set selection signal; the clock generation unit is used for performing frequency conversion and phase adjustment on the clock signal output by the clock selection unit according to a set configuration signal to generate one or more single-ended output clocks; the clock distribution unit is used for outputting one or more single-ended output clocks generated by the clock generation unit to corresponding functional modules according to a set control signal; and the clock control unit is used for generating a selection signal, a configuration signal and a control signal according to preset configuration information or externally input configuration information. According to the integrated clock module, the problem that an existing programmable logic chip depends on an external clock chip is solved.

An antenna device includes an array antenna; a phase adjuster; and circuitry configured to acquire, based on a second position, an elevation angle of a projected position that is obtained by projecting a first position of a marker included in an image onto a second plane including a first axis and a third axis, the elevation angle being relative to the third axis of the second plane. The circuitry is configured to control the phase adjuster such that a direction of a beam, emitted by the array antenna based on retrieved phase data, defines the elevation angle for the second plane, the phase data relating to elevation angles that are within a predetermined included angle range.

This invention relates to the field of microgrid control technology and discloses a method and system for synchronizing microgrid inverters based on satellite time synchronization. The method includes at least: receiving a satellite time synchronization signal and preprocessing it to obtain a global time reference signal; acquiring real-time operating parameters of each inverter within the microgrid and calculating the real-time phase offset of each inverter based on the global time reference signal and each real-time operating parameter; generating a synchronization phase angle for the corresponding inverter based on each real-time phase offset; acquiring real-time interaction data of each inverter and updating each initial phase adjustment command based on the real-time interaction data and the global synchronization phase angle to obtain a target phase adjustment command for the corresponding inverter; and adjusting the output voltage of the corresponding inverter using each target phase adjustment command. This invention improves the synchronization control accuracy and operational stability of multi-inverter clusters in microgrids.

A voltage amplitude and phase adjustment apparatus and method, and a computer device and a storage medium. The apparatus comprises: a three-phase multi-winding transformer, a first winding switch and a second winding switch, wherein a primary side of each phase of the three-phase multi-winding transformer comprises a first split winding and a second split winding. Ahead end of the first split winding is connected to an input end of the present phase, and a tail end of the first split winding is connected to a head end of the second split winding of the present phase by means of the first winding switch, and is connected to the head end of the second split winding of an adjacent phase by means of the second winding switch. By means of controlling the operating states of the winding switches, the connection mode of the split windings is switched, thereby widening the adjustment range of a circuit.

The invention relates to a phase adjusting circuit and method and a distance measuring device. The phase adjustment circuit comprises: at least one adjustment unit configured to adjust an input signal according to an initial gain coefficient to generate an adjustment signal; and changing a gain coefficient for adjusting the input signal in response to a gate control signal; wherein when the adjusting unit has different gain coefficients, the cut-off frequencies corresponding to the gain coefficients are the same; and the control unit is coupled with the adjusting unit and is configured to generate the gating control signal to the adjusting unit according to the adjusting signal and a preset signal. By adopting the scheme, the phase delay in the dynamic range can be reduced, and the distance measurement precision is improved.

The invention provides an acoustic transducer module and an acoustic transducer module directivity control method, and relates to the technical field of acoustic equipment. The module comprises a module rear cavity, a phase adjusting circuit, a plurality of sound production units and a module front cavity, the module rear cavity is used for accommodating a plurality of sound production units and a phase adjusting circuit; the phase adjustment circuit comprises at least one signal input end and a plurality of phase adjustment branches, the signal input end is used for receiving an input electric signal, the plurality of phase adjustment branches are respectively used for adjusting the phase of the electric signal, and each phase adjustment branch is respectively connected to at least one sound production unit in the plurality of sound production units; the plurality of sound production units are used for converting the received electric signals into sound signals; the module front cavity comprises a radiation port which is used for converging and radiating sound signals to the outside. According to the invention, the change of the sound phase can be realized through the phase adjustment circuit in a hardware structure manner, so that the directivity of sound radiation is controlled without depending on any complex algorithm or high-computing-power chip.

A high-frequency front-end circuit (10A) that has the following features: a triplexer circuit (20A) comprising a first transmit filter (211), a receive filter (221) and a second transmit filter (212), wherein one end of the first transmit filter (211) and one end of the receive filter (221) and one end of the second transmit filter (212) are connected to each other by a common junction; a low-noise amplifier (LNA); and a phase adjustment circuit (30A) that is connected between the receive filter (221) and the low-noise amplifier (LNA), where the first transmit filter (211) is set such that a fundamental frequency of a first transmit signal in a first communication band falls into a passband of the first transmit filter (211), the receive filter (221) is set such that a fundamental frequency of a received signal in the first communication band falls into a passband of the receive filter (221), the second transmit filter (212) is set such that a fundamental frequency of a second transmit signal in a second communication band, which differs from the first communication band, falls into a passband of the second transmit filter (212), where the transmission of the second transmit signal and the reception of the received signal are carried out simultaneously, wherein, assuming that a Smith chart is divided into four quadrants by a first line representing pure resistance and by a second line connecting points along an outer periphery of the Smith chart, each with a phase of 90°, and a reference impedance point, the phase adjustment circuit (30A) performs a phase adjustment such that, at a harmonic frequency of the second transmit signal, a quadrant in which a phase of the low-noise amplifier (LNA) is present when viewed from the receive filter (221), and a quadrant in which a phase is present when viewed from the low-noise amplifier (LNA) towards the receive filter (221), are not in a conjugate relationship.

The invention discloses a broadband multichannel amplitude-phase error real-time compensation and synthesis method and system, relates to the technical field of broadband communication, and ensures that the amplitude-phase error of a full frequency band can be detected by injecting a broadband standard pilot signal which is completely matched with the bandwidth of a working signal; the standard pilot signal and the working signal are transmitted in the same path, and the amplitude-phase change of the standard pilot signal can truly reflect the error state of the working signal, so that the problem that the narrow-band pilot cannot cover the full-band error is solved; by monitoring the amplitude-phase error change rate, the updating period of compensation parameters is adaptively adjusted, and it is ensured that the compensation response speed is always higher than the error change speed; a real-time compensation parameter is generated based on the dynamic amplitude-phase error spectrum, so that the problem of lag failure of an offline parameter is avoided; a multi-frequency-point parallel processing mechanism is adopted, a broadband working signal is decomposed into a plurality of frequency components to synchronously execute amplitude-phase adjustment, the adjustment time consumption is consistent with that of a single-path signal, and compared with a traditional serial adjustment mode, the efficiency is improved, and the real-time processing requirement of the broadband signal is met.

The application provides a phase shifter phase adjusting device and a base station antenna. The phase shifter phase adjusting device comprises a first screw rod, a first nut seat, a first bearing, a second screw rod, a first sliding sleeve and a second sliding sleeve. The first end of the first screw rod is drivingly connected to a driving unit. The first nut seat is screwed on the outside of the first screw rod. The inner ring of the first bearing is mounted on the first nut seat. The outer ring of the first bearing is mounted on the second screw rod. The second screw rod is slidably sleeved on the outside of the first screw rod. The first screw rod has a first guide groove on the outside. The second screw rod has a first guide rib on the inside. The first sliding sleeve is sleeved on the outside of the first screw rod. The second sliding sleeve is sleeved on the outside of the second screw rod. The second sliding sleeve is slidably sleeved in the first sliding sleeve. The first nut seat is fixedly connected to the second sliding sleeve. The first sliding sleeve has a first guide part on the inside. The second sliding sleeve has a second guide part on the outside. The phase shifter phase adjusting device and the base station antenna are compact in structure and small in space occupation.

The present invention relates to a steering system that well controls a reaction force. This steering system is an electric power steering system provided with a reaction force device and a steering device. In this steering system, a reaction force is controlled on the basis of a steering angle deviation, which is the difference between a target steering angle and an actual steering angle. In addition, the steering angle deviation is a phase-adjusted value. As a result, it is possible to suppress a delay in the influence of a change in the steering angle deviation on the reaction force, and to enable a driver to well know the steering state of the wheels by means of the reaction force applied to the steering operation member. And the reaction force can be well controlled.

This invention discloses a displacement sensor circuit for monitoring settlement in a water diversion tunnel. The sensor circuit includes a compensation circuit, a monitoring circuit, a phase adjustment circuit, and a gain amplification circuit. The monitoring circuit is connected to the compensation circuit, the phase adjustment circuit, and the gain amplification circuit. The compensation circuit is connected to the phase adjustment circuit and the gain amplification circuit. The phase adjustment circuit or the gain amplification circuit adjusts the phase or amplitude of the signal output by the detection probe based on the type of the compensation signal, either forward or reverse. The monitoring circuit monitors the DC voltage signal output by the detector before and after compensation and outputs a switching signal based on the monitoring result. The compensation circuit outputs a compensation signal.

A radio wave control system includes a phase adjustment plate that transmits a radio wave from a second main surface to a first main surface and focuses the radio wave on a focal point; and a reflection plate installed at a position irradiated with the radio wave transmitted through the phase adjustment plate.

The application relates to a dual-polarized low-temperature compact receiving front-end device capable of realizing rapid phase adjustment, which comprises a vacuum sealing window, a heat insulation waveguide, a polarization network, a waveguide coupler, a low-temperature isolator, a low-temperature amplifier and a vacuum refrigeration system. The vacuum refrigeration system comprises a cold head, a cold plate, an expander, a vacuum Dewar and a cold screen. Different electromagnetic wave transmission forms are adopted to form dual-polarized signals, the signals are transmitted to a rectangular waveguide form, the rectangular waveguide transmission distance difference is utilized, a rectangular waveguide diaphragm is added for the adjustment of the phase difference of the dual-polarized signals, the waveguide coupler and the polarizer are only needed to be disassembled, the waveguide diaphragm with the corresponding thickness is added, and the screw is fixed back, so that the adjustment of the phase difference between the dual-polarized signals can be rapidly and effectively realized, other electrical performances are not affected, and the original assembly relationship is ensured.

The invention relates to an interface circuit of a memory, a retraining method, a memory controller, a device and a non-transient storage medium. The interface circuit comprises a receiving module, an adjustable delay module, a sampling module and a phase adjustment module, the receiving module is respectively connected with a first input end of the sampling module and a first end of the adjustable delay module, a second end of the adjustable delay module is connected with a second input end of the sampling module, and an output end of the sampling module is connected with an input end of the phase adjusting module; the output end of the phase adjusting module is connected with the control end of the adjustable delay module; wherein the receiving module is used for receiving a data signal and a clock reference signal, inputting the data signal to the sampling module, delaying the clock reference signal through the adjustable delay module, and inputting the delayed clock reference signal to the sampling module; and the phase adjustment module is used for generating a phase adjustment signal according to the output signal of the sampling module and adjusting the adjustable delay of the adjustable delay module according to the phase adjustment signal.

The invention relates to a DAC clock duty ratio and quadrature phase calibration circuit and a digital regulation and control method. The digital regulation and control method comprises the steps that a four-phase clock generation circuit (1) generates four paths of fixed phase offset clocks based on differential signals; the DCC duty ratio adjusting circuit (2) responds to the duty ratio adjusting signal to adjust the duty ratio of the four paths of fixed phase offset clocks; the QEC phase adjusting circuit (3) responds to the phase adjusting signals to correct the quadrature phases of the four duty ratio adjusting signals; the one-to-three inverter link (4) shapes the four orthogonal clock signals, performs signal shaping processing and outputs a calibration clock; the detection circuit (5) analyzes the calibration clock to generate a detection result; and the digital regulation and control circuit (6) dynamically generates a duty ratio adjustment signal and a phase adjustment signal according to a detection result, so that closed-loop control is formed, and synchronous optimization of the duty ratio and the quadrature phase is realized. The circuit can solve the problems of duty ratio distortion and phase deviation between two groups of I / Q signals existing in the generated four-path fixed phase offset clock.

A method, system, and storage medium for optimizing the layout of blade vibration monitoring sensors include: S100, obtaining geometric constraints and vibration assessment strategy constraints for the sensor layout; S200, generating sensor phase sequences based on geometric constraints; S300, determining multiple vibration orders to be analyzed; S400, for each vibration order, constructing a coefficient matrix for vibration response estimation based on the sensor phase sequence and the total number of cycles to be calculated; S500, for each vibration order, calculating the condition number of the product of the coefficient matrix and its transpose; S600, selecting the maximum value of the condition number as the evaluation parameter of the current sensor phase sequence; S700, adjusting the sensor phase sequence based on the phase adjustment step size under geometric constraints, and re-executing S300-S600; S800, selecting the minimum value among all evaluation parameters and outputting its corresponding sensor phase sequence as the optimization result.

The application relates to a digital frequency synthesizer, a signal compensation method, an SOC chip and electronic equipment, and belongs to the integrated circuit field.The digital frequency synthesizer comprises a digital frequency synthesis unit, a phase compensation unit and a phase adjustment unit; the digital frequency synthesis unit is used for generating a first clock signal with a first specified duty cycle according to an externally input first digital phase enable binary code and a multi-path initial phase clock signal; the phase compensation unit is used for generating a target compensation clock signal with a corresponding phase width according to required phase accuracy; and the phase adjustment unit is used for generating an output clock signal with a second specified duty cycle according to the target compensation clock signal and the first clock signal. The first clock signal is compensated by generating the target compensation clock signal with the required phase width, so that a clock signal with an arbitrary duty cycle can be output, and the problem that the existing digital frequency synthesizer can only output a clock signal with a specific frequency is effectively improved.