323 results about "Phase adjustment" patented technology

Aspects of the subject disclosure may include, for example, obtaining data regarding interference detected in a received communication signal, and performing phase adjusting for one or more radiating elements of an antenna system such that an impact of the interference on the antenna system is minimized. Other embodiments are disclosed.

The invention provides a communication method and a related device, which can realize protection of user privacy in a perception scene. The method comprises the steps that a first device and a second device determine the type of a target scrambling function corresponding to a first sensing scene and parameters included in the target scrambling function; the first device generates a first signal and a second signal, the second signal is obtained by performing phase adjustment on the first signal based on a target scrambling function, and the target scrambling function is determined based on the type of the target scrambling function and the parameter; the first device outputs a first signal and a second signal, sends first information through a first antenna corresponding to the first device, and sends the second signal through a second antenna corresponding to the first device; correspondingly, the second device receives the signal from the first device, and obtains a sensing result based on the received signal and the target scrambling function.

The present disclosure provides an antenna and electronic device, and belongs to the field of communication technology. The antenna includes a feed layer, a phase adjustment layer, and a radiation layer, wherein the feed layer is configured to transmit a microwave signal to the phase adjustment layer; the phase adjustment layer is configured to phase-shift the microwave signal by a preset phase shift amount; and the radiation layer is configured to radiate the microwave signal phase-shifted by the phase adjustment layer; the radiation layer includes at least one first radiation patch.

The invention relates to a motor encoder protocol real-time conversion device and a minimum delay method, and the method is characterized in that a high-precision clock is arranged in a protocol converter, and the following steps are executed: periodically reading position data from an encoder, recording a latching moment and a position value of the encoder, and calculating a real-time speed; and when a position reading request of the driver is received, recording a request moment, carrying out interpolation calculation by utilizing a set calculation formula, and returning a compensated real-time position to the driver. In order to minimize time delay, a phase-locked loop is adopted, the request time of the driver is taken as a reference, and the reading trigger time sequence of the encoder is synchronized and subjected to phase adjustment, so that the encoder can respond to the next request of the driver as soon as possible after data reading is completed, and the interpolation error is reduced to the minimum. The method effectively solves the problem of position transmission delay when encoders and drivers of different protocols are interconnected, and is suitable for high-precision servo control.

The invention provides a chip testing method and device, and belongs to the technical field of chip testing. The method comprises the steps that an intermediate clock with the frequency the same as that of an input channel-associated clock in a test excitation signal is generated through a high-frequency clock signal, and the frequency of the high-frequency clock signal is larger than that of the input channel-associated clock; adjusting the phase of the intermediate clock according to the time sequence parameter of each tested chip, and generating a phase correction associated clock; and replacing the input associated clock based on the phase correction associated clock to update the test excitation signal so as to test each tested chip by using the updated test excitation signal. Independent time sequence compensation of each chip is achieved through high-frequency signal dynamic high-precision phase adjustment, the limitation of a traditional single time sequence parameter is broken through, and flexible consideration of the test rate and the test number is achieved. From the aspect of deployment, the design process and the file format of the original test system do not need to be modified, the compatibility is good, the universality and the deployment efficiency are improved, and the deployment cost is reduced.

The invention belongs to the technical field of robots, and discloses a differential ball joint which comprises a shell, a first input bevel gear, a second input bevel gear, an output bevel gear and a phase adjusting assembly, and the first input bevel gear, the second input bevel gear and the output bevel gear are all rotationally arranged on the shell; the first input bevel gear and the second input bevel gear are both meshed with the output bevel gear, and the axis of the output bevel gear is perpendicular to the axis of the first input bevel gear and the axis of the second input bevel gear. The phase adjusting assembly is used for adjusting phases of the first input bevel gear and the second input bevel gear, so that gear teeth in the first input bevel gear and the second input bevel gear make contact with tooth surfaces of two adjacent gear teeth in the output bevel gear, and therefore transmission gaps between the first input bevel gear and the output bevel gear and between the second input bevel gear and the output bevel gear are eliminated. The transmission stability is improved, and the transmission noise is reduced.

The invention provides a three-phase balance user phase adjustment method based on multi-objective optimization control, and relates to the technical field of power system control. According to the technical scheme provided by the invention, after the phase distribution results under different constraint conditions are calculated, the problem of deterioration of other indexes possibly caused by single target optimization can be avoided by constructing the multi-objective function containing the indexes. And meanwhile, multi-objective function value calculation and comparison are carried out on each phase distribution scheme, and the phase distribution scheme with the minimum multi-objective function value is selected as the optimal scheme, so that the overall optimality and the balance of each technical index can be considered. Compared with a phase adjustment mode in which only a single-phase meter or a three-phase meter is considered in the prior art, the phase adjustment scheme provided by the invention adopts a multi-objective function to realize trade-off optimization among indexes for the condition that the single-phase meter and the three-phase meter exist at the same time, so that accurate phase adjustment can be realized, and the load balancing effect is improved.

The invention discloses a dynamic balance adjusting device and method for a magnetic suspension fan rotor, and relates to the technical field of self-adaptive adjustment. The method comprises the steps of collecting a suspension bearing displacement signal, a magnetic suspension coil current signal, a machine body vibration acceleration signal, a motor end electromagnetic response signal and a rotor angular displacement parameter, and constructing a rotor operation signal set; performing preprocessing and feature extraction on each signal to obtain four types of feature data; inputting the comprehensive characteristic data into a rotor balance diagnosis model to identify the unbalance state of the rotor; based on an amplitude phase inversion algorithm, solving a virtual counterweight amplitude and a phase adjustment amount, and injecting into a suspension coil to execute adjustment; judging whether dynamic correction is needed or not according to the real-time comprehensive characteristic data, and if yes, generating a dynamic gain coefficient to correct the adjustment parameters and then injecting the adjustment parameters into the suspension coil again; according to the invention, real-time identification and self-adaptive adjustment are carried out on the mass unbalance vibration of the magnetic suspension fan rotor, the operation vibration of the rotor is effectively inhibited, and the balance stability and reliability of the system are improved.

A phase adjustment circuit (11) of a received signal quality monitor is capable of performing phase scanning of a sampling clock signal (phi e) of a reference sampler in a phase range that is several times the unit interval (UI) of a serial data signal. A first synchronization circuit (13A) receives a first output signal of one sampler included in the plurality of data receiving samplers and a second output signal of the reference sampler (SMe). A first output signal and a second output signal synchronously output from the first synchronization circuit (13A) are input to a comparison logic circuit (15), and the comparison logic circuit (15) outputs a comparison result relating to the quality of the received signal.

The invention relates to the technical field of phase adjustment, and discloses a synchronous phase modifier phase modulation method adopting a digital twinborn model, and the method comprises the steps: carrying out the modularization processing of a synchronous phase modifier, and obtaining a system module; identifying a power grid topological structure of the power system, and collecting load data, generator data and line parameters of the power system to construct a simulation model of the power system; integrating the system module and the simulation model to obtain an integrated model; performing impedance adjustment on the module integration system to obtain an impedance adjustment model; collecting system data of the synchronous phase modifier, and analyzing control characteristics of the synchronous phase modifier; and executing the phase adjustment reference of the impedance adjustment model by using the control characteristics, obtaining a digital twin model when the model precision meets the preset model precision, analyzing the real-time power data by using the digital twin model, and performing phase adjustment on the power system based on the analysis result. The accuracy of phase adjustment of the synchronous phase modifier can be improved.

A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value. The clock generator circuit may be implemented in a clock domain of a system along with one or more other clock generator circuits that each generate an output clock based on a reference clock generated by a reference clock source, such as a phase-locked loop.

Embodiments of the present invention provide a phase determination method, apparatus, device, and storage medium. The method includes: obtaining a reference phase value of an equidistant processing device; determining a first phase difference corresponding to the product production device when the product production device is operating at a uniform speed; wherein the first phase difference is the difference between the phase value of the product production device and the phase value of the equidistant processing device when the product production device is operating at a uniform speed; obtaining a real-time phase difference between the product production device and the equidistant processing device; and determining a target phase value for the equidistant processing device based on the reference phase value, the first phase difference, and the real-time phase difference. The present invention can adjust the phase of a product so that the product enters the equidistant processing device.

A transmission line phase shifter, a chip, and a radar sensor are provided. The transmission line phase shifter includes at least one transmission line phase-shifting unit. At a calibration stage, a preset number of transmission line phase-shifting units are configured to be in a state of a first phase or in a state of a second phase and configured to output an output RF signal, such that phase calibration information of each transmission line phase-shifting unit is determinable. At an operation stage, the phase adjusting circuit of the respective transmission line phase-shifting unit is configured to receive a corresponding phase shifting control signal and to adjust the respective transmission line phase-shifting unit, to enable the respective transmission line phase-shifting unit to shift a phase of an input RF signal by a calibrated first phase or a calibrated second phase.

In some embodiments, the phase adjustment circuit includes a clock generator that is configured to generate a sinusoidal clock signal, and may include a variable amplifier that is configured to receive the clock signal output from the clock generator as an input, output an amplitude-adjusted sinusoidal differential clock signal, and output an amplitude-adjusted in-phase signal. The phase adjustment circuit may include an adder that is configured to output a differential signal obtained by adding the in-phase signal to each of a positive phase side and a negative phase side of the differential clock signal output from the variable amplifier, a differential transmission line that includes two transmission lines configured to transmit the differential signal output from the adder, and a terminal circuit that is configured to terminate the differential transmission line where a signal is output from a terminal of any one of the two transmission lines.

The invention belongs to the technical field of radar interference, and particularly discloses a retrodirective array for cross-eye interference, which comprises at least two antennas, the antennas are configured to receive input signals and forward interference signals based on the input signals, and each antenna is provided with a transponder assembly coupled with the antenna. The transponder assembly can modify the phase of a forwarding signal thereof according to a reference signal, that is, all transponder assembly configurations except at least one transponder assembly can invert the phase of the forwarding signal of an input signal of a coupled antenna thereof according to the reference signal, so as to ensure that all signals are in phase at the source of the input signal. At least one transponder component is configured to introduce at least one phase adjustment to a forwarded signal such that the signal forwarded from the antenna has a phase difference of 170 DEG to 190 DEG and an amplitude difference of less than 3 dB at an input signal source, eliminate inherent delays in a Van Atta cross-eye jammer, introduce angle errors in a threat radar, and achieve conditions required for cross-eye jamming.

The invention discloses a multi-protocol self-adaptive management docking station core board control method and system, and belongs to the technical field of docking station core board monitoring control, and the method comprises the steps: analyzing the stability risk analysis necessity of a docking station core board, analyzing the stability risk score of the docking station core board, and determining the stability risk of the docking station core board; and performing control optimization adjustment on the docking station core board based on the stability risk score of the docking station core board, performing protocol layer clock recovery circuit sampling phase drift analysis, analyzing a protocol layer clock recovery circuit sampling phase drift characterization factor, and executing control adjustment of sampling phase drift. According to the method, the stability and reliability of system operation can be improved, the link retraining frequency is reduced, sampling phase adjustment is optimized, sampling point dislocation, inter-frame phase lock out-of-step and systematic communication faults are prevented under the condition of multi-protocol concurrent working, and long-term stable operation and multi-protocol compatibility of the docking station core board are guaranteed.

The invention discloses an audio signal phase adjustment method, device and equipment and a storage medium, and relates to the technical field of vehicle-mounted loudspeakers, and the method comprises the steps: carrying out the frequency division processing, delay compensation and equalizer adjustment of an input audio signal, and obtaining an initial processing signal; outputting the initial processing signal to a target loudspeaker, and measuring a current frequency response curve of the target loudspeaker; determining an all-pass filter coefficient and a maximum phase filter coefficient according to the frequency division point, the wave crest and the wave trough of the current frequency response curve; performing phase adjustment on the initial processing signal based on the all-pass filter coefficient or the maximum phase filter coefficient to obtain an adjusted audio signal; and outputting the audio signal to the target loudspeaker, and returning to the step of measuring the current frequency response curve of the target loudspeaker until the current frequency response curve meets a preset flatness requirement, thereby completing phase adjustment. Phase distortion at the frequency division point and the wave crest and the wave trough of the frequency response curve can be improved through phase adjustment, so that the frequency response curve of the loudspeaker is optimized.

A voltage amplitude and phase adjustment apparatus and method, and a computer device and a storage medium. The apparatus comprises: a three-phase multi-winding transformer, a first winding switch and a second winding switch, wherein a primary side of each phase of the three-phase multi-winding transformer comprises a first split winding and a second split winding. A head end of the first split winding is connected to an input end of the present phase, and a tail end of the first split winding is connected to a head end of the second split winding of the present phase by means of the first winding switch, and is connected to the head end of the second split winding of an adjacent phase by means of the second winding switch. By means of controlling the operating states of the winding switches, the connection mode of the split windings is switched, thereby widening the adjustment range of a circuit.

To obtain a phasing processing system, etc., with which, while having the capability of suppressing a noise signal in either of orthogonal axis directions, it is possible to suppress a computing amount in adaptive phasing processing.SOLUTION: The present invention comprises: a subarray division processing device 10 that carries out the process of dividing a plurality of signals pertaining to the detection of a sensor array 200 which is composed by arraying a plurality of sensor 201 in a plurality of orthogonal axis directions and generating as a signal pertaining to the detection of a plurality of subarrays; an elevation phasing processing device 20 that carries out phasing processing on the basis of the signals processed by the subarray division processing device 10; and a horizontal phasing processing device 30 that carries out phasing processing on the basis of the results of phasing processing carried out by the elevation phasing processing device 20. The subarray division processing device 10 includes: a first subarray division processing unit 11 that divides a plurality of signals along some axis direction and generates a first subarray signal; and a second subarray division processing unit 12 that divides the first subarray signal into a plurality of second subarray signals and outputs these to the elevation phasing processing device 20.SELECTED DRAWING: Figure 1

This disclosure relates to a driving circuit, a driving chip, and a display device. The driving circuit includes a clock module and M channel modules. The clock module generates N first clock signals with a phase difference between each pair of signals. Each channel module includes a phase adjustment module, a PWM generation module, and a selection module. The phase adjustment module is connected to the clock module and is used to phase-shift the N first clock signals to obtain N second clock signals. The PWM generation module is connected to the clock module and the phase adjustment module and is used to generate a first PWM signal based on a reference clock signal and a PWM fundamental frequency, and to generate a second PWM signal based on the reference clock signal, a target clock signal, and the PWM fundamental frequency. The selection module is connected to the PWM generation module and is used to select either the first PWM signal or the second PWM signal for output based on a first selection signal, as the target PWM signal. This disclosure simplifies the circuit structure and reduces the circuit footprint.

An antenna array apparatus, and a phase-set configuration method, apparatus, and device. In the present application, the antenna array apparatus comprises a plurality of phase shifters and antenna elements respectively connected to the phase shifters. Each phase shifter is configured with a phase set, the phase set of each phase shifter comprises one or more phase values, and the phase sets of the respective phase shifters are not completely identical. Any one of the phase shifters is configured to adjust the phase of the connected antenna element on the basis of the phase set of the phase shifter. Because the phase values in the phase sets of the respective phase shifters are not completely identical, exhibiting a "non-uniform" characteristic, the phase adjustment made by each phase shifter to the antenna array connected thereto is not concentrated on several identical phase values. The antenna elements connected to the respective phase shifters have different phase values, so that the antenna array apparatus can flexibly adjust the phases of the antenna elements, thereby achieving improved beamforming performance and enhancing the beamforming capability of the antenna array apparatus.

The invention provides a clock synchronization circuit and system which can be applied to the technical field of signal transmission. The clock synchronization circuit comprises: a first node comprising: a first port unit configured to send downlink data to a second node via a downlink according to a first sending reference clock obtained based on an input reference clock, and obtain a first recovery clock according to uplink data returned by the second node via an uplink, performing phase adjustment on the first sending reference clock according to the first phase adjustment step length number; a second port unit configured to output a first measurement reference clock according to an input reference clock; the first phase measurement unit is configured to sample an input reference clock and a first recovery clock according to a first measurement reference clock and output a first phase adjustment step length number; and the second node is configured to obtain the second recovery clock according to the downlink data received by the downlink, and send the uplink data through the uplink according to the second sending reference clock.

Techniques and apparatus for wireless communication are provided. An example method generally includes: transmitting at least one transmit waveform via at least one transmit antenna; receiving a first receive waveform via a first receive antenna; receiving a second receive waveform via a second receive antenna, the first receive waveform and the second receive waveform corresponding to the at least one transmit waveform; determining at least one tuning parameter based on the first received waveform and the second received waveform, wherein the at least one tuning parameter is associated with at least one of a phase difference or a time delay between the first received waveform and the second received waveform; and configuring at least one of a phase adjustment element or a timing adjustment element of a transmit chain coupled to each of the at least one transmit antenna based on the at least one tuning parameter.

The invention discloses a programmable logic chip supporting single-ended clock input and electronic equipment. The chip comprises a function module and a clock module, and the clock module comprises a first clock source used for generating a first single-ended clock signal; the clock selection unit is used for selecting the first single-ended clock signal or the second single-ended clock signal to be output according to a set selection signal; the clock generation unit is used for performing frequency conversion and phase adjustment on the clock signal output by the clock selection unit according to a set configuration signal to generate one or more single-ended output clocks; the clock distribution unit is used for outputting one or more single-ended output clocks generated by the clock generation unit to corresponding functional modules according to a set control signal; and the clock control unit is used for generating a selection signal, a configuration signal and a control signal according to preset configuration information or externally input configuration information. According to the integrated clock module, the problem that an existing programmable logic chip depends on an external clock chip is solved.

The present invention belongs to the field of battery detection, and discloses a synchronous detection sampling circuit and method for phase compensation. The synchronous detection sampling circuit for phase compensation includes a sampling and amplifying circuit, an RC phase adjustment circuit, a signal amplifying circuit, an analog switch and a low-pass filtering circuit, a temperature monitoring signal transmitting circuit, an arithmetic circuit, and an analog-to-digital conversion circuit. The analog switch and the low-pass filtering circuit are connected to the arithmetic circuit, the signal amplifying circuit, and the RC phase adjustment circuit. The signal amplifying circuit is connected to the sampling and amplifying circuit. The arithmetic circuit is connected to the temperature monitoring signal transmitting circuit and the analog-to-digital conversion circuit. The present invention optimizes the processing process of the signal to be measured by using the synchronous detection method of the tester, and improves the convenience and reliability of test debugging.

According to an embodiment of the present disclosure, a multi-phase clock calibration apparatus and method for a SerDes transmitter are provided. The apparatus includes a replicated output driver stage for generating a replicated signal proportional to an output signal of the output driver stage; a filter connected to an output end of the replicated output driver stage; an analog-to-digital converter for receiving the filtered analog signal output by the filter and converting the filtered analog signal into a digital signal; a phase error detection unit for calculating an autocorrelation function between adjacent output signals and generating a phase adjustment signal according to a comparison result of the autocorrelation function; and a clock phase adjustment unit for adjusting a phase of a multi-phase clock signal according to the phase adjustment signal, where the multi-phase clock signal is used to drive a multiplexer of the SerDes transmitter to serialize parallel digital information. The embodiment of the present disclosure can ensure the accuracy of the output signal of the SerDes transmitter by adjusting the multi-phase clock signal.

An antenna device includes an array antenna; a phase adjuster; and circuitry configured to acquire, based on a second position, an elevation angle of a projected position that is obtained by projecting a first position of a marker included in an image onto a second plane including a first axis and a third axis, the elevation angle being relative to the third axis of the second plane. The circuitry is configured to control the phase adjuster such that a direction of a beam, emitted by the array antenna based on retrieved phase data, defines the elevation angle for the second plane, the phase data relating to elevation angles that are within a predetermined included angle range.

The invention provides an antenna phase adjusting device and antenna equipment, relates to the technical field of communication, and is used for solving the problems that in the prior art, a phase adjusting device is complex in structure, low in reliability and high in cost, the device comprises at least two driving shafts and a gear shifting module, the gear shifting module comprises a moving structure and a rotating structure, the moving structure is in transmission fit with the at least two driving shafts and is used for selectively driving the phase shifter slip sheet corresponding to any driving shaft to perform phase adjustment; wherein the rotating structure is rotationally connected with the moving structure, the rotating structure is used for rotating to pass through different transmission positions, and the moving structure is driven to be in transmission fit with one of the at least two driving shafts on the different transmission positions. The antenna can simplify the structure, improve the reliability and reduce the cost, thereby meeting the high requirements of the communication base station on the antenna performance.

The invention relates to the technical field of spacecraft on-orbit service, in particular to a GEO multi-spacecraft cooperative on-orbit refueling task planning method, which is characterized by comprising the following steps of: 1, establishing an orbit transfer model based on a surface and phase modulation maneuvering method, and revealing a relationship between spacecraft orbit transfer speed increment and time; 2, establishing a double-layer optimization model for collaborative on-orbit refueling task planning, and determining a task time range on the basis of minimum fuel consumption; 3, efficiently solving the optimization model by utilizing a double-layer optimization algorithm, wherein a branch and bound algorithm and a fast elite multi-objective genetic algorithm are respectively adopted in an inner layer and an outer layer; according to the method, the limitation of a traditional many-to-many on-orbit refueling strategy is broken through, multiple service spacecrafts are allowed to cooperate to complete the same refueling task, the fuel consumption and time cost of the on-orbit refueling task are reduced, the result is close to the Pareto optimal state, the constraints of multiple aspects such as dynamic scheduling and effective load limitation are fully considered, and the method is suitable for large-scale popularization and application. And actual engineering requirements are met.

The invention relates to a self-adaptive clock phase adjustment SPI host and method based on an FPGA, and belongs to the technical field of electronic engineering, the self-adaptive clock phase adjustment SPI host based on the FPGA comprises a data receiving module used for receiving test data and generating a test result based on the accuracy of the test data; the result storage module is used for storing the test result in the target register; the phase calculation module is used for calculating an optimal phase based on the test result in the target register; the phase control module is used for controlling the phase-locked loop to output an optimal phase clock based on the optimal phase; and the clock selector is used for outputting the optimal phase clock to a clock pin of the SPI interface. According to the adaptive clock phase adjustment SPI host based on the FPGA provided by the invention, by introducing an adaptive clock phase adjustment technology, the accuracy of data transmission is ensured, and the communication speed of the SPI host is remarkably improved.