6 results about "Timing generator" patented technology

An exposure control unit, a timing generator unit, a metering unit, and a pulse control unit are provided. The exposure control unit generates a signal defining multiple second exposure periods contained within a first exposure period, which corresponds to a frame, each of which is shorter than the first exposure period. The timing generator unit generates a pulse signal defining the timing information within each second exposure period. The metering unit counts the pulse signal at or after the first photon capture in the second exposure period, based on the pulse signal generated by the timing generator unit. The pulse control unit performs pulse counting in a second exposure period following the first, based on a value from the metering unit.

Embodiments of a radio frequency (RF) controller for a 5G modem, a 5G modem, and a method for operating an RF controller of a 5G modem are disclosed. In an embodiment, an RF controller for a 5G modem includes a timing generator configured to generate a symbol clock signal, a memory unit containing execution boxes (Eboxes) of micro-operations and an index of the Eboxes to be executed in response to detecting a symbol idle period of the symbol clock signal, and an Ebox execution engine configured to execute micro-operations in one of the Eboxes based on the index of the Eboxes to perform an RF maintenance or calibration operation during the symbol idle period.

The application discloses a kind of FPGA-based timing generator resolution and linearity promotion method and system, belong to automatic test equipment technical field.For the problem that existing FPGA timing generator is difficult to consider high resolution, large dynamic range and high linearity, the application adopts multi-phase clock and carry chain coarse, fine delay line to form three-stage time interpolation architecture, to realize picosecond-level interpolation of large dynamic range with very few logic resources;At the same time, the actual physical delay is obtained by constructing a time measurement channel in the chip, and is transmitted to the host computer to execute the selection algorithm, and the target delay code with the smallest integral nonlinear error is selected to update the delay code table.The application effectively overcomes the nonlinear deviation caused by the underlying hardware wiring, significantly improves the accuracy of timing edge placement and the system test rate, and is mainly used for generating high-precision timing signals in digital integrated circuit automatic test equipment.

The utility model relates to a GENLOCK control circuit and a GENLOCK control device. The GENLOCK control circuit comprises an SYNC-IN input end, a super synchronous separator, an MCU (Microprogrammed Control Unit) module and a synchronous phase-locked chip, the input end of the super synchronous separator is connected with the SYNC-IN input end, and the output end of the super synchronous separator is connected with the input end of the synchronous phase-locked chip; the MCU module is connected with the input end of the synchronous phase-locked chip; the utility model provides a highly flexible and digitally controlled GENLOCK control circuit, the adopted chip is very concise in structure, a plurality of VCXOs, PLLs and timing generators are replaced, the design complexity is reduced, the space of a circuit board is saved, video and audio clocks and timing signals can be generated, and a plurality of devices are allowed to carry out genlock with an input reference.

It can suitably generate signals at any desired timing. [Solution] The timing generator comprises a counter, a control unit, a plurality of basic pulse generation units, and one or more latch output units. The counter performs a counting operation based on a clock signal. The control unit controls the operating state of each basic pulse generation unit by setting an operation start counter value for each of the basic pulse generation units. When the counter value input from the counter becomes the operation start counter value, the basic pulse generation unit enters an operating state and controls the logic level of at least one of the latch output units. The latch output unit outputs a timing signal corresponding to the control by at least one of the basic pulse generation units.

An ADC with built-in charge-based capacitance measurement is described. Examples include: multiple capacitors coupled in parallel to an input voltage at a common node; multiple drivers, each coupled to a corresponding capacitor opposite the common node; a first switch coupled to the common node to couple the common node to ground in response to a second clock signal from a timing generator; a second switch coupled to the common node to couple the common node to a reference voltage in response to a third clock signal from the timing generator; successive logic circuitry configured to control each driver to alternately drive the second clock signal to a selected capacitor or couple a selected capacitor to ground; and measurement logic including a current sensor for measuring the current through the common node and configured to determine the capacitance of the selected capacitor.