23 results about "Timing generator" patented technology

The invention relates to an automatic test system for a dual-frequency dual-polarized antenna array plane. The automatic test system comprises a main control computer, a time sequence generator, a beam controller, a vector network analyzer, a radio frequency transceiver module, a power meter, a primary power supply, a power-on and power-off enabling module and the dual-frequency dual-polarized antenna array plane, the main control computer is respectively connected with the time sequence generator, the power-on and power-off enabling module, the vector network analyzer, the primary power supply and the power meter through network cables; a transmit-receive total port of each frequency band of the dual-frequency dual-polarized antenna array plane is connected with the radio frequency transmit-receive module. Each secondary power supply is connected with the primary power supply and the power-on and power-off enabling module. The radio frequency transceiver module is connected with the vector network analyzer through a radio frequency cable; the time sequence generator is connected with the beam controller, the radio frequency transceiver module and the vector network analyzer through control cables. The system has the characteristics of automatic selection of working frequency bands and polarization channels, automatic switching of transmitting and receiving links, real-time monitoring of working current and working temperature, real-time monitoring of transmitting calibration power and the like.

To reduce power consumption. A photodetection element includes a plurality of pixels, in which each of the plurality of pixels includes: a physical signal acquisition unit that acquires a physical signal; a comparison unit that compares a physical signal acquired by the physical signal acquisition unit with a reference signal; a signal accumulation floating unit that is electrically connected to one end of the comparison unit; a signal detection unit that is electrically connected to the signal accumulation floating unit and detects a comparison result of the comparison unit; a signal amplification unit that amplifies a detection result of the signal detection unit; a signal storage unit that stores a time code; a signal input / output unit that inputs and outputs a time code; and a signal control unit that performs control to store a time code output from the signal input / output unit in the signal storage unit on the basis of the comparison result, and outputs, to the signal input / output unit, a time code of the time when the comparison result is inverted, the time code being stored in the signal storage unit, and at least two or more of the pixels operate in parallel.

An exposure control unit, a timing generator unit, a metering unit, and a pulse control unit are provided. The exposure control unit generates a signal defining multiple second exposure periods contained within a first exposure period, which corresponds to a frame, each of which is shorter than the first exposure period. The timing generator unit generates a pulse signal defining the timing information within each second exposure period. The metering unit counts the pulse signal at or after the first photon capture in the second exposure period, based on the pulse signal generated by the timing generator unit. The pulse control unit performs pulse counting in a second exposure period following the first, based on a value from the metering unit.

Embodiments of a radio frequency (RF) controller for a 5G modem, a 5G modem, and a method for operating an RF controller of a 5G modem are disclosed. In an embodiment, an RF controller for a 5G modem includes a timing generator configured to generate a symbol clock signal, a memory unit containing execution boxes (Eboxes) of micro-operations and an index of the Eboxes to be executed in response to detecting a symbol idle period of the symbol clock signal, and an Ebox execution engine configured to execute micro-operations in one of the Eboxes based on the index of the Eboxes to perform an RF maintenance or calibration operation during the symbol idle period.

The invention discloses a method and a system for improving resolution and linearity of a time sequence generator based on an FPGA (Field Programmable Gate Array), and belongs to the technical field of automatic test equipment. In order to solve the problem that an existing FPGA time sequence generator is difficult to consider high resolution, large dynamic range and high linearity at the same time, a multi-phase clock and coarse and fine delay lines of a carry chain are adopted to form a three-level time interpolation framework, and picosecond interpolation in the large dynamic range is achieved with extremely few logic resources; meanwhile, a time measurement channel is constructed in the chip to obtain actual physical delay, the actual physical delay is transmitted to the upper computer to execute a selection algorithm, and a target delay code with the minimum integral nonlinear error is screened out to update the delay code table. According to the invention, non-linear deviation caused by bottom hardware wiring is effectively overcome, the accuracy of time sequence edge placement and the system test rate are remarkably improved, and the method is mainly used for high-precision time sequence signal generation in digital integrated circuit automatic test equipment.

The application discloses a kind of FPGA-based timing generator resolution and linearity promotion method and system, belong to automatic test equipment technical field.For the problem that existing FPGA timing generator is difficult to consider high resolution, large dynamic range and high linearity, the application adopts multi-phase clock and carry chain coarse, fine delay line to form three-stage time interpolation architecture, to realize picosecond-level interpolation of large dynamic range with very few logic resources;At the same time, the actual physical delay is obtained by constructing a time measurement channel in the chip, and is transmitted to the host computer to execute the selection algorithm, and the target delay code with the smallest integral nonlinear error is selected to update the delay code table.The application effectively overcomes the nonlinear deviation caused by the underlying hardware wiring, significantly improves the accuracy of timing edge placement and the system test rate, and is mainly used for generating high-precision timing signals in digital integrated circuit automatic test equipment.

Disclosed herein is a controller circuit of a series capacitor buck converter including input and output lines, a first switch, a coupled inductor including a first inductor and a second inductor, a second switch, a series capacitor, a third switch, a fourth switch, and an output capacitor. The controller circuit includes a control logic circuit that generates a plurality of control signals instructing ON-OFF states of the first to fourth switches so as to alternately repeat a first state in which the first switch and the fourth switch are ON and a second state in which the second switch and the third switch are ON, with an interval of dead time, and a first timing generator that generates a first timing signal as a trigger for turning on the first switch at a second dead time inserted into a period of transition from the second state to the first state.

The application belongs to the technical field of aerospace, and provides a driving circuit supporting multi-degree-of-freedom image motion compensation function, which comprises a camera controller, a multi-degree-of-freedom image motion compensation timing generator, a vertical driving circuit, a two-dimensional direction charge transfer area array CCD detector, a horizontal driving circuit, a front-end signal processing circuit and an interface circuit. The camera controller is connected with the multi-degree-of-freedom image motion compensation timing generator. The multi-degree-of-freedom image motion compensation timing generator is connected with the vertical driving circuit, the two-dimensional direction charge transfer area array CCD detector and the horizontal driving circuit respectively. The vertical driving circuit and the horizontal driving circuit are further connected with the two-dimensional direction charge transfer area array CCD detector. The two-dimensional direction charge transfer area array CCD detector is connected with the front-end signal processing circuit. The front-end signal processing circuit is connected with the interface circuit. The application can realize on-chip compensation of roll, pitch, yaw and multi-degree-of-freedom dynamic motion without moving parts.

A transceiver (20) that sends and receives data used in a communication system, wherein the data is encoded by a transmission line code and a signal level of the transmission line code changes in a bit duration at a predetermined transmission time, wherein the transceiver (20) has: a clock generator (51) that generates an internal clock used for internal circuitry; a timing generator (50) which, using the internal clock generated by the clock generator (51), generates a timing signal synchronized with a reference clock provided externally; a coding circuit (35) which, using the timing signal generated by the timing generator (50), encodes transmission data which is synchronized with the reference clock to be the transmission line code; and a signal shaping unit (36) which performs signal shaping of a signal waveform for predetermined transmission timing of the transmission data based on the reference clock, characterized by the fact that the signal shaping unit (36) includes: a release signal generation unit (361) that generates a release signal specifying a release period including a predetermined period; and a signal waveform composition circuit (362) which combines a signal waveform of the reference clock and a signal waveform of the transmission data such that the reference clock is selected during the release period specified by the release signal generated by the release signal generation circuit and the transmission data encoded by the coding circuit (35) is selected outside the release period and a selected signal is output to combine the signal waveform of the reference clock and the signal waveform of the transmission data.

The utility model relates to a GENLOCK control circuit and a GENLOCK control device. The GENLOCK control circuit comprises an SYNC-IN input end, a super synchronous separator, an MCU (Microprogrammed Control Unit) module and a synchronous phase-locked chip, the input end of the super synchronous separator is connected with the SYNC-IN input end, and the output end of the super synchronous separator is connected with the input end of the synchronous phase-locked chip; the MCU module is connected with the input end of the synchronous phase-locked chip; the utility model provides a highly flexible and digitally controlled GENLOCK control circuit, the adopted chip is very concise in structure, a plurality of VCXOs, PLLs and timing generators are replaced, the design complexity is reduced, the space of a circuit board is saved, video and audio clocks and timing signals can be generated, and a plurality of devices are allowed to carry out genlock with an input reference.

The present invention discloses a FPGA-based SLVS-EC serial decoding method. The method receives N-channel SLVS-EC high-speed serial data through the FPGA's hard-core GT to obtain N-channel parallel data. The method then converts the data bit width to half, while still outputting N-channel parallel data. The method detects control codes in the data and identifies valid data. The method also removes pad codes from the data and simultaneously performs channel alignment. The method also removes ECC error correction codes from the data. The method converts bytes into pixels, reducing the data bit width. The method parses the packet header to obtain packet header information. Timing parameters are obtained based on the packet header information. Based on the timing parameters, a timing generator generates an XSVI timing sequence. The method then caches the data, matches the data with the XSVI timing sequence, and converts the data into N / 2-channel parallel data. The method solves the problem that existing decoding methods cannot complete SLVS-EC encoding and decoding.

It can suitably generate signals at any desired timing. [Solution] The timing generator comprises a counter, a control unit, a plurality of basic pulse generation units, and one or more latch output units. The counter performs a counting operation based on a clock signal. The control unit controls the operating state of each basic pulse generation unit by setting an operation start counter value for each of the basic pulse generation units. When the counter value input from the counter becomes the operation start counter value, the basic pulse generation unit enters an operating state and controls the logic level of at least one of the latch output units. The latch output unit outputs a timing signal corresponding to the control by at least one of the basic pulse generation units.

An ADC with built-in charge-based capacitance measurement is described. Examples include: multiple capacitors coupled in parallel to an input voltage at a common node; multiple drivers, each coupled to a corresponding capacitor opposite the common node; a first switch coupled to the common node to couple the common node to ground in response to a second clock signal from a timing generator; a second switch coupled to the common node to couple the common node to a reference voltage in response to a third clock signal from the timing generator; successive logic circuitry configured to control each driver to alternately drive the second clock signal to a selected capacitor or couple a selected capacitor to ground; and measurement logic including a current sensor for measuring the current through the common node and configured to determine the capacitance of the selected capacitor.

The present application relates to the field of semiconductors, and discloses a timing generator based on FPGA, a timing generation method, a terminal device, and a readable storage medium, including: a clock source for providing a working frequency; a test cycle buffer for sequentially buffering each test cycle data; a timing data buffer for sequentially buffering each timing data; a test cycle counter for starting counting each time a test cycle is entered; a timing edge generator for determining whether the timing clock is enabled according to the count of the test cycle data and the integer part value of the timing data in the same test cycle, and outputting the fractional part value of the timing clock that is less than an integer multiple; a data generator for generating parallel data with a preset bit width from the received one-bit pattern data when the timing clock is enabled; a converter for converting the parallel data into serial data by using a preset multiple-frequency clock of the working frequency and then outputting it. This solution can improve the time resolution based on the timing generator.

The present disclosure relates to a display system, method, storage medium and electronic device, the display system comprising an LCD controller, a synchronous timing generator, an LCD timing generator and an LCD driver, the LCD controller configured to, in response to receiving a display request message, acquire a pre-stored display command, send the display command to the synchronous timing generator, and send image data to the LCD driver; the synchronous timing generator configured to generate a synchronous timing signal according to the display command, and send the synchronous timing signal to the LCD timing generator; the LCD timing generator configured to generate a driving signal according to the synchronous timing signal, and send the driving signal to the LCD driver; and the LCD driver configured to display the image data according to the driving signal. In this way, the CPU does not need to participate in data interaction during the entire display process, which can save CPU resources and improve the performance of the system.

The invention provides a GSM (Global System for Mobile Communications) timing system and a GSM timing method applied to an O-RU (Open Radio Access Unit), relates to the technical field of an O-RAN (Open Radio Access Network), and solves the problems of timing generation and synchronization when the GSM timing system is realized on an O-RU platform. The system is deployed in an O-RU under an O-RAN architecture, and generates a GSM frame / time slot timing signal according to a 1 PPS pulse per second and TOD information provided by a PTP protocol, so that the O-RU supports a 2G GSM system; the system comprises a GSM timing generator and a GSM timing regulator. The timing generator determines a timing reference starting point according to synchronization characteristics of a TOD second field and a 3-second period, and outputs a reference timing signal; the timing regulator generates independent uplink and downlink timing signals on the basis of a reference timing signal. According to the method, efficient implementation on an FPGA platform is supported, and a reliable basis is established for complete implementation of the GSM communication function in the O-RU.

The invention belongs to the technical field of video processing. The invention provides a DVI-LCOS time sequence conversion method based on an FPGA (Field Programmable Gate Array). According to the embodiment of the invention, the writing memory writes the DVI video data into the writing memory according to the DVI video data effective signal DVIDE. When the read-write controller is in the WRITE state, the read-write controller continuously reads data from the write memory and writes the data into the external high-speed memory; in the READ state, the read-write controller continuously reads data from the external high-speed memory and writes the data into the read memory. And a CRC check mechanism is added in the read-write controller. And the LCOS time sequence generator generates a corresponding time sequence control signal according to the LCOS driving video time sequence parameter. And the read memory reads the video data from the read memory according to the LCOSDE signal output by the LCOS time sequence generator.

A video transfer circuit includes: a first communication interface; a second communication interface; and a digital timing generator having an input, an output, and a video timing signal interface. The input is coupled to the first communication interface. The video timing signal interface is coupled to the second communication interface. The digital timing generator is configured to: provide a first video timing signal to the second communication interface via the video timing signal interface responsive to a first mode selection; and receive a second video timing signal from the second communication interface via the video timing signal interface responsive to a second mode selection.

The present invention discloses a multi-target secure communication system based on a pseudo-random time-modulated four-dimensional antenna array, which includes a four-dimensional wave control module, a modulation timing generator, a baseband modulation module, a mixer, a power divider, a radio frequency modulation switch, a filter, a power amplifier, an antenna element, and optical fibers and cables connecting various parts; since operations such as time modulation and filtering are performed before the power amplifier amplifies, the power loss caused by either time modulation or filtering is small and can be approximately ignored. The present invention also discloses a multi-target secure communication method based on a pseudo-random time-modulated four-dimensional antenna array. This method can perform digital-analog hybrid pseudo-random modulation on the original signal by jointly utilizing the digital baseband and analog time modulation degrees of freedom, so as to transmit different original undistorted signals in multiple desired directions, while the signals in non-desired directions are pseudo-randomly disturbed and distorted, thereby realizing secure communication transmission for multiple targets simultaneously.

The present invention relates to a chopping timing control method and system for a reference voltage generator of a sigma-delta ADC, including connecting an output end of the sigma-delta ADC to a first end of an exclusive-NOR operator; connecting an output end of a first timing generator to a second end of the exclusive-NOR operator; an output of the exclusive-NOR operator being a chopping timing control signal; using the chopping timing control signal as a clock signal of the reference voltage generator; and using an output of the reference voltage generator as a reference voltage of the sigma-delta ADC. The present invention avoids the problem of reduced signal-to-noise ratio caused by the intermodulation of the chopping ripple of the amplifier used for the reference voltage and the quantizer data stream; and avoids the residual offset voltage generated by the offset voltage of the amplifier through a second-order modulator.

The application belongs to the technical field of integrated circuits, and discloses a high-speed high-precision timing generator, which comprises a communication interface, a clock generation, a memory module, a digital control module, an edge positioning circuit, an edge merging circuit and a sampling circuit. The timing generator pre-stores test vector data in the memory, and dynamically adjusts the edge positioning in real time by calling the digital control module, thereby avoiding the vector rate bottleneck caused by the limited communication interface rate. The system adopts a delay unit structure combining coarse adjustment and fine adjustment, and introduces interpolation technology, so as to realize the adjustment of the edge position with picosecond-level resolution, and ensure the high precision and stability of the output timing vector. Meanwhile, the edge merging circuit is used to complete the parallel-to-serial conversion of multiple parallel signals, so as to improve the vector output rate, and reduce the design difficulty and power consumption of the front-end edge positioning circuit.

A technique is provided that reduces the occurrence of a difference in print resolution between an upstream ejector and a downstream ejector due to expansion and contraction of a recording medium. An inkjet printing apparatus includes four heads arranged in a transport direction and four ejection controllers that control the four heads, respectively. Each ejection controller includes an ejection timing generator that generates an ejection timing signal for causing the head that is controlled to eject ink toward a target portion of a recording medium, an expansion / contraction amount estimator that estimates the amount of expansion and contraction in the target portion, and a correction information generator that outputs, to a downstream ejection controller, correction information that includes the ejection timing signal and expansion / contraction amount information indicating the amount of expansion and contraction.

A video transfer circuit includes: a first communication interface; a second communication interface; and a digital timing generator having an input, an output, and a video timing signal interface. The input is coupled to the first communication interface. The video timing signal interface is coupled to the second communication interface. The digital timing generator is configured to: provide a first video timing signal to the second communication interface via the video timing signal interface responsive to a first mode selection; and receive a second video timing signal from the second communication interface via the video timing signal interface responsive to a second mode selection.