4732results about "Pulse automatic control" patented technology

The invention discloses a sampling implementation method and system suitable for motor protection quick response, belongs to the technical field of motor protection, and can increase the sampling frequency and improve the quick response of motor fault protection. Comprising the steps that motor phase current and bus voltage are collected, after anti-aliasing filtering is conducted, parallel sampling is conducted through a main ADC module and a redundant ADC module which are independently configured, and the following operations are synchronously executed based on a double-buffer-area framework: in a first buffer area, a compensation coefficient updating period is dynamically adjusted, and convergence is restrained; in the second buffer area, generating a voltage gradient prediction sequence, and compensating data abrupt change; when the harmonic frequency spectrum amplitude or the voltage gradient prediction sequence exceeds the limit, an oversampling mode is triggered, a redundant ADC module is allocated to load a multi-order digital filter, and an independent hardware acceleration unit is started to process harmonic compensation and gradient prediction in parallel; and generating a dynamic safety envelope, and if the gradient extreme value in the preset continuous window breaks through the safety envelope, generating an overvoltage fault signal.

The invention discloses a multichannel high-precision PAF signal synchronous acquisition system and a multichannel high-precision PAF signal synchronous acquisition method, and relates to the technical field of phased array signal acquisition and processing, the multichannel high-precision PAF signal synchronous acquisition system is characterized in that a hydrogen atomic clock time-frequency distribution module is in signal connection with a plurality of signal acquisition processing boards, and each signal acquisition processing board comprises a double-loop phase determination clock circuit and an RFSoC circuit; and the double-loop phase determination clock circuit is in signal connection with the RFSoC circuit. The time-frequency distribution module adopts a time-frequency signal output by a hydrogen atomic clock as a reference, so that the synchronization precision is ensured; the clock architecture of the acquisition processing board card adopts a phase determination mode, so that a Tile clock and a PL logic clock in the board are strictly in phase with an external input reference clock, and ADC acquisition synchronization of all channels is ensured; a phase clock circuit design is determined by adopting double loops, and all output clocks and an input reference clock keep a strict phase relationship; the system adopts a three-step synchronization process, so that the synchronous acquisition of hundreds of paths of PAF signals reaches the ps-level precision.

The invention provides a multi-band radio frequency power amplifier dynamic range adaptive test method and a system thereof. The method comprises the following steps: acquiring an output signal frequency spectrum of a tested radio frequency power amplifier, extracting characteristic frequency points including a center frequency and a bandwidth, matching the characteristic frequency points with a preset frequency band database, and automatically loading a test scheme of a corresponding frequency band. According to the method, the frequency bands are automatically matched through spectrum sensing, the test scheme is loaded, the multi-frequency-band characteristics can be rapidly adapted without manual parameter configuration, index missing test is avoided, and the switching efficiency is improved; dynamically optimizing test parameters by using a genetic algorithm, and accurately capturing a nonlinear distortion critical point while balancing coverage and efficiency; by combining multi-dimensional signal analysis and a deep learning model, the problem of missing detection of traditional single-domain analysis is solved, and the abnormal signal recognition capability is remarkably enhanced; through linear model correction, impedance dynamic matching and index threshold iteration, full automation and high precision of the test are realized, the environmental interference influence is effectively reduced, and a self-adaptive test system is constructed.

The invention relates to a digital lock-in amplifier based on a frequency adaptive technology and a weak signal acquisition system and method, and the system comprises a front-end signal processing module which is used for obtaining a weak signal to be detected; the frequency self-adaptive tracking module is used for performing fast Fourier transform on the frequency of the weak signal to be measured to obtain the position of the maximum spectral line so as to synthesize a frequency control word, further generate a local reference signal and simultaneously adjust the coefficients of a low-pass filter and a loop filter and the series adjustment mode of a carrier synchronization ring; the multi-rate narrow-band low-pass filter module is used for multiplying the digital signal by a local reference signal and then carrying out filtering and down-sampling on a high-frequency signal to obtain a plurality of mutually orthogonal difference frequency components; the vector operation module is used for carrying out vector operation on the plurality of mutually orthogonal difference frequency components to obtain the phase and the amplitude in the weak signal to be measured; and the man-machine interaction module is used for displaying and storing the phase and the amplitude in the weak signal to be detected.

A receiver circuit is configured to generate a reception symbol from a multi-level signal. The receiver circuit is configured to generate three compensation signal pairs from an input signal pair to perform a loop unrolled decision feedback equalization operation. A first summing circuit is configured to equalize the input signal pair with a first offset to generate a first compensation signal pair, and a second summing circuit is configured to equalize the input signal pair with a second offset to generate a second compensation signal pair. An averaging circuit is configured to average the first compensation signal pair and the second compensation signal pair to generate a third compensation signal pair.

The invention relates to the technical field of atomic clock control, and discloses a punctuality type atomic clock control method based on a microwave frequency band. The method comprises the following steps: firstly, acquiring microwave frequency band signal data and atomic state data, and constructing a time calculation model in combination with historical operation data to output a theoretical time value; performing multi-dimensional difference analysis on the theoretical time value and the actual measurement time value to generate a time difference coefficient matrix; inputting the matrix into a spatial propagation analysis network, and combining atomic clock component parameters and environmental parameters to generate a time anomaly probability distribution diagram; and finally, configuring microwave control parameters according to the distribution diagram, including starting a high-frequency monitoring mode for a high-probability abnormal region and applying a disturbance test to adjacent frequency bands. According to the method, through multi-dimensional data modeling, difference analysis and dynamic parameter configuration, the accuracy and adaptability of atomic clock control are improved, and the operation stability of the atomic clock in a complex environment can be enhanced.

The invention provides a clock signal generating circuit, a wired communication transceiver and electronic equipment, and the circuit outputs a first DC voltage comprising phase difference information and frequency difference information of a reference clock signal and a feedback clock signal through a phase frequency detection module. The pulse generator generates a narrow pulse signal based on the DC voltage and a reference clock signal, the oscillation frequency of each secondary ring oscillator in the cross-coupled ring oscillator is controlled by the first DC voltage, and the cross-coupled loop performs synchronous coupling and phase sequence adjustment processing on each secondary ring oscillator. One output node in the cross coupling ring oscillator receives the narrow pulse signal, frequency and phase locking is completed in an injection locking mode, and the frequency divider is used for conducting frequency division processing on any high-frequency clock signal and outputting a feedback clock signal. Therefore, a high-frequency multi-phase clock signal with low phase noise and high phase precision can be generated by using the low-frequency reference clock signal.

An injection-locked oscillator includes a plurality of delay elements, two or more voltage control circuits, a phase comparator and a controller. The plurality of delay elements is connected in a loop and coupled to a global power supply. Each delay element has an input driven by a preceding stage and an output that drives a next stage. Each voltage control circuit couples one of the plurality of delay elements to the global power supply. The phase comparator is coupled to in-phase and quadrature outputs of the injection-locked oscillator. The controller is coupled to an output of the phase comparator and is configured to drive control inputs of the two or more voltage control circuits. The control input of each voltage control circuit determines a level of a voltage drop across the each voltage control circuit.

A charge pump, a phase-locked loop, a radar sensor, and an electronic device. The charge pump is applicable to the phase-locked loop. The charge pump comprises a discharging circuit and a charging circuit, both of which are connected to an output end of the charge pump. The discharging circuit reduces a current of the output terminal under control of a first control signal, the charging circuit increases it under control of a second control signal, the first control signal and the second control signal being corresponding to error signals between the two clock signals. The charge pump further comprises a voltage control circuit connected to a first node in the discharging circuit and / or a second node in the charging circuit to maintain the locked state of the phase-locked loop by controlling voltages of corresponding nodes, the first node and the second node being both connected to the output end.

The invention provides a broadband tunable low-phase-noise photo-generated microwave signal source and device, and relates to the technical field of photo-generated microwaves. According to the invention, a low-frequency optical pulse and a high-frequency microwave signal are respectively input into the electro-optical sampling phase-locked loop; and the electro-optical sampling phase-locked loop determines the synchronization error of the optical pulse and the microwave signal based on the phase difference between the optical pulse center point and the microwave signal zero crossing point. And taking the synchronization error as a feedback signal, and continuously adjusting the frequency and the phase of the microwave signal by the voltage-controlled oscillation module until the frequency and the phase are synchronized with the Nth harmonic of the optical pulse. By setting different initial frequencies of the voltage-controlled oscillation module, microwave signals with different integral multiple optical pulse frequencies can be obtained, and broadband tuning of photo-generated microwave signals is realized. Furthermore, the repetition frequency of the frequency comb is locked through beat frequency of two beams of reference laser and two adjacent comb teeth, the stability of the reference laser is transmitted to the optical pulse, and the stability of the reference laser is further transmitted to the microwave signal through synchronization of the optical pulse and the microwave signal, so that the phase noise of the photo-generated microwave signal source is reduced.

A phase interpolator circuit that generates an output clock signal having a phase according to a PI code based on input clock signals, the phase interpolator circuit includes: a first generation circuit configured to generate a first intermediate current based on a first input clock signal according to the PI code; a second generation circuit configured to generate a second intermediate current based on a second input clock signal having a first phase difference from the first input clock signal according to the PI code; a synthesis circuit configured to synthesize the first and second intermediate currents to generate the output clock signal; and a correction circuit configured to correct a current amount of at least one of the intermediate currents based on a correction current according to a correction code set according to at least an amount of shift of the first phase difference from a certain value.

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

The invention discloses a frequency source synthesis system and method based on a frequency agility radar, and belongs to the technical field of microwave radio frequency, and the method specifically comprises the steps: generating a target clock signal, carrying out the frequency processing of the target clock signal to generate a frequency multiplication signal, and dividing the frequency multiplication signal into two clock signals through a power divider; performing frequency multiplication processing on one path of clock signal, taking the processed signal as a clock reference signal of a direct digital synthesizer, generating an analog signal according to the clock reference signal, and calibrating the analog signal as an output signal; performing frequency multiplication processing on the other path of clock signal, and taking the processed clock signal as a local oscillation signal of the frequency mixer; performing frequency conversion processing to obtain a frequency mixing signal, performing quadruplicated frequency processing on the frequency mixing signal, and calibrating the processed frequency mixing signal as a final output signal; according to the invention, the frequency source has the characteristics of low phase noise, rapid agility, fine resolution and miniaturization at the same time.

The invention relates to a phase-locked loop circuit, a clock generator, a chip and electronic equipment, and the phase-locked loop circuit mainly comprises a phase frequency detector which is used for generating a phase detection output signal according to the phase of a reference clock signal and the phase of a feedback clock signal; the proportional path module is used for generating a first control current according to the phase discrimination output signal; the integral path module is used for generating a second control current according to the phase discrimination output signal; the current control oscillation module is used for generating a clock output signal according to the first control current and the second control current; and the feedback frequency divider is used for obtaining a feedback clock signal through frequency division of the clock output signal. According to the phase-locked loop, the advantages of the analog charge pump phase-locked loop and the full-digital phase-locked loop are combined, the generation of a high-performance clock which is small in area, high in bandwidth, stable in loop and low in quantization noise is facilitated, the applicability of the phase-locked loop to the high bandwidth requirement is facilitated, the quantization noise is reduced, and the performance of the phase-locked loop is improved. And unconditional stability of the phase-locked loop is realized theoretically.

The present application belongs to the technical field of wireless communications and radar systems. Disclosed are a dual-band fusion and multiplexing frequency source, chips, a radio-frequency transceiver, a system, and a device. The system comprises: a full-function millimeter-wave CMOS 4+1 phased array chip, which is connected to an antenna end, and is used for realizing signal processing and frequency conversion between a millimeter-wave signal and a C-band intermediate-frequency signal, performing phase control and gain adjustment on the millimeter-wave signal, and providing an internal frequency source and a calibration function; a C-band front end, which is connected to the antenna end, and is used for receiving or transmitting a C-band signal; a C-band / intermediate-frequency transceiver multiplexing chip, which is used for performing frequency conversion between a C-band or intermediate-frequency signal and a baseband signal in a multiplexing manner, and performing signal processing and gain control on the C-band intermediate-frequency signal; a dual-band fusion and multiplexing frequency source, which is used for providing a local oscillator signal; and an all-digital control logic circuit, which is used for providing a control instruction. The present application improves the efficiency and performance of dual-band joint communications.

The invention discloses a current and voltage signal synchronous correction and output method and system, and relates to the technical field of power system analysis and control. Compared with a previous current and voltage signal correction method, the method solves the problems that traditional multi-channel signal acquisition depends on conventional clock control, and synchronization precision is insufficient; a conventional sampling circuit is weak in anti-interference capability. The problem that an existing scheme lacks efficient error prediction and dynamic optimization capability is solved. Through a multi-channel FPGA clock synchronization and double-differential sampling technology, complete acquisition of high-frequency transient characteristics of voltage and current signals is ensured; a dynamic calibration algorithm and multi-stage composite filtering are combined, so that common-mode interference and non-linear errors are effectively suppressed; and finally, through optical fiber isolation output and intelligent feedback control, signal full-link synchronous correction is realized, the electric energy metering error can be reduced, the fault positioning precision is improved, the characteristics of high precision, strong anti-interference and low energy consumption are realized, and a reliable data reference is provided for intelligent power grid and new energy grid connection.

The invention provides a novel clock control method and system based on FPGA, and relates to the technical field of signal processing. The system provided by the invention comprises: a VCXO voltage-controlled crystal oscillator, a digital-to-analog converter, a PLL phase-locked loop module, a DDMTD measurement module and an adaptive clock control module. The phase-locked loop is implemented, a phase detection algorithm and a clock control algorithm are executed based on a single FPGA chip, and the hardware design complexity is low. The invention uses a digital dual-mixing time difference method (DDMTD) to measure and obtain a clock phase detection result, and cooperates with a dynamic PID clock control algorithm to quickly adjust the local clock frequency, so as to realize the fast tracking and locking of the frequency and phase between the local clock and the clock source. The dynamic PID clock control algorithm of the invention dynamically adjusts the parameter P of the PID algorithm in real time according to the state, the clock frequency deviation and the clock phase difference, so that the algorithm has the advantages of stronger locking ability, shorter convergence time and faster response.

Millimeter wave (mmWave) technologies, devices, and methods related to transceivers, receivers, and antenna structures for wireless communications are described. Various aspects include collocated millimeter wave (mmWave) antennas and near field communication (NFC) antennas, scalable phased array radio transceiver architecture (SPARTA), phased array distributed communication systems with MIMO support and phase noise synchronization on a single coaxial cable, passing RF signals over cable (RFoC) in distributed phased array communication systems, clock noise leakage reduction, IF to RF auxiliary chips for backward and forward compatibility and modularity, on-package matching networks, 5G scalable receiver (Rx) architectures, and the like.

The invention relates to the field of signal processing, and provides a signal processing method and system for a reconnaissance unmanned aerial vehicle, and the method comprises the steps: carrying out the signal decomposition of a first intermediate frequency signal obtained through the frequency mixing of an unmanned aerial vehicle signal, so as to obtain a set of signal component intrinsic mode functions; a signal analysis and processing algorithm based on deep learning is adopted to carry out waveform semantic feature extraction on the intrinsic mode function of each signal component, so that a filtered first intermediate frequency signal is automatically generated based on the significant dynamic aggregation representation of the waveform semantic feature of each signal component in a global domain; the method can dynamically adapt to the change of a signal environment and extract more representative features so as to improve the flexibility of signal processing. Compared with a traditional fixed parameter filter, the method can better deal with interference and noise in a complex environment, enables the final signal to be clearer, and improves the signal processing quality and automation level of the reconnaissance unmanned aerial vehicle.

The invention provides a crystal oscillator and an atomic clock, and relates to the technical field of oscillators, the crystal oscillator comprises a packaging cavity, a crystal, a temperature sensor and a cantilever beam assembly, the crystal, the temperature sensor and the cantilever beam assembly are arranged in a containing cavity of the packaging cavity, and the packaging cavity is of a vacuum packaging structure. The crystal and the temperature sensor are arranged on the cantilever beam assembly, the crystal and the temperature sensor are electrically connected with different connection points of the packaging cavity through the cantilever beam assembly, and the temperature sensor is arranged around the crystal; the cantilever beam assembly comprises a heating module, and when the temperature sensor monitors that the temperature of the area where the crystal is located is smaller than a preset temperature threshold value, the heating module heats the crystal. The energy loss of air damping to the high-frequency vibration of the crystal is eliminated, the Q value is improved, and the phase noise suppression capability is enhanced; accurate control over the temperature of the area where the crystal is located is achieved, the thermal response speed and the temperature control precision are improved, and the problem that an existing crystal oscillator is poor in stability is solved.

A multi-modulus divider includes a prescaler and a finite state machine. The prescaler includes a combinational logic circuit programmable to divide a frequency of an input clock signal by a first value or a second value. The multi-modulus divider includes a first flip-flop having a data input coupled to an output of the prescaler and an output coupled to an input of the finite state machine. The multi-modulus divider includes a second flip-flop having a data input coupled to the finite state machine such that the data input is configured to receive a programming signal output by the finite state machine and associated with programming the combinational logic circuit. The multi-modulus divider includes a third flip-flop having a data input coupled to an output of the second flip-flop. The third-flip flop also has an output coupled to the combinational logic circuit.

The invention discloses a reference-clock-free clock and data recovery circuit, a use method and an integrated circuit. The circuit comprises a first circuit and a second circuit, the first circuit comprises a voltage-controlled oscillator, the second circuit comprises a comparison module and a frequency capture module, and the comparison module is used for comparing a first clock signal with a high-speed serial data signal, generating a first signal and outputting the first signal to the frequency capture module. The frequency capture module outputs a first control signal, the first control signal is used for adjusting the first oscillation frequency so as to enable the frequency deviation between the first oscillation frequency and the second oscillation frequency to be smaller than a first deviation threshold value, and the second circuit generates a second clock signal and outputs the second clock signal to the first circuit; the first circuit adjusts the voltage-controlled oscillator using a second clock signal such that the frequency offset is less than a second offset threshold. According to the invention, the CDR and PLL functions are fused and an external reference clock is replaced by the CDR recovery clock, so that a clock and data recovery system without an external clock is realized.

The invention belongs to the field of electronic devices, particularly relates to an anti-SET reinforced phase frequency detector, and aims to solve the problems that the existing SET injection can change the output logic state of a PFD (phase frequency detector), and a post-stage circuit obtains a wrong phase difference indication signal. According to the invention, an output UP signal and an output DOWN signal of a first-stage unit are used as the input of an input control logic, and the input control logic outputs four indication signals; the input of the first output control logic is four indication signals, and the output of the first output control logic is a first conduction control signal; the second-stage unit is used for carrying out rising edge sampling on the UP signal and the DOWN signal respectively and outputting two indication signals; the input of the phase selector is a reference clock signal, a feedback clock signal and two indication signals, the output of the phase selector is the input of the second output control logic, and the second output control logic outputs a second conduction control signal. According to the invention, the output logic state is not changed during SET injection, and a correct phase difference indication signal is obtained at a rear stage.

The invention relates to the technical field of radio frequency generator circuits, and provides a phase-locking frequency-stabilizing multi-core control radio frequency system, which processes I / Q signals and constructs a multi-core task allocation and cooperation mechanism through a digital baseband processing module, and performs pre-distortion processing and system scheduling. The double-closed-loop control module is used for stabilizing fundamental frequency, correcting temperature drift and compensating and adjusting frequency swing amplitude; the hybrid power amplification module is used for performing multi-stage hybrid power amplification signal processing and temperature monitoring through a driving stage and output stage combined topology; and the feedback sampling network module collects output signals in real time through a directional coupler and feeds back, adjusts and precisely controls the frequency stability according to the output signals.

Disclosed in the present invention is a variable coefficient equivalent SISO model based stability analysis method for a grid-connected converter system, comprising the following steps: constructing a variable coefficient equivalent SISO model; obtaining a complex space vector open-loop transfer function on the basis of the variable coefficient equivalent SISO model; and obtaining Nyquist curves under different current loop parameters or phase-locked loop parameters on the basis of the complex space vector open-loop transfer function. If the Nyquist curves surround point (-1,0), the grid-connected converter system is stable; and if the Nyquist curves do not surround point (-1,0), the grid-connected converter system is unstable. The present invention performs small disturbance modeling on the grid-connected converter system, considers the influence of mutual coupling between the phase-locked loop and the inner current loop, and derives a variable coefficient SISO open-loop transfer function capable of characterizing an MIMO system. Compared with the technical solution in the prior art that actual working conditions are not considered, the method disclosed in the present invention can more accurately analyze the system stability of the system under variable working conditions and variable parameters.

The invention provides a multi-phase clock generator which outputs N injection current signals corresponding to different phases by processing an input clock signal, N is an integral multiple of 4, and a cross-coupled loop is arranged in a cross-coupled ring oscillator. The loop is respectively coupled with output nodes in N / 4 secondary ring oscillators based on a phase sequence, and the secondary ring oscillators realize high-working-frequency and high-stability oscillation frequency output and low-error phase alignment through a cross coupling mechanism, so that the secondary ring oscillators can output N oscillation clock signals with equally-spaced phases, and the phase alignment is realized. Since the injection current signal is input into each output node in the secondary ring oscillator based on the phase sequence, the frequency and the phase of the secondary ring oscillator are locked, the frequency is the same as the frequency of the input clock signal, and the phase noise is very low, so that the frequency and the phase of the secondary ring oscillator are locked. According to the invention, a high-speed multi-phase clock signal with low phase noise and high phase precision can be generated.

The embodiment of the invention discloses a delay-locked loop circuit, a clock generator, a chip and electronic equipment, and belongs to the technical field of integrated circuits. The delay-locked loop circuit includes: a digital control circuit for transmitting a first adjustment code adapted to adjust the number of delay units in a coarse adjustment phase, and determining whether to adjust the first adjustment code based on a first feedback signal; in the fine adjustment stage, a third adjustment code suitable for adjusting the delay attribute parameter of the delay unit is sent, and whether the third adjustment code is adjusted or not is determined based on the second feedback signal; in the locking phase, transmitting a second adjustment code suitable for adjusting the control voltage of the delay unit, and determining whether to adjust the second adjustment code based on the third feedback signal; and the phase detection unit is used for sending the first feedback signal, the second feedback signal and the third feedback signal to the digital control circuit. A hybrid circuit of digital design and analog design is provided, high-precision clock phase adjustment is achieved, and an output clock in a wide frequency range can also be achieved.

The invention relates to the technical field of integrated circuits, in particular to a charge pump phase-locked loop circuit, a radar and a charge pump phase-locked loop locking control method.The circuit comprises a charge pump, the charge pump comprises a first branch circuit, a second branch circuit, a third branch circuit and a fourth branch circuit, the frequency sweeping state refers to the state when the frequency of the signal output by the phase-locked loop is linearly changed; the at least one second branch is connected to the first branch under the condition that the hopping amplitude of the frequency of the signal output by the phase-locked loop is greater than or equal to a preset amplitude threshold value so as to increase the magnitude of the current output by the charge pump, and is disconnected with the first branch when the phase-locked loop enters a frequency sweeping state; the circuit can effectively shorten the locking time of the phase-locked loop when the phase-locked loop has relatively large frequency hopping, and is beneficial to improving the response speed and performance of a system.

The invention discloses an intermittently operated phase-locked loop and an implementation method thereof. The phase-locked loop can be controlled to be switched between an open loop and a closed loop. The phase-locked loop is controlled to be switched between an open loop and a closed loop by judging whether the performance of a phase-locked loop circuit meets a preset standard of a system applying the phase-locked loop or not in real time; or, the phase-locked loop circuit is controlled to be switched between the open loop and the closed loop according to a preset period according to a time period preset period required by the system for the preset standard of the phase-locked loop circuit. Therefore, the open loop or the closed loop of the phase-locked loop can be controlled according to actual needs, and the influence of the phase-locked loop on the system can be reduced while the phase-locked performance of the phase-locked loop can be completed.

The invention discloses a frequency measurement circuit and a frequency measurement method, belongs to the technical field of frequency measurement, and mainly solves the problems that the existing frequency measurement is large in frequency error, low in frequency measurement speed and narrow in frequency measurement bandwidth, and cannot meet the requirements of radar communication. The frequency measurement circuit comprises an FPGA control module, a reference clock circuit connected with the FPGA control module, a DDS frequency output circuit, a phase discrimination frequency control circuit, a frequency mixer connected with the phase discrimination frequency control circuit, and a radio frequency input circuit connected with the frequency mixer. According to the frequency measurement technology, the DDS output frequency is directly collected according to the characteristic that the FPGA collects the low frequency, the DDS output frequency serves as the phase discriminator phase discrimination frequency, frequency measurement is conducted in a phase locking mode, and the frequency measurement precision is high; the phase discriminator is set to have a fixed frequency dividing ratio, the phase discriminator is configured with a fixed register, a DDS frequency sweeping mode is adopted, and the frequency measurement time is short by changing the phase discrimination frequency of the phase discriminator to the output frequency of the phase-locked loop; and the frequency measurement bandwidth is increased by using a radio frequency input frequency division mode.