2254results about "Pulse automatic control" patented technology

The invention relates to the technical field of atomic clock control, and discloses a punctuality type atomic clock control method based on a microwave frequency band. The method comprises the following steps: firstly, acquiring microwave frequency band signal data and atomic state data, and constructing a time calculation model in combination with historical operation data to output a theoretical time value; performing multi-dimensional difference analysis on the theoretical time value and the actual measurement time value to generate a time difference coefficient matrix; inputting the matrix into a spatial propagation analysis network, and combining atomic clock component parameters and environmental parameters to generate a time anomaly probability distribution diagram; and finally, configuring microwave control parameters according to the distribution diagram, including starting a high-frequency monitoring mode for a high-probability abnormal region and applying a disturbance test to adjacent frequency bands. According to the method, through multi-dimensional data modeling, difference analysis and dynamic parameter configuration, the accuracy and adaptability of atomic clock control are improved, and the operation stability of the atomic clock in a complex environment can be enhanced.

The invention provides a broadband tunable low-phase-noise photo-generated microwave signal source and device, and relates to the technical field of photo-generated microwaves. According to the invention, a low-frequency optical pulse and a high-frequency microwave signal are respectively input into the electro-optical sampling phase-locked loop; and the electro-optical sampling phase-locked loop determines the synchronization error of the optical pulse and the microwave signal based on the phase difference between the optical pulse center point and the microwave signal zero crossing point. And taking the synchronization error as a feedback signal, and continuously adjusting the frequency and the phase of the microwave signal by the voltage-controlled oscillation module until the frequency and the phase are synchronized with the Nth harmonic of the optical pulse. By setting different initial frequencies of the voltage-controlled oscillation module, microwave signals with different integral multiple optical pulse frequencies can be obtained, and broadband tuning of photo-generated microwave signals is realized. Furthermore, the repetition frequency of the frequency comb is locked through beat frequency of two beams of reference laser and two adjacent comb teeth, the stability of the reference laser is transmitted to the optical pulse, and the stability of the reference laser is further transmitted to the microwave signal through synchronization of the optical pulse and the microwave signal, so that the phase noise of the photo-generated microwave signal source is reduced.

A data and clock recovery circuit, a receiving apparatus, a circuit system, a vehicle-mounted device, a vehicle, and a data and clock recovery method are provided. The data and clock recovery circuit includes a sampler, a phase detector, a multi-order filter, a frequency change detection circuit, and a selector. The sampler is configured to sample an input signal based on a multi-order filtered signal to generate a sampled signal. The phase detector is configured to determine a phase difference in the sampled signal based on the sampled signal. The multi-order filter is configured to generate the multi-order filtered signal based on the phase difference. The frequency change detection circuit is configured to determine a frequency change direction of a spread spectrum clock in the input signal by using the phase difference.

The present application belongs to the technical field of wireless communications and radar systems. Disclosed are a dual-band fusion and multiplexing frequency source, chips, a radio-frequency transceiver, a system, and a device. The system comprises: a full-function millimeter-wave CMOS 4+1 phased array chip, which is connected to an antenna end, and is used for realizing signal processing and frequency conversion between a millimeter-wave signal and a C-band intermediate-frequency signal, performing phase control and gain adjustment on the millimeter-wave signal, and providing an internal frequency source and a calibration function; a C-band front end, which is connected to the antenna end, and is used for receiving or transmitting a C-band signal; a C-band / intermediate-frequency transceiver multiplexing chip, which is used for performing frequency conversion between a C-band or intermediate-frequency signal and a baseband signal in a multiplexing manner, and performing signal processing and gain control on the C-band intermediate-frequency signal; a dual-band fusion and multiplexing frequency source, which is used for providing a local oscillator signal; and an all-digital control logic circuit, which is used for providing a control instruction. The present application improves the efficiency and performance of dual-band joint communications.

The invention relates to the technical field of radio frequency generator circuits, and provides a phase-locking frequency-stabilizing multi-core control radio frequency system, which processes I / Q signals and constructs a multi-core task allocation and cooperation mechanism through a digital baseband processing module, and performs pre-distortion processing and system scheduling. The double-closed-loop control module is used for stabilizing fundamental frequency, correcting temperature drift and compensating and adjusting frequency swing amplitude; the hybrid power amplification module is used for performing multi-stage hybrid power amplification signal processing and temperature monitoring through a driving stage and output stage combined topology; and the feedback sampling network module collects output signals in real time through a directional coupler and feeds back, adjusts and precisely controls the frequency stability according to the output signals.

The invention belongs to the technical field of data analysis and processing, and particularly relates to an equipment state monitoring method based on a time sequence synchronous compression mechanism, and the method comprises the steps: 1, a monitoring terminal collects vibration type, acoustic type and acceleration type signals on a unified time baseline of Beidou time service signals, and registers a second sequence number and a frame sequence number in a unified fragment index table; 2, inputting an original time sequence data packet, constructing a phase grid frame by a phase locking ring according to a reference phase rail, extracting road-level flag event bits frame by frame, and fusing the road-level flag event bits into frame-level flag event bits; and step 3, outputting an equipment state label according to a mutual exclusion priority rule only on the basis of the synchronous compression time sequence packet and the coupling mark, the mode instruction and the abnormal fragment mark in the unified fragment index table in the identification window. The method is obviously superior to the prior art in the aspects of time sequence alignment precision, pattern recognition certainty, data compression efficiency and health state judgment reliability.

A dual path PLL provides excellent output phase stability over PVT variations, without implementing a high accuracy TDC. A digital integral path employs a binary phase detector, comparing the reference and feedback signals, and an integrator to generate an oscillator control input to lock the long-term output phase to the reference signal. An analog proportional path employs a linear (e.g., edge triggered) phase detector and a charge pump and filter to generate an oscillator control input to mitigate phase noise in the output signal. The feedback signal to the proportional path is delayed, which has the effect of increasing the width of phase error pulses, and moving the charge pump operating point away from the zero point where it generates both positive and negative currents, which are difficult to match. A second linear phase detector in the proportional path compensates for the increased phase error pulse width by comparing the delayed and non-delayed feedback signals, and generating pulses in the opposite direction.

The embodiment of the invention provides a delay measurement circuit and a memory. The delay measurement circuit is applied to the delay phase-locked loop and comprises a loop mark generation circuit which is electrically connected with a loop of the delay phase-locked loop and is configured to generate a loop mark signal and input the loop mark signal to the loop of the delay phase-locked loop when loop delay measurement is carried out on the delay phase-locked loop; after the loop mark signal circulates M times in the loop of the delay phase-locked loop, a measurement ending signal is generated, a target pulse signal is generated, and the effective pulse width of the target pulse signal is equal to M times of the loop delay; wherein M is an even number greater than 1; the counting circuit is electrically connected with the loop mark generation circuit and is configured to receive a frequency division clock signal, and the effective pulse width of the target pulse signal is timed by using the frequency division clock signal to obtain a timing result; and carrying out preset processing on the timing result to obtain a loop delay measurement result of the delay-locked loop. The embodiment of the invention is at least beneficial to increasing the margin value of the delay measurement circuit and improving the accuracy of loop delay measurement.

The invention provides a VCO digital circuit control method and system with temperature compensation, and relates to the technical field of circuit control, and the method comprises the steps: obtaining VCO output frequency and real-time temperature, and calculating an initial frequency deviation; correcting the frequency deviation based on the temperature compensation coefficient, and generating a temperature-frequency deviation characteristic curve; an optimal compensation factor is determined through Monte Carlo sampling; calculating a compensation parameter adaptive weight by using Bayesian iteration, and dynamically adjusting a compensation factor; and a control signal is generated through the digital integrator to realize frequency calibration. According to the invention, the high-precision frequency stability of the VCO under the temperature change condition is realized, and the circuit reliability is improved.

The application discloses a double-resonance atomic clock ultra-miniature substrate integrated waveguide chamber, comprising: a substrate integrated waveguide annular gap cavity, the substrate integrated waveguide annular gap cavity is formed by longitudinal stacking of a plurality of longitudinal slit substrate integrated waveguides, the longitudinal slit substrate integrated waveguide comprises a metalized through hole and a metal microstrip line, and the longitudinal slit substrate integrated waveguide is provided with a longitudinal slit; a MEMS atomic gas chamber; a mode matching excitation structure for exciting a microwave magnetic field to the substrate integrated waveguide annular gap cavity; and an electromagnetic shielding and heating assembly arranged outside the substrate integrated waveguide annular gap cavity. The application can effectively solve the key problem that the resonant performance of a printed miniature annular gap cavity is extremely sensitive to the size change of subwavelength structure parameters, increase the processing tolerance of the ultra-miniature integrated chamber, reduce the processing difficulty and manufacturing cost of high-precision PCB through holes, and improve product yield.

The invention relates to the technical field of serial communication, in particular to a high-speed clock recovery method and device based on an adjustable delay chain, and the method comprises the steps: generating a recovery clock initial phase; a multi-stage programmable delay chain is adopted, and a phase-locked loop or delay-locked loop structure is combined, so that the initial phase of a recovered clock is finely adjusted and locked, and phase capture and clock edge alignment are performed; based on a multi-path recovery structure, a path with the minimum error is selected from the delay paths through a preset phase error detection mechanism to serve as an output channel; environment parameters of the environment are collected, parameters of the multi-stage programmable delay chain are dynamically adjusted, and high-speed clock recovery is completed. According to the method, the edge capture precision, the system jitter tolerance and the working frequency range of the recovered clock are remarkably improved, and then the phase consistency, the anti-interference capability and the overall data receiving reliability of the recovered clock in the high-speed communication system are effectively improved.

Generation of a clock signal in a semiconductor integrated circuit (IC) is controlled using a Noise Modulation Agent (NMA), configured to measure the clock signal and output a parameter indicative of an effective cycle time of the clock signal. An Adaptive Frequency Scaling (AFS) circuit selectively adjusts a frequency of the clock signal, based on the output of the NMA indicating a change in a power supply voltage of the semiconductor IC.

The invention discloses a conversion circuit for measuring time sequence arc delay of a standard unit, which belongs to the field of integrated circuits and comprises a time sequence arc delay clock generation circuit of the standard unit, a clock frequency dividing circuit, a control module and an IO output module. The standard unit time sequence arc delay clock generation circuit connects a plurality of same standard units in series to form a test chain, delays the time sequence arc of a single standard unit, and outputs the time sequence arc in a stable-frequency clock form; the clock frequency division circuit performs frequency division on the stable clock generated by the standard unit time sequence arc delay clock generation circuit through an algorithm, so that the stable clock can be detected by a machine table; the control module selects a plurality of standard cell types from the control signal, selects a time sequence arc, selects a cascade stage number, and controls the output of the clock frequency dividing circuit; and the IO output module outputs the frequency-divided clock generated on the chip through an IO port so as to be detected by a machine. According to the invention, extra power consumption, area and design complexity caused by an extra on-chip high-frequency clock can be effectively avoided.

Linear unretimed interfaces lack clock and data recovery and retiming circuits implemented on a sophisticated digital signal processor. When the interface is not a retimed interface, it can be especially useful to extract some information about the link to allow for debugging and optimization of system deployment. An efficient solution can be implemented in unretimed interfaces to compute metrics such as the impulse response and signal histogram. Having the metrics allows for the solution to check and monitor the quality and the status of the link. Based on the link quality and status information, it is possible to address non-idealities and optimize performance of the unretimed interfaces and the link.

An example chiplet includes a first die, a second die, a first clock mesh, and a second clock mesh. A first clock circuit in the first die includes a first clock generation circuit and a first drive buffer circuit. A second clock circuit in the second die includes a second drive buffer circuit. An input end of the first drive buffer circuit is coupled to a first output end of the first clock generation circuit, and a first output end of the first drive buffer circuit is coupled to an input end of the first clock mesh. An input end of the second drive buffer circuit is coupled to a second output end of the first clock generation circuit, and a first output end of the second drive buffer circuit is coupled to an input end of the second clock mesh.

The invention relates to the technical field of digital signal processing, and particularly discloses a mixed precision low-resource digital control oscillator implementation method and system based on an FPGA (Field Programmable Gate Array), and the method comprises the steps: dividing a 32-bit phase accumulator into a high-bit 24-bit dominant frequency control section and a low-bit 8-bit dynamic compensation section, and carrying out the phase accumulation in parallel through double carry chains, the high-order section receives high 24 bits of a frequency tuning word FTW to control a dominant frequency, and the low-order section receives low 8 bits of the FTW and overlaps an overflow remainder to dynamically compensate for a phase error. According to the implementation method of the mixed precision low-resource digital control oscillator based on the FPGA disclosed by the embodiment of the invention, through collaborative innovation of mixed precision phase accumulation, hierarchical mixed storage, high-order interpolation reconstruction and dynamic phase compensation, the core problems of a traditional NCO in resource occupation, phase continuity, waveform precision and time sequence performance are systematically solved.

The invention provides a clock transmission circuit, a phase calibration method and a memory. The clock transmission circuit comprises a first clock distribution network and a second clock distribution network which respectively receive a first input clock signal and a second input clock signal, transmit the first input clock signal and the second input clock signal to an output port area and output a first target clock signal and a second target clock signal; in the normal working mode, the phase difference between the second input clock signal and the first input clock signal is a preset value; in the calibration mode, the second input clock signal and the first input clock signal are in the same phase; the phase calibration module is used for receiving the first target clock signal and the second target clock signal in a calibration mode, and outputting a first phase calibration code according to the phase difference between the first target clock signal and the second target clock signal for adjusting the delay of the second clock distribution network; when calibration is completed, the phase difference between the first target clock signal and the second target clock signal is smaller than a preset threshold value. The invention is at least beneficial to improving the phase difference among the multi-phase clocks and shortening the test time.

Offline prior to operation, an optimised control sequence is derived for a pulse system comprising a reactive circuit for generating electromagnetic pulses, such as a transcranial magnetic stimulation circuit, and cascaded switching modules for switchably connecting capacitive discharge elements to provide a multi-level output voltage for the reactive circuit. A discrete-time model predicts an electrical state of the pulse system. A target profile for an electromagnetic pulse is received. For respective time-steps of the control sequence taken in succession, an optimal path of switching states over a window of time-steps starting with the respective time-step is derived, optimising a cost function having a deviation cost contribution representing deviation of an electrical state of the pulse system predicted by the discrete-time model from the target profile over the window. The switching state of the determined path at the respective time-step is selected for the control sequence.

A radar system injects a calibrated current at a signal generator during a reset portion and acquisition portion of each chirp period. The signal generator employs “gear-switching” to reduce PLL bandwidth during an acquisition phase and to increase the phase lock loop (PLL) bandwidth during a reset phase. By employing gear switching to change the bandwidth of the PLL circuit during the different portions of each chirp period, the length of the reset period is reduced, thus improving overall efficiency of the radar system while maintaining good performance.

A high linearity phase interpolator (PI) is disclosed. A phase value parameter indicative of a desired phase difference between an output signal and an input clock signal edge may be provided by control logic. A first capacitor may be charged for a first period of time with a first current that is proportional to the phase value parameter to produce a first voltage on the capacitor that is proportional to the phase value parameter. The first capacitor may be further charged for a second period of time with a second current that has a constant value to form a voltage ramp offset by the first voltage. A reference voltage may be compared to the voltage ramp during the second period of time. The output signal may be asserted at a time when the voltage ramp equals the reference voltage.

An optical frequency generation system (100), comprising: - reference atoms (7) in a gas phase, - an interrogation laser source (1) configured to emit an interrogation signal (101) comprising a first optical frequency suitable for exciting a two-photon transition in said reference atoms (7), said interrogation signal (101) being configured to interact with said reference atoms (7) in a Doppler-free scheme; - optical frequency modulation means (31, 31a, 31b) configured to adjust said first optical frequency and to modulate said first optical frequency at a first modulation frequency f1; - an optical sensor (9) configured to detect a fluorescence signal (110) from said reference atoms (7); - a first control loop (10) configured to lock said first optical frequency to a resonance frequency of said two-photon transition, said fluorescence signal (110) being input into the first control loop (10); - a mitigation laser source (2) configured to emit a mitigation signal (102) comprising a second optical frequency selected to produce a light-shift of said two-photon transition of opposite sign of the light-shift produced by the interrogation signal (101); characterized in that the optical frequency generation system (100) further comprises: - optical amplitude modulation means (5) configured to modulate the amplitude of the interrogation signal (101) and of the mitigation signal (102) at a second modulation frequency f2, and - a second control loop (20) configured to adjust the relative amplitude of the mitigation signal (102) with respect to the interrogation signal (101) such as to cancel the effective light-shift of the combined interrogation (101) and mitigation (102) signals.

The invention discloses a system reference clock frequency accuracy automatic calibration circuit and a calibration method thereof, and belongs to the technical field of frequency sources, the calibration circuit comprises a first crystal oscillator, a first power divider, a second power divider, a second crystal oscillator, an analog switch, a radio frequency switch, a detector, a comparator, an FPGA controller, a digital analog converter, an operational amplifier and a temperature sensor. When an external high-precision reference clock is accessed, the FPGA controller automatically switches a frequency measurement reference, performs high-precision frequency measurement on a 100MHz signal output by the first crystal oscillator, and judges whether calibration is needed or not according to frequency offset; if calibration is needed, the output voltage of the digital-to-analog converter is adjusted, the Vc end of the first crystal oscillator is controlled after operational amplification, and frequency closed-loop adjustment is achieved. According to the method, the crystal oscillator does not need to be disassembled, calibration is rapidly completed on site, and system availability and long-term frequency stability are remarkably improved.

The invention discloses a GPS oscillator taming system and method based on PID parameter adaptive adjustment, and the system comprises a forgetting factor dynamic updating module which is used for dynamically updating a forgetting factor with the variance of the frequency error of VC-TCXO as a negative index; the system identification module is used for estimating ARX model parameters of the VC-TCXO by adopting a recursive least square algorithm with the updated forgetting factor; the model parameter mapping module is used for mapping the estimated ARX model parameters to obtain PID control parameters; the incremental PID controller is used for calculating a frequency control word increment based on the frequency error; the digital-to-analog converter is used for calculating according to the frequency control word increment to obtain a frequency control word and converting the frequency control word into analog voltage; and the VC-TCXO is used for obtaining the frequency of the GPS reference signal based on the analog voltage corresponding to the frequency control word so as to complete frequency taming. The method is high in calculation efficiency and robustness, and can adapt to the dynamic change and external disturbance of the controlled object in real time.

The invention discloses a single-phase phase-locked loop system capable of intelligently adjusting parameters, and the system comprises a spectrum analysis unit which outputs a fundamental wave frequency fc, a fundamental wave angular velocity omega c, and a cascade delay signal elimination parameter ni; the self-adaptive single-phase phase-locked loop unit comprises a third-order generalized integrator, a dq converter, a cascade delay signal canceller CDSC, a PI controller, an integrator and a modulus taking device, and the cascade delay signal canceller CDSC takes a fundamental wave frequency fc as a reference frequency and takes a fundamental wave angular velocity omega c as a reference angular velocity of an input end of the integrator; an angular velocity increment delta omega output by the PI controller and a fundamental wave angular velocity omega c are added to jointly determine a phase locking angle theta, and a proportionality coefficient kp and an integral coefficient ki of the PI controller are refreshed online from the outside and take effect immediately; and the control parameter intelligent optimization unit is used for iteratively solving the optimal [kp, ki] based on a mirage search optimization algorithm MSO and writing the optimal [kp, ki] into the nonvolatile memory. According to the single-phase phase-locked loop system capable of intelligently adjusting the parameters, manual parameter adjustment is avoided, and phase locking is rapid, accurate and stable for a long time.

Compounds and compositions that have an asialoglycoprotein receptor (ASGPR) binding ligand bound to an extracellular protein binding ligand for the selective degradation of the target extracellular protein in vivo to treat disorders mediated by the extracellular protein are described.

The invention discloses a quantum phase-locked detection method based on entanglement enhancement, and the method comprises the steps: encoding quantum bits in a ground state and an excited state, and preparing the quantum bits into an initialized quantum state; loading a periodic multi-pulse sequence to act on the quantum bits; and loading a carrier pulse resonating with the ground state and the excited state, detecting the final quantum state of the quantum bit, and comparing curves of each component of the measurement density matrix and the theoretical density matrix changing along with the pulse time interval of the periodic multi-pulse sequence to obtain the half cycle and the amplitude of the sine wave to be measured. According to the method, measurement noise under the condition that the rotation angle and the detuning error exist can be effectively restrained, high measurement precision is kept under the condition that the rotation angle and the detuning error exist, and the robustness enables the method to be more reliable in practical application.

The invention relates to the technical field of atomic frequency standards, in particular to a rubidium cold atom gas chamber-based two-photon transition optical frequency standard device, which comprises a two-photon transition clock laser system, a rubidium cold atom gas chamber, a cooling laser system, a sputtering ion pump and a rubidium source, wherein the two-photon transition clock laser system comprises a laser generation modulation light path, a laser power stabilization light path and a laser frequency control light path; the rubidium cold atom gas chamber is arranged behind the Glan-Taylor prism; the cooling laser system comprises a cooling laser, a second isolator, a second polarization beam splitter, a pumping light path, a re-pumping light path and a detection light path; the sputtering ion pump is connected with the rubidium cold atom gas chamber; and the rubidium source is connected with the rubidium cold atom gas chamber. The two lasers are utilized to obtain the two-photon transition signal, so that the rubidium atom two-photon transition light frequency standard with high stability is obtained, and the intensity of the two-photon transition fluorescence signal is improved.

A clock generator includes a phase controller configured to generate phase control information in response to comparing a phase of an input clock signal against a phase of a division clock signal, and an oscillator configured to generate a plurality of oscillation signals at an equivalent output frequency but different phases, in response to the phase control information and duty control information. A duty cycle converter is provided, which is configured to generate a plurality of output clock signals at the output frequency by adjusting duty cycles of the plurality of oscillation signals, such that the plurality of output clock signals have duty cycles smaller than the duty cycles of the plurality of oscillation signals. A clock divider is provided, which is configured to generate the division clock signal by dividing the output frequency of one of the plurality of output clock signals, such that the division clock signal has a division frequency smaller than the output frequency. A duty cycle calibrator is provided, which is configured to generate the duty control information for adjusting a duty cycle difference of the plurality of output clock signals, in response to detecting duty cycle differences between the plurality of output clock signals.

The invention provides a circuit for automatically adjusting magnification times and realizing synchronous sampling, and belongs to the technical field of power electronics. The circuit comprises an amplifying circuit, a resistance switching circuit, a phase locking circuit and an acquisition circuit, the amplifying circuit is used for receiving and processing an original signal, obtaining a voltage signal and analyzing an amplification factor required by the voltage signal, and an amplifier is correspondingly connected to a resistor in the resistance switching circuit according to the required amplification factor and is used for acquiring the voltage signal. And amplifying the voltage signal according to the amplification factor, receiving the amplified voltage signal by the phase-locked loop, analyzing the amplified voltage signal to obtain an average voltage, and adjusting the output frequency of the phase-locked loop according to the average voltage to lock the phase. And the acquisition circuit is used for synchronously sampling the amplified voltage signal according to the locked phase. In an electric power system data acquisition application, the amplification factor can be automatically adjusted, phase synchronization can be realized, and signal acquisition and data analysis of different capacitive devices of a power grid can be satisfied.

The utility model provides a phase-locked loop circuit and an image sensor, and the phase-locked loop circuit comprises a phase frequency detector, a charge pump circuit, a switching circuit, an inductance capacitance voltage-controlled oscillator, an automatic frequency control circuit, and a detection control circuit. The automatic frequency control circuit controls the switching circuit to output a voltage reference signal and output a digital code signal, so that the capacitance in the inductance-capacitance voltage-controlled oscillator is changed, the frequency of an output signal of the phase-locked loop circuit is further changed, after calibration is finished, the phase frequency detector and the charge pump circuit output a changed first voltage signal, and the charge pump circuit outputs a second voltage signal. The capacitance of the inductance capacitance voltage-controlled oscillator and the frequency of an output signal of the phase-locked loop circuit are changed, and the detection control circuit outputs a closing signal to close the automatic frequency control circuit, so that additional circuit power consumption is reduced; digital code signals input by the inductance-capacitance voltage-controlled oscillator are not changed, and disturbance influence is eliminated.