1498 results about "Phase locked loop circuit" patented technology

[Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation.[Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.

A PLL circuit and a DLL circuit able to stabilize a control voltage within a short time after a phase pull-in operation in each cycle of a reference clock. In a phase comparator, the size of a leading phase or a delayed phase of a feedback signal is detected with respect to a reference clock signa, and pulse signals having pulse widths corresponding to the size are output. A current corresponding to the signals is output from a charge pump circuit to a lag-lead filter, and a control voltage obtained by removing noise of the above output is output from a low-pass filter to a voltage-controlled oscillator. Furthermore, through capacitors, pulse signals are superposed on the control voltage, and a sharp waveform is obtained by correcting blunting of the waveform by the low-pass filter. Due to this, the control voltage is stabilized within a short time after a phase pull-in operation in each cycle of the reference clock signal.

Several open-loop calibration techniques for phase-locked-loop circuits (PLL) that provide a process, temperature and divider modulus independence for the loop bandwidth and damping factor are disclosed. Two categories of open-loop techniques are presented. The first method uses only a single measurement of the output frequency from the oscillator and adjusts a single PLL loop element that performs a simultaneous calibration of both the loop bandwidth and damping factor. The output frequency is measured for a given value of the oscillator control signal and the charge-pump current is adjusted such that it cancels the process variation of the oscillator gain. The second method uses two separate and orthogonal calibration steps, both of them based on the measurement of the output frequency from the oscillator when a known excitation is applied to the open loop signal path. In the first step the loop bandwidth is calibrated by adjusting the charge-pump current based on the measurement of the forward path gain when applying a constant phase shift between the two clocks that go to the phase frequency detector, while the integral path is hold to a constant value. During the second step the damping factor is calibrated by adjusting the value of the integral loop filter capacitor based on the measurement of the oscillator output frequency when excited with a voltage proportional with the integral capacitor value, while the proportional control component is zeroed-out.

A method and apparatus for monitoring a condition having a known relation to, or influence on, the transit time of a cyclically-repeating energy wave moving through a transmission channel, by: (a) transmitting a cyclically-repeating energy wave through the transmission channel from a transmitter at one end to a receiver at the opposite end; (b) continuously changing the frequency of the transmitter according to changes in the monitored condition while maintaining the number of waves in the transmission channel as a whole integer; and (c) utilizing the changes in frequency of the transmitter to provide a continuous indication of the monitored condition. Operation (b) is preferably performed by detecting a predetermined fiducial point in each cyclically-repeating energy wave received by the receiver, but may also be performed by the use of a phase-locked loop circuit, to maintain the number of energy waves in the loop of the transmission channel as a whole integer.

A phase-locked loop (PLL) circuit includes a voltage-controlled oscillator (VCO) having a first input to receive a control voltage, one or more second inputs to receive one or more tuning range control signals, and an output to provide an oscillation output signal, a phase detector having inputs to receive the oscillation output signal and a reference signal, a charge pump having an input coupled to the output of the phase detector and having an output to generate the control voltage, a loop filter having an input to receive the control voltage and having a control terminal, and a controller having inputs to receive the control voltage, a high reference voltage, a low reference voltage, and one or more mode signals, and having a first output connected to the control terminal of the loop filter and second outputs to generate the tuning range signals.

The present invention provides a radar altimeter system with a closed loop modulation for generating more accurate radar altimeter values. The system includes an antenna, a circulator, a receiver, and a transmitter. The circulator receives or sends a radar signal from / to the antenna. The receiver receives the received radar signal via the circulator. The transmitter generates a radar signal and includes a phase-locked loop circuit for generating the radar signal based on a pre-defined phase signal. The transmitter includes a direct digital synthesizer that generates the phase signal based on a pre-defined clock signal and a control signal. The system includes a digital signal processor and a tail strike warning processor that determine position of a tail of the aircraft relative to ground and present an alert if a warning condition exists based on the determined position of the tail of the aircraft and a predefined threshold.

A phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal, a phase detector circuit coupled to receive the timing reference signal, a controllable oscillator circuit controlled according to an output of the phase detector circuit, and a feedback divider circuit having an output coupled to the phase detector and an input coupled to the controllable oscillator circuit. The phase-locked loop circuit is coupled to output one of a plurality of output signals having an arbitrary frequency relationship to each other according to a frequency selection mechanism, the frequency selection mechanism including one or more input terminals coupled to control a divide ratio of the feedback divider circuit. The frequency selection mechanism selects one of a plurality of stored values. The selected stored value controls, at least in part, a divide ratio of the feedback divider circuit, thereby providing a pin programmable device capable of selecting among output frequencies having an arbitrary relationship to each other.

A voltage controlled oscillator of a phase locked loop circuit having digitally controlled gain compensation. The digital control circuitry provides binary logic input to the voltage controlled oscillator for a digitally controlled variable resistance circuit, a digitally controlled variable current transconductor circuit, or differential transistor pairs having mirrored circuitry for adjusting the V-I gain. The latter configuration requires the voltage controlled oscillator to incorporate a source-coupled differential pair which is driven by a low pass filter capacitor output voltage, and connected to load transistors; a current source and a current mirror for generating a tail current; individual banks of transistors to mirror the load transistor currents; a digital-to-analog converter with control lines outputted there from, the digital-to-analog converter used to increase the amount of current allowed to flow to the transconductor output, the current being digitally increased and decreased corresponding to an amount of current pulled from the current source, and mirroring the current through at least one transistor mirror circuit.

A circuit and method for monitoring a frequency divider. The circuit including a phase locked loop circuit including a voltage controlled oscillator and a feedback frequency divider, an output of the voltage controlled oscillator connected to an input of the feedback frequency divider, and output of the feedback frequency divider coupled to an input of the voltage controlled oscillator; and a frequency divider monitor having a first input, a second input and an output, the first input of the frequency divider monitor connected to the output of the voltage controlled oscillator and the second input of the frequency divider monitor coupled to an output of the feedback frequency divider.