215 results about "Phase locked loop circuit" patented technology

The invention discloses a data sampling timing error evaluation method based on an evaluation model, relates to the technical field of timing error evaluation, and solves the problem that timing error evaluation is not accurate enough. Wherein the sampling module realizes undistorted receiving and clock signal frequency output of a clock signal through a CMOS clock input circuit, a third-order digital phase-locked loop circuit and a DSP digital signal processing chip, and a Fourier phase difference algorithm removes harmonic interference to solve a phase difference between the clock signal and an ideal clock signal; the clock signal feature recognition unit adopts a convolutional neural network to carry out iterative training on a training set of the timing error evaluation module to obtain an error evaluation module, the error evaluation module and the time migration algorithm module realize accurate calculation of a timing error value, and the timing error value calculation accuracy is greatly improved.

An apparatus includes a phase-locked loop (PLL) circuit and a logic circuit. The logic circuit may manage, via one or more programmable operating parameters of the PLL circuit, PLL bandwidth variation exhibited by the PLL circuit due to variations in its manufacturing process (P), supply voltage (V) or temperature (T), i.e., PVT variations exhibited by the PLL circuit.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

The invention provides a design method and system of a high-speed RC clock system. The system comprises a high-speed RC oscillator, a reference clock module, a clock calibration module, a trigger module and a state machine module. The method comprises the following steps of: controlling a calibration process through a state machine module, counting a high-frequency clock signal by taking a theoretical count value as a reference after a clock calibration module is triggered, judging whether the frequency has deviation or not and the direction of the deviation according to a counting result, performing stepping adjustment on a calibration value, and performing frequency adjustment on a high-speed RC oscillator. And circularly executing the calibration step until the counting result falls into an allowable error range. A phase-locked loop circuit does not need to be additionally arranged, high and low temperature calibration in the production stage does not need to be introduced, the chip design complexity, the manufacturing cost and the production test cost can be effectively reduced, meanwhile, high precision and stability of clock signals are ensured, and output of a low-cost, high-frequency and high-precision RC clock is achieved.

The utility model provides a phase-locked loop circuit and an image sensor, and the phase-locked loop circuit comprises a phase frequency detector, a charge pump circuit, a switching circuit, an inductance capacitance voltage-controlled oscillator, an automatic frequency control circuit, and a detection control circuit. The automatic frequency control circuit controls the switching circuit to output a voltage reference signal and output a digital code signal, so that the capacitance in the inductance-capacitance voltage-controlled oscillator is changed, the frequency of an output signal of the phase-locked loop circuit is further changed, after calibration is finished, the phase frequency detector and the charge pump circuit output a changed first voltage signal, and the charge pump circuit outputs a second voltage signal. The capacitance of the inductance capacitance voltage-controlled oscillator and the frequency of an output signal of the phase-locked loop circuit are changed, and the detection control circuit outputs a closing signal to close the automatic frequency control circuit, so that additional circuit power consumption is reduced; digital code signals input by the inductance-capacitance voltage-controlled oscillator are not changed, and disturbance influence is eliminated.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

A clock circuit, a receiver, and a passive optical communication network system are disclosed. The clock circuit is applied to a receiver in a passive optical communication network and is configured to adjust the clock frequency of an output clock signal based on a transmission protocol, the clock circuit comprises at least one clock path and a frequency divider, and the at least one clock path comprises a first clock path; wherein the first clock path receives a reference clock signal from the first phase-locked loop circuit and a control signal from the clock data recovery circuit, and interpolates a conversion signal of the reference clock signal by using the reference clock signal so as to output a multi-phase clock signal; and the frequency divider receives the multi-phase clock signal and performs frequency division on the multi-phase clock signal based on a preset frequency division value, and the preset frequency division value is determined based on a transmission protocol. The clock circuit can be compatible with fast clock switching schemes of data rates of different PON protocols, so that the adaptability and the locking performance of a receiver in a burst mode are improved.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

The embodiment of the invention discloses a phase discriminator circuit, a phase-locked loop circuit and a memory. The phase discriminator circuit comprises a phase discriminator unit which is connected with a first input path and a second input path; the first input path is used for inputting a reference clock signal to the phase discriminator unit; the second input path is used for inputting a feedback clock signal to the phase discriminator unit; the control unit is connected with the second input path of the phase discriminator unit and used for delaying the feedback clock signal for a preset time length to obtain a delayed clock signal, and the delayed clock signal is input to the phase discriminator unit through the second input path; wherein the phase discriminator unit obtains a first phase discrimination signal based on the feedback clock signal and the reference clock signal, and obtains a second phase discrimination signal based on the delay clock signal and the reference clock signal, and the first phase discrimination signal and the second phase discrimination signal are both used for representing the sequential relationship of clock signals input by different input paths of the phase discriminator unit.

The invention discloses a phase synchronization circuit, an expanded phase-locked loop circuit and a delay phase-locked loop circuit. The phase synchronization circuit comprises a clock comparison unit, a biasing circuit, a charge pump circuit, a time / analog conversion circuit, a compensation charge pump circuit, a loop filter and a clock output unit. The clock comparison unit is connected with the clock output unit, the charge pump circuit and the time / analog conversion circuit; the biasing circuit is connected with the charge pump circuit and the time / analog conversion circuit; the time / analog conversion circuit is connected with the compensation charge pump circuit; the loop filter is connected with the charge pump circuit, the compensation charge pump circuit and the clock output unit. According to the phase synchronization circuit and the expansion structure thereof, time information can be directly converted into voltage for leakage current compensation, so that comparison action based on the voltage is not needed, and analog circuits such as an integrated operational amplifier and a voltage comparator are not needed. Therefore, it is possible to suppress an increase in the chip area of the compensation circuit and to reduce the phase error of the output clock.

A digital phase-locked loop (PLL) circuit is provided, comprising: a synchronization control module configured to generate an input characterization signal representing the periodic change of the input periodic signal relative to the base clock signal based on a base clock signal and an input periodic signal; a counting control module configured to generate a clock counting result representing the multiple relationship between the period of the input characterization signal and the period of the base clock signal based on the base clock signal and the input characterization signal; an arithmetic control module configured to generate a base clock control variable based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal, and to generate an output clock control variable based on the clock counting result; and an output control module configured to generate an output control signal based on the base clock control variable and the output clock control variable, and to generate an output clock signal based on the output control signal and the base clock signal.

The described technology provides a device including a phase locked loop (PLL) circuit, the PLL circuit including a voltage controlled oscillator (VCO) and a phase detector, and a voltage supply and transconductance cell (Gm) configured to drain a current Iout from the VCO based on a sensed voltage (Vsup_sense) input into the Gm, wherein the Gm cell is configured to generate an open_loop signal based on the Iout drain from the VCO.

Example embodiments are directed to a phase-locked loop (PLL) circuit that includes a reference current generation circuit including a PT-VAR circuit. The PT-VAR circuit generates a compensation current to compensate for process variations, temperature changes, and / or power supply voltage changes in the PLL circuit, and the reference current generation circuit outputs the compensation current as a reference current. The PLL circuit further includes a current digital-to-analog converter (DAC) circuit that converts the reference current into a control current based on a digital code, and a VCO that generates a signal based on the control current. The compensation current is a sum of a first compensation current based on PMOS and NMOS transistors and having a complementary-to-absolute temperature (CTAT) characteristic, a second compensation current based on a PMOS transistor and having a proportional-to-absolute temperature (PTAT) characteristic, and a third compensation current based on an NMOS transistor and having a PTAT characteristic.

The invention relates to the technical field of integrated circuits, and discloses a double-feedback loop spread spectrum phase-locked loop circuit. The circuit comprises a clock generation phase-locked loop and a spread spectrum signal generation loop. The clock loop generates and locks the center frequency. The spread spectrum loop adopts a time length locking principle, a fixed reference time T4 is set through a digital parameter SSR, and a feedback counter is used for measuring an output clock period to obtain a feedback time T6. The error between the T4 and the T6 is compared, the error is converted into a triangular wave modulation voltage through a charge pump and a modulation signal generator, and after superposition, a voltage-controlled oscillator is controlled to realize frequency modulation. The spread spectrum depth is directly and accurately controlled through pure digital parameters, the problems that modulation precision of a traditional scheme depends on analog gain, is limited by loop bandwidth and is complex in circuit design are solved, high-precision, programmable and stable spread spectrum clock generation is achieved, system electromagnetic interference is remarkably reduced, and the method is suitable for a high-integration-level communication chip.

The invention relates to a method, an apparatus, a controller, a system and a product for disabling a phase-locked loop circuit. The method includes determining a current of a compressor in the fuel cell system. The method also includes determining that the fuel cell system is in a purge phase in response to the current being less than a current threshold. Further, the method includes disabling a phase-locked loop circuit in the fuel cell system when the fuel cell system is in a purge phase, where the phase-locked loop circuit is configured to determine whether there is a fault in the compressor based on the current. According to the embodiment of the invention, the accuracy of judging the fault of the air compressor in the fuel cell system can be improved, the normal work of the fuel cell system is realized when the air compressor is in the purging stage, and the working efficiency of the fuel cell system is improved.

An apparatus comprising a phase locked loop circuit including: an input configured to receive an oscillating reference signal having a reference period; a current-controlled-oscillator (CCO) configured to generate an oscillating output signal based on an input signal; an error detector configured to generate one or more error signals based on a phase difference between the reference signal and one or more feedback signals wherein the feedback signals are based on the oscillating output signal; and a charge pump circuit configured to receive at least a first of the error signals, determine a voltage indicative of a duration of the first error signal during a first part of the reference period, and provide a control current to the CCO for at least a remaining part of the reference period, wherein the control current comprises at least part of the input signal to the CCO and is based on the determined voltage.

The application discloses a duty cycle tunable frequency multiplier, a phase-locked loop circuit and electronic equipment, wherein the frequency multiplier comprises an input port, a first adjusting unit, a second adjusting unit, a third adjusting unit, a first control unit, a second control unit, a third control unit and a frequency multiplication unit. The frequency multiplier performs delay processing on a reference frequency through the adjusting units, selects a target delay signal through the control units, and then multiplies the reference frequency signal to generate a frequency multiplication signal, so that the duty cycle of the output clock signal is flexibly adjusted while the frequency multiplication is realized.

A delay-locked loop circuit and a semiconductor memory device are provided. The delay-locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal and a feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and change a code value in response to the first phase difference detection signal or the second phase difference detection signal.

In a calibrated digital phase-locked-loop (DPLL) circuit, during a normal operating mode, a control value provided to a digitally controlled oscillator (DCO) is updated by a feedback circuit to keep an output clock generated by the DCO synchronized with a reference clock. The feedback circuit includes a time-to-digital converter (TDC) circuit to measure a phase difference as a time interval. In a calibration operating mode of the calibrated DPLL circuit, calibration of a resolution of a time measurement of the time interval measured by the TDC is performed in the feedback circuit while the control value provided to the DCO is kept constant. Calibrating the TDCs in each of the DPLLs in an integrated circuit (IC) to a nominal resolution in this manner improves synchronization of the clock domains. In some examples, the TDC circuit is a Vernier type circuit and calibration sets a delay difference to a nominal resolution.

A power converter 10 contains a separation computer (a first transformation unit 122 and a separator 124), a PLL circuit 142, a PLL circuit 162, a negative-sequence current amplitude command generator 168, a negative-sequence current command generator 169, and a signal generator (a current control unit 180 and a pulse generator 190). The separation computer calculates positive-sequence voltages (Vpα and Vpβ) and negative-sequence voltages (Vnα and Vnβ) from three-phase AC voltages of a power grid. The PLL circuit 142 calculates a positive-sequence phase (θp) from the positive-sequence voltages (Vpα and Vp(3)). The PLL circuit 162 calculates a negative-sequence phase (θn) and a negative-sequence voltage amplitude (Vn) from the negative-sequence voltages (Vnα and Vnβ). The negative-sequence current amplitude command generator 168 calculates a negative-sequence current amplitude command value (In) based on the negative-sequence voltage amplitude (Vn).The opposite-system current command generator 169 calculates opposite-system current command values ​​(Ina, Inb, and Inc) based on the opposite-system current amplitude command value (In) and the opposite-system phase (θn). The signal generator generates the control signal (PLS) based on a result obtained by adding (i) positive-system current command values ​​based on the positive-system phase (θp) and (ii) the opposite-system current command values ​​(Ina, Inb, and Inc).

This invention discloses a power module, comprising: a first PMIC module and a second PMIC module whose power input terminals are connected to a first power signal; and an enable input terminal of the first PMIC module and the second PMIC module connected to an external enable signal. The first PMIC module has a first power output port to a seventh power output port, its first signal output port and second signal output port connected to an external reset signal, its third signal output port for outputting fault signals of the first PMIC module and the second PMIC module, and its first signal input terminal and second signal input terminal connected to an external reset feedback signal. The second PMIC module's first power output port is connected to an external platform chip power supply terminal, its second power output port is connected to an external platform RAM module power supply terminal, its third power output port is connected to an external platform USB power supply terminal, its fourth power output port is connected to an external platform input / output port power supply terminal, and its fifth power output port is connected to an external platform phase-locked loop circuit power supply terminal.

A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.

A phase-locked loop working system includes: a pre-frequency divider, a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator, a loop frequency divider and a circuit parameter regulator. The phase frequency detector, the charge pump, the filter, the voltage-controlled oscillator and the loop frequency divider are sequentially coupled end to end to form a phase-locked loop circuit. The circuit parameter regulator is coupled to the phase-locked loop circuit and is used to adjust a filtering resistor and a filter capacitor in the filter, to control loop parameters generated by the phase-locked loop circuit to be within a preset margin range. The circuit parameter regulator is coupled to the phase-locked loop circuit and is further used to adjust a frequency-division coefficient of the pre-frequency divider and / or a frequency of the signal to be processed inputted into the pre-frequency divider.

An initial control voltage generating circuit for a voltage controlled oscillator (VCO) includes a resistor coupled between a supply voltage terminal and an output node from which the initial control voltage is output, and a transmission gate resistor coupled between the output node and a ground voltage terminal. The transmission gate resistor includes a P-channel type MOS (PMOS) transistor and an N-channel type MOS (NMOS) transistor coupled in parallel between the output node and the ground voltage terminal.

A phase conjugation circuit 100 for a retrodirective antenna system includes a phase locked loop (PLL) circuit and a signal amplifying device 102 comprising a power amplifier that produces an intermediate frequency (IF) signal by subtracting a received signal from a transmit signal. The IF signal is divided by two by frequency divider 110, the resulting signal provided as an input 103 for the phase detector 112 of the PLL circuit. A second input 105 to the phase detector is provided by mixing the transmit signal with a reference signal to produce a signal having the same phase as the transmit signal. The output of the phase detector controls a signal generator 114 for generating the transmit signal. The circuit requires fewer components in comparison with conventional phase conjugation circuits, and results in minimal loss, particularly in the transmission path. A retrodirective transceiver or array may comprise an antenna module having the phase conjugation circuit. A signal amplifying device is also provided.

The utility model discloses an SIP radio frequency surface-mounted BPSK modulator, which relates to the technical field of semiconductor radio frequency devices, and comprises a substrate and a phase-locked loop circuit arranged on the substrate, the phase-locked loop circuit is connected with a power divider and a differential buffer output unit, the power divider and the differential buffer output unit are connected with a modulation multiplier, and the modulation multiplier is connected with an SIP radio frequency surface-mounted BPSK modulator. The modulation multiplier is connected with a baseband processing unit and a first filter, the baseband processing unit is connected with a first signal input end, the first filter is connected with a switch modulation unit, the switch modulation unit is connected with a second signal input end and a second filter, and the second filter is connected with a signal output end. The device provided by the utility model has the advantages of small size, integration, multiple functions and good modulation effect.

The invention belongs to the field of large-scale application-specific integrated circuit design, and particularly relates to a phase-locked loop circuit. The phase-locked loop circuit comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider; the voltage-controlled oscillator comprises a common-source amplifier, a multi-stage delay unit and a level conversion unit; the control end of the common source amplifier serves as the input end of the voltage-controlled oscillator, and the output end of the common source amplifier is connected with the voltage end of the multi-stage delay unit. The output end of the multi-stage delay unit is connected with the input end of the level conversion unit; the output end of the level conversion unit is used as the output end of the voltage-controlled oscillator; according to the voltage-controlled oscillator, the common-source amplifier is used for controlling the multi-stage delay unit along with the change of the control voltage output by the charge pump so as to adjust the oscillation frequency, and a multi-phase clock signal is output through the level conversion unit, so that the power consumption of the phase-locked loop is reduced, and the output clock has relatively small clock jitter.

A phase-locked loop (PLL) circuit, an operating method thereof, and a sub-range control circuit are provided. The PLL circuit includes a time-to-digital converter (TDC), a loop filter, a digitally controlled oscillator (DCO), a feedback circuit, a sigma-delta modulator (SDM), and a prediction circuit. The TDC includes a phase detector and a processing circuit. The phase detector generates a charging current signal according to an input frequency signal and a feedback signal. The processing circuit limits a voltage level corresponding to the charging current signal within a certain voltage range according to a prediction signal to generate a digital output. The loop filter is coupled to the TDC to perform a low-pass filtering operation according to the digital output. The DCO generates a DCO frequency signal according to an output of the loop filter. The feedback circuit generates the feedback signal according to the DCO frequency signal. The sigma-delta modulator (SDM) generates a phase signal representing accumulated phase shift information to the prediction circuit according to information of the feedback circuit and fractional frequency information. The prediction circuit generates the prediction signal according to the phase signal.

The invention discloses a phase-locked loop chip, a frequency switching method of the phase-locked loop chip and display equipment, in the phase-locked loop chip, a control module configures a reference clock signal for a phase-locked loop circuit and generates and sends a clock switching control signal; the spread spectrum modulation circuit generates a frequency modulation step value according to the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal; and the phase-locked loop circuit performs frequency adjustment on the feedback clock signal by using the frequency modulation step value to generate an output clock signal, wherein the frequency of the output clock signal is consistent with that of the reference clock signal. Because the frequency modulation step value is determined according to the frequency division coefficient and the modulation coefficient of spread spectrum modulation, the frequency modulation step value is used for frequency adjustment, so that the lock loss abnormity can be effectively avoided, the system stability is improved, the spread spectrum modulation circuit is multiplexed, other devices do not need to be additionally arranged, the chip cost is reduced, and the power consumption is reduced. And a small-step multi-frequency frequency approximation mode is adopted, so that the frequency switching time is shortened, and the chip performance is improved.

The application discloses a kind of based on the realization method of analog-digital conversion of phase-locked loop, belong to CMOS integrated circuit technical field.The application utilizes the phase-locked loop increased in circuit, by reasonably adjusting input-output relationship, and correcting signal between voltage-controlled oscillator and phase-locked loop circuit, can guarantee the linearity of overall circuit in larger input range, with higher stability;At the same time, with the frequency divider in phase-locked loop, the pressure of subsequent counter is relieved, and a more digital circuit is obtained.The application can accurately determine the time when the output signal frequency reaches stability by checking the input signal voltage change of voltage-controlled oscillator in phase-locked loop.