1480 results about "Phase locked loop circuit" patented technology

The present invention provides a multi-band, multi-mode RFID tag that uses a single antenna structure and integrated circuit to provide asset location information at any stage of a supply chain. The unified tag design operates at multiple frequencies (or bands) using the antenna structure, for example, 125 kHz, 13.56 MHz, 915 MHz, and 2.45 GHz, and preferably operates electrostatically (at lower frequencies) and electromagnetically (ay higher frequencies). An on-chip frequency monitor in the integrated circuit automatically determines which frequency is present and derives a local clock for the tag's integrated circuit, which can vary in accordance with the frequency or which can be constant. Alternatively, a phase locked loop circuit can be used to derive a local clock signal modulated into the interrogation signal. On-chip matching and power extraction circuits derive power for the tag from the interrogation signal, which is preferably passive. Additionally, a receiver can receive data from the interrogation signal.

[Problems] To realize a reliable and stable transfer of digital data that does not require a reference clock and a handshake operation.

[Means for Solving the Problem] The present invention provides a digital data transfer method for alternately and periodically transferring first information and second information respectively in a first period and in a second period, wherein: an amount of information of the first information per unit time in the first period is greater than an amount of information of the second information per unit time in the second period; and the second information in the first period is transferred as pulse-width-modulated serial data.

A digital phase lock loop circuit including an error generation circuit for generating at least three error signals and a phase error adjustment circuit for generating at least one phase error adjustment signal from the at least three error signals. By using at least three error signals, as opposed to just one, the drift in the sampling phase of the recovered clock is easily detected and corrected to reduce burst errors and to improve loss of lock (LOL) performance.

A cycle slip detector interfaces with a phase/frequency detector (PFD), such as might be used in a phase-locked loop circuit (PLL), and indicates when cycle slips occur in the PFD. Typically, the PFD generates output control signals as a function of the phase difference between first and second input signals, with the first input signal usually serving as a reference signal against which the PLL adjusts the second input signal. The PFD provides linear phase comparison between its input signals, provided their relative phase difference does not exceed ±2π radians. If one of the two signals leads or lags the other by more than that amount, a cycle slip occurs, and the PFD responds nonlinearly. The cycle slip detector provides logic for detecting and indicating leading and lagging cycle slips as they occur in the PDF, and is typically implemented as a minimal arrangement of logic gates and flip-flops.

The present invention relates to cycle slip detectors for phase and frequency detectors (PFD) and to lock detectors for phase lock loop (PLL) circuits. The present invention provides a cycle slip detector circuit for use with a phase and frequency detector circuit having first and second signal inputs, and arranged to provide first and second PLL control signal outputs responsive to clock edges in the first and second input signals respectively; the cycle slip detector circuit comprising: means for determining a cycle slip between said input signals by determining when a delayed output signal coincides with a respective input signal.

An optical disk read signal processing system for Blu-ray disc systems to ensure stable phase-locked locked operation even with a low signal-to-noise ratio. This system changes a loop configuration of a phase lock loop circuit according to the operating state, and utilizes a FIR equalizer for phase detection. This system attains a low error rate even when the signal-to-noise ratio of an input signal is low, and avoids pulse edges with low phase detection accuracy or signal pulse streams with a high possibility of being mistakenly detected as an edge in conventional methods, and also supports diverse types of input signals.

A digital phase lock loop circuit, where under certain conditions the phase error is derived from phase comparison between a reference clock edge and the next oscillator clock edge rather than a feedback clock edge. This technique can be used to significantly reduce digital phase lock loop circuit power by disabling feedback divider and sync FF once initial frequency lock is established, provided phase jitter of digital phase lock loop circuit is low enough so that there is no cycle slip. This technique can also be used to multiply the effective reference clock frequency of digital phase lock loop circuits to increases the loop bandwidth, thus reducing the phase noise. Both the applications of this technique can be combined in some circuits.

A scalable DLL (delay locked loop) circuit that has a calibration mechanism to auto tune locking precision. The delay locked loop circuit includes a multi-phase phase locked loop circuit for generating a plurality of phase signals according to a system clock, wherein one of the phase signals is a pixel clock; a phase detector for detecting an integral phase error and a fractional phase error between a reference signal and a feedback signal according to the pixel clock; a phase selector for selecting one of the phase signals according to the fractional phase error; and a delay circuit for shifting the phase of the reference signal according to the integral phase error and the selected phase signal to generate an output signal.

A phase locked loop (PLL) circuit automatically corrects the offset of the analog (especially active type) loop filter to improve the stability and precision of the locked clock or frequency signals. In addition to the general PLL circuit configuration having active type loop filter (30), the PLL circuit also has a frequency comparing circuit (42), a DAC controller (44) and a DAC (digital-to-analog converter) (46). In an offset measurement mode, the outputs of phase error detecting circuit (12, 14) and frequency error detecting circuit (18, 20) are cut, respectively, to establish locking in offset measurement locked loop (42, 44, 45, 30, 40). In this case, offset correction code (EDs) are identified and held. In normal mode, DAC controller (44) has offset correction code (ED) input to DAC (46), and DAC (46) sends offset correction signal (EAs) to loop filter (30).

Clock data recovery (CDR) circuitry or phase locked loop (PLL) circuitry can be provided with a dynamically adjustable bandwidth. One CDR circuit or PLL circuit can be provided to support multiple systems or protocols, multiple parameter requirements for a given system or protocol, and changes in the input frequency or data rate within a given system or protocol. The parameters can include jitter (e.g., jitter tolerance, jitter transfer, jitter generation), source of dominant noise, and lock time. Control signals can be used to dynamically adjust the bandwidth of the CDR circuitry or PLL circuitry while the circuitry is processing data. The control signals can be set by a PLD, by a processor, by circuitry external to the PLD, or by user input.

The application provides a low noise fiber laser frequency combs device with controllable carrier envelope phase shift frequency. The low noise fiber laser frequency combs device with controllable carrier envelope phase shift frequency comprises an optical path structure and a circuit structure, wherein the optical path structure comprises an oscillator, an acousto-optic frequency shifter, an optical fiber amplifier, a pulse compressor, an optical fiber spread spectrum device and a coherent heterodyne beat device; and the circuit structure comprises a feed-forward circuit control phase device and a phase-locked loop circuit control repetition frequency device. The fiber laser oscillator can ensure long-time operation of a system, so that the stability of the system is superior to that of a system adopting a solid laser oscillator; through the technologies of optimizing intracavity net dispersion of the fiber oscillator, introducing an inner cavity modulator in the oscillator, adopting the feed-forward acousto-optic frequency shifter, and the like, the low noise fiber laser frequency combs device can be realized; and meanwhile, due to the application of the acousto-optic frequency shifter, the carrier envelope phase shift frequency of the optical frequency combs can be accurately regulated, so that the optical frequency combs device with precise phase position regulation and secular stability is provided for realizing applications such as optical frequency standard, attosecond science and non-linear optics.

An image display system synchronizes the display of images on a plurality of display devices. The system includes a first computer system generating a first signal representing first image data to be displayed on a first display device, a second computer system generating a second signal representing second image data to be displayed on a second display device, and means for synchronizing the first and second image data. The synchronizing means includes a phase-locked loop circuit having a digital rate controller. The digital rate controller allows programmable control of the speed of the phase-locked loop.