122 results about "Phase locked loop circuit" patented technology

The invention provides a design method and system of a high-speed RC clock system. The system comprises a high-speed RC oscillator, a reference clock module, a clock calibration module, a trigger module and a state machine module. The method comprises the following steps of: controlling a calibration process through a state machine module, counting a high-frequency clock signal by taking a theoretical count value as a reference after a clock calibration module is triggered, judging whether the frequency has deviation or not and the direction of the deviation according to a counting result, performing stepping adjustment on a calibration value, and performing frequency adjustment on a high-speed RC oscillator. And circularly executing the calibration step until the counting result falls into an allowable error range. A phase-locked loop circuit does not need to be additionally arranged, high and low temperature calibration in the production stage does not need to be introduced, the chip design complexity, the manufacturing cost and the production test cost can be effectively reduced, meanwhile, high precision and stability of clock signals are ensured, and output of a low-cost, high-frequency and high-precision RC clock is achieved.

The utility model provides a phase-locked loop circuit and an image sensor, and the phase-locked loop circuit comprises a phase frequency detector, a charge pump circuit, a switching circuit, an inductance capacitance voltage-controlled oscillator, an automatic frequency control circuit, and a detection control circuit. The automatic frequency control circuit controls the switching circuit to output a voltage reference signal and output a digital code signal, so that the capacitance in the inductance-capacitance voltage-controlled oscillator is changed, the frequency of an output signal of the phase-locked loop circuit is further changed, after calibration is finished, the phase frequency detector and the charge pump circuit output a changed first voltage signal, and the charge pump circuit outputs a second voltage signal. The capacitance of the inductance capacitance voltage-controlled oscillator and the frequency of an output signal of the phase-locked loop circuit are changed, and the detection control circuit outputs a closing signal to close the automatic frequency control circuit, so that additional circuit power consumption is reduced; digital code signals input by the inductance-capacitance voltage-controlled oscillator are not changed, and disturbance influence is eliminated.

According to an embodiment, a phased-locked loop (PLL) circuit, within a gyroscope system, generates demodulation signals. It includes a phase frequency detector receiving gyroscope output, which compares a reference signal with a feedback signal to produce an error signal. A charge pump then converts this error into a first analog control signal. A programmable clamp circuit refines this into a second analog control signal. A voltage-controlled oscillator uses the second signal to produce an output signal at a controlled frequency determined by the clamp circuit. A frequency divider sends a comparison frequency signal back to the detector, completing the loop.

Wireless circuitry may include phase-locked loop (PLL) circuitry. The PLL circuitry can include a time-to-digital converter (TDC) having a first input configured to receive a reference clock signal, a second input configured to receive a feedback clock signal, and an output at which a measured phase error is produced, a frequency divider configured to output the feedback clock signal, and a phase alignment circuit configured to output a corrected phase error that is used in adjusting the frequency divider. The phase alignment circuit can include a scaling component configured to scale the measured phase error by a phase alignment coefficient to produce a corresponding scaled phase error and a multiplexing component configured to selectively output a corrected phase error that is used in controlling a sigma delta modulator coupled to the divider.

A digital phase-locked loop (PLL) circuit is provided, comprising: a synchronization control module configured to generate an input characterization signal representing the periodic change of the input periodic signal relative to the base clock signal based on a base clock signal and an input periodic signal; a counting control module configured to generate a clock counting result representing the multiple relationship between the period of the input characterization signal and the period of the base clock signal based on the base clock signal and the input characterization signal; an arithmetic control module configured to generate a base clock control variable based on a preset multiplication factor between the frequency of the output clock signal and the frequency of the input periodic signal, and to generate an output clock control variable based on the clock counting result; and an output control module configured to generate an output control signal based on the base clock control variable and the output clock control variable, and to generate an output clock signal based on the output control signal and the base clock signal.

The invention relates to the technical field of integrated circuits, and discloses a double-feedback loop spread spectrum phase-locked loop circuit. The circuit comprises a clock generation phase-locked loop and a spread spectrum signal generation loop. The clock loop generates and locks the center frequency. The spread spectrum loop adopts a time length locking principle, a fixed reference time T4 is set through a digital parameter SSR, and a feedback counter is used for measuring an output clock period to obtain a feedback time T6. The error between the T4 and the T6 is compared, the error is converted into a triangular wave modulation voltage through a charge pump and a modulation signal generator, and after superposition, a voltage-controlled oscillator is controlled to realize frequency modulation. The spread spectrum depth is directly and accurately controlled through pure digital parameters, the problems that modulation precision of a traditional scheme depends on analog gain, is limited by loop bandwidth and is complex in circuit design are solved, high-precision, programmable and stable spread spectrum clock generation is achieved, system electromagnetic interference is remarkably reduced, and the method is suitable for a high-integration-level communication chip.

The invention relates to a method, an apparatus, a controller, a system and a product for disabling a phase-locked loop circuit. The method includes determining a current of a compressor in the fuel cell system. The method also includes determining that the fuel cell system is in a purge phase in response to the current being less than a current threshold. Further, the method includes disabling a phase-locked loop circuit in the fuel cell system when the fuel cell system is in a purge phase, where the phase-locked loop circuit is configured to determine whether there is a fault in the compressor based on the current. According to the embodiment of the invention, the accuracy of judging the fault of the air compressor in the fuel cell system can be improved, the normal work of the fuel cell system is realized when the air compressor is in the purging stage, and the working efficiency of the fuel cell system is improved.

An apparatus comprising a phase locked loop circuit including: an input configured to receive an oscillating reference signal having a reference period; a current-controlled-oscillator (CCO) configured to generate an oscillating output signal based on an input signal; an error detector configured to generate one or more error signals based on a phase difference between the reference signal and one or more feedback signals wherein the feedback signals are based on the oscillating output signal; and a charge pump circuit configured to receive at least a first of the error signals, determine a voltage indicative of a duration of the first error signal during a first part of the reference period, and provide a control current to the CCO for at least a remaining part of the reference period, wherein the control current comprises at least part of the input signal to the CCO and is based on the determined voltage.

The application discloses a duty cycle tunable frequency multiplier, a phase-locked loop circuit and electronic equipment, wherein the frequency multiplier comprises an input port, a first adjusting unit, a second adjusting unit, a third adjusting unit, a first control unit, a second control unit, a third control unit and a frequency multiplication unit. The frequency multiplier performs delay processing on a reference frequency through the adjusting units, selects a target delay signal through the control units, and then multiplies the reference frequency signal to generate a frequency multiplication signal, so that the duty cycle of the output clock signal is flexibly adjusted while the frequency multiplication is realized.

A delay-locked loop circuit and a semiconductor memory device are provided. The delay-locked loop circuit includes a phase detection and delay control circuit configured to detect a phase difference between a first internally generated clock signal and a feedback clock signal to generate a first phase difference detection signal in response to a first selection signal being activated, detect a phase difference between a second internally generated clock signal and the feedback clock signal to generate a second phase difference detection signal in response to a second selection signal being activated, and change a code value in response to the first phase difference detection signal or the second phase difference detection signal.

A power converter 10 contains a separation computer (a first transformation unit 122 and a separator 124), a PLL circuit 142, a PLL circuit 162, a negative-sequence current amplitude command generator 168, a negative-sequence current command generator 169, and a signal generator (a current control unit 180 and a pulse generator 190). The separation computer calculates positive-sequence voltages (Vpα and Vpβ) and negative-sequence voltages (Vnα and Vnβ) from three-phase AC voltages of a power grid. The PLL circuit 142 calculates a positive-sequence phase (θp) from the positive-sequence voltages (Vpα and Vp(3)). The PLL circuit 162 calculates a negative-sequence phase (θn) and a negative-sequence voltage amplitude (Vn) from the negative-sequence voltages (Vnα and Vnβ). The negative-sequence current amplitude command generator 168 calculates a negative-sequence current amplitude command value (In) based on the negative-sequence voltage amplitude (Vn).The opposite-system current command generator 169 calculates opposite-system current command values ​​(Ina, Inb, and Inc) based on the opposite-system current amplitude command value (In) and the opposite-system phase (θn). The signal generator generates the control signal (PLS) based on a result obtained by adding (i) positive-system current command values ​​based on the positive-system phase (θp) and (ii) the opposite-system current command values ​​(Ina, Inb, and Inc).

This invention discloses a power module, comprising: a first PMIC module and a second PMIC module whose power input terminals are connected to a first power signal; and an enable input terminal of the first PMIC module and the second PMIC module connected to an external enable signal. The first PMIC module has a first power output port to a seventh power output port, its first signal output port and second signal output port connected to an external reset signal, its third signal output port for outputting fault signals of the first PMIC module and the second PMIC module, and its first signal input terminal and second signal input terminal connected to an external reset feedback signal. The second PMIC module's first power output port is connected to an external platform chip power supply terminal, its second power output port is connected to an external platform RAM module power supply terminal, its third power output port is connected to an external platform USB power supply terminal, its fourth power output port is connected to an external platform input / output port power supply terminal, and its fifth power output port is connected to an external platform phase-locked loop circuit power supply terminal.

A phase-locked loop circuit includes a phase-frequency detector circuit, a time amplifier circuit, a control circuit, and a variable oscillator circuit, such as a voltage-controlled oscillator. The phase-frequency detector is configured to generate a phase error output indicating a phase difference between a reference signal and a feedback signal generated using an output signal. The time amplifier is configured to extend the phase difference to generate an extended phase error output. The variable oscillator is configured to use one or more control signals generated by the control circuit using the extended phase error to adjust a frequency of the output signal. The control circuit may generate a proportional control signal using a switched-resistor circuit that includes a pull-up resistor and a pull-down resistor. The control circuit may generate an integral control signal using a capacitive-shared-integration circuit that includes passive integrating components.

A phase-locked loop working system includes: a pre-frequency divider, a phase frequency detector, a charge pump, a filter, a voltage-controlled oscillator, a loop frequency divider and a circuit parameter regulator. The phase frequency detector, the charge pump, the filter, the voltage-controlled oscillator and the loop frequency divider are sequentially coupled end to end to form a phase-locked loop circuit. The circuit parameter regulator is coupled to the phase-locked loop circuit and is used to adjust a filtering resistor and a filter capacitor in the filter, to control loop parameters generated by the phase-locked loop circuit to be within a preset margin range. The circuit parameter regulator is coupled to the phase-locked loop circuit and is further used to adjust a frequency-division coefficient of the pre-frequency divider and / or a frequency of the signal to be processed inputted into the pre-frequency divider.

An initial control voltage generating circuit for a voltage controlled oscillator (VCO) includes a resistor coupled between a supply voltage terminal and an output node from which the initial control voltage is output, and a transmission gate resistor coupled between the output node and a ground voltage terminal. The transmission gate resistor includes a P-channel type MOS (PMOS) transistor and an N-channel type MOS (NMOS) transistor coupled in parallel between the output node and the ground voltage terminal.

The utility model discloses an SIP radio frequency surface-mounted BPSK modulator, which relates to the technical field of semiconductor radio frequency devices, and comprises a substrate and a phase-locked loop circuit arranged on the substrate, the phase-locked loop circuit is connected with a power divider and a differential buffer output unit, the power divider and the differential buffer output unit are connected with a modulation multiplier, and the modulation multiplier is connected with an SIP radio frequency surface-mounted BPSK modulator. The modulation multiplier is connected with a baseband processing unit and a first filter, the baseband processing unit is connected with a first signal input end, the first filter is connected with a switch modulation unit, the switch modulation unit is connected with a second signal input end and a second filter, and the second filter is connected with a signal output end. The device provided by the utility model has the advantages of small size, integration, multiple functions and good modulation effect.

The invention belongs to the field of large-scale application-specific integrated circuit design, and particularly relates to a phase-locked loop circuit. The phase-locked loop circuit comprises a phase frequency detector, a charge pump, a low-pass filter, a voltage-controlled oscillator and a frequency divider; the voltage-controlled oscillator comprises a common-source amplifier, a multi-stage delay unit and a level conversion unit; the control end of the common source amplifier serves as the input end of the voltage-controlled oscillator, and the output end of the common source amplifier is connected with the voltage end of the multi-stage delay unit. The output end of the multi-stage delay unit is connected with the input end of the level conversion unit; the output end of the level conversion unit is used as the output end of the voltage-controlled oscillator; according to the voltage-controlled oscillator, the common-source amplifier is used for controlling the multi-stage delay unit along with the change of the control voltage output by the charge pump so as to adjust the oscillation frequency, and a multi-phase clock signal is output through the level conversion unit, so that the power consumption of the phase-locked loop is reduced, and the output clock has relatively small clock jitter.

A phase-locked loop (PLL) circuit, an operating method thereof, and a sub-range control circuit are provided. The PLL circuit includes a time-to-digital converter (TDC), a loop filter, a digitally controlled oscillator (DCO), a feedback circuit, a sigma-delta modulator (SDM), and a prediction circuit. The TDC includes a phase detector and a processing circuit. The phase detector generates a charging current signal according to an input frequency signal and a feedback signal. The processing circuit limits a voltage level corresponding to the charging current signal within a certain voltage range according to a prediction signal to generate a digital output. The loop filter is coupled to the TDC to perform a low-pass filtering operation according to the digital output. The DCO generates a DCO frequency signal according to an output of the loop filter. The feedback circuit generates the feedback signal according to the DCO frequency signal. The sigma-delta modulator (SDM) generates a phase signal representing accumulated phase shift information to the prediction circuit according to information of the feedback circuit and fractional frequency information. The prediction circuit generates the prediction signal according to the phase signal.

The invention discloses a phase-locked loop chip, a frequency switching method of the phase-locked loop chip and display equipment, in the phase-locked loop chip, a control module configures a reference clock signal for a phase-locked loop circuit and generates and sends a clock switching control signal; the spread spectrum modulation circuit generates a frequency modulation step value according to the frequency division coefficient and the modulation coefficient under the control of the clock switching control signal; and the phase-locked loop circuit performs frequency adjustment on the feedback clock signal by using the frequency modulation step value to generate an output clock signal, wherein the frequency of the output clock signal is consistent with that of the reference clock signal. Because the frequency modulation step value is determined according to the frequency division coefficient and the modulation coefficient of spread spectrum modulation, the frequency modulation step value is used for frequency adjustment, so that the lock loss abnormity can be effectively avoided, the system stability is improved, the spread spectrum modulation circuit is multiplexed, other devices do not need to be additionally arranged, the chip cost is reduced, and the power consumption is reduced. And a small-step multi-frequency frequency approximation mode is adopted, so that the frequency switching time is shortened, and the chip performance is improved.

The utility model proposes a phase-locked loop circuit and an image sensor, the phase-locked loop circuit comprises a phase frequency detector, a charge pump circuit, a switching circuit, an inductance capacitance voltage-controlled oscillator and an automatic frequency control circuit, in a calibration mode, the automatic frequency control circuit controls the switching circuit to output a voltage reference signal, and the inductance capacitance voltage-controlled oscillator outputs the voltage reference signal. The phase-locked loop circuit changes the frequency of an output signal of the phase-locked loop circuit, compares the frequency of the output signal with a clock reference signal, outputs a correspondingly changed digital code value according to a comparison result, and the digital code value changes according to a dichotomy rule, so that the capacitance and frequency of the inductance-capacitance voltage-controlled oscillator are rapidly changed, and the calibration efficiency is improved. After calibration is finished, the phase frequency detector and the charge pump circuit output a variable first voltage signal, and the capacitance of the inductance capacitance voltage-controlled oscillator and the frequency of an output signal of the phase-locked loop circuit are changed.

The application provides a clock synchronization circuit, a chip and an electronic device, the clock synchronization circuit comprises: a first phase-locked loop circuit, a second phase-locked loop circuit and a first frequency divider; a first end of the first phase-locked loop circuit is connected with an input end; second ends of the first phase-locked loop circuit are respectively connected with a first end of the second phase-locked loop circuit and a first output end; a second end of the second phase-locked loop circuit is connected with a first end of the first frequency divider; and a second end of the first frequency divider is connected with a second output end. The clock synchronization circuit provided by the application comprises: a first phase-locked loop circuit, a second phase-locked loop circuit and a first frequency divider, can realize simultaneous output of standard Ethernet and wireless communication system homologous clock, and simplifies a clock scheme and reduces device cost.

The application provides a programmable frequency divider, a phase-locked loop circuit, a chip and an electronic device, and the programmable frequency divider comprises: a frequency division module, which comprises n frequency division unit cascades, each frequency division unit is controlled by shielding based on a respective reset signal and is controlled by frequency division based on a respective frequency division control bit and a mode input signal, so as to perform frequency division operation on a respective input clock, wherein n is a natural number greater than 1; a control module, which is connected with the frequency division control end and the reset end of each frequency division unit in the frequency division module, and is used for providing a corresponding frequency division control bit and a corresponding reset signal to each frequency division unit; and an output sampling module, which is connected with the mode output end of the second frequency division unit in the frequency division module, and samples the mode output signal of the second frequency division unit based on the input clock of the first frequency division unit to obtain a final frequency division clock. The application solves the problem that the existing programmable frequency divider cannot realize a wide frequency division range.

This invention relates to the field of circuit hardening technology, and provides a voltage-controlled oscillator (VCO) circuit and phase-locked loop (PLL) circuit that are resistant to single-event transients. Addressing the issue that traditional three-mode relaxation oscillator (VCO) circuits are unsuitable for low-voltage conditions, especially when the power supply voltage drops to around 0.8V, this invention employs six oscillation branches coupled into three large oscillation loop circuits to improve loop gain. Furthermore, by combining bias circuits, comparators, and voting circuits for each path, the problem of increasing nonlinearity is avoided. This achieves a combination of large oscillation loops, bias circuits, and a three-mode VCO architecture, resulting in a VCO circuit that maintains high-frequency stable operation under ultra-low voltage conditions such as 0.8V, thus achieving a single-event transient resistance effect, especially at low voltages of 0.8V.

The invention provides a frequency jittering clock signal generation method and device, and relates to the technical field of electronics. The method comprises the following steps: acquiring target jitter frequency parameters including a jitter frequency center frequency, a jitter frequency mode and a jitter frequency width; a modulation signal and a source clock signal are determined according to the target jitter frequency parameter, the amplitude of the modulation signal changes along with time, and the amplitude change range of the modulation signal is configured to enable the first-order sigma-delta modulator to work in an unsaturated linear response area; inputting the modulation signal to a first-order sigma-delta modulator, and under the driving of the source clock signal, performing pulse density modulation on the modulation signal by the first-order sigma-delta modulator and outputting a unit pulse density modulation code stream; and carrying out edge detection on the unit pulse density modulation code stream to generate a jittering frequency clock signal. According to the technical scheme, a complex phase-locked loop circuit is replaced by a scheme which is extremely simple in structure and is completely realized by digital logic, and the problem of balancing the integration level, the cost and the signal purity is synchronously solved.

An integrated circuit and a PLL circuit including the same are provided. An integrated circuit receiving a control voltage and converting the control voltage into an oscillator control current includes a PAR circuit outputting a compensation current compensating for at least one of process variation, power voltage variation, and temperature variation of the integrated circuit, an amplifier including a first power terminal receiving a power voltage, a second power terminal outputting an amplifier current determining a gain of the amplifier, an inverting input terminal receiving the control voltage, and a non-inverting input terminal receiving an amplifier voltage formed based on the gain of the amplifier, and an IDAC circuit converting a reference current generated based on the amplifier voltage into the oscillator control current according to an IDAC code. The PAR circuit outputs the compensation current.

The invention provides a fractional phase-locked loop circuit and a working method thereof.The circuit comprises a modulation module, a first digital time converter, a second digital time converter and a phase-locked loop module, and the modulation module is used for outputting a first control signal and a second control signal according to an input frequency control signal; the first digital time converter is used for responding to a first control signal and obtaining a first delay signal according to a reference clock signal, the second digital time converter is used for responding to the first control signal and obtaining a second delay signal according to a feedback clock signal, and the phase-locked loop module is used for responding to a second control signal and obtaining a second delay signal according to a feedback clock signal. And outputting a feedback clock signal with the same frequency as the reference clock signal according to the phase difference between the first delay signal and the second delay signal. The average delay offset of the first digital time converter and the second digital time converter in the circuit is 0, so that the noise and the power consumption of the first digital time converter and the second digital time converter are relatively low.

Various solutions for duty cycle error cancellation method and phase-locked loop (PLL) circuit are described. The PLL circuit may measure a duty cycle of a reference signal from an external oscillator by an internal clock signal to obtain a digital cycle value. The PLL circuit may shift an edge of a divided signal according to the digital cycle value to obtain a time alignment divided signal. The PLL circuit may compare the time alignment divided signal with the reference signal to generate a phase-locked signal.

Techniques are disclosed for managing clock signals during transitions between performance states (P-states) in processors. In some embodiments, an apparatus includes processor circuitry configured to operate based on an input clock signal at different input clock frequencies in different performance states. Phase-locked loop (PLL) circuitry provides the input clock signal at the different input clock frequencies. Bypass circuitry provides a bypass clock signal during different re-lock intervals in which the PLL circuitry adjusts the frequency of the input clock signal for a change from a first performance state to a second performance state. The bypass circuitry is configured to provide the bypass clock signal at a first frequency during a first re-lock interval and at a second, different frequency during a second re-lock interval. Dither circuitry may dither the bypass clock signal during the re-lock intervals, based on factors such as the origin and target performance states.

The invention provides an image data display system and method, electronic equipment and a storage medium. Wherein the display system transmits data through a serial peripheral interface (SPI) bus, the display system comprises a master device and a slave device, the master device comprises a data input circuit, a data output circuit and a serial clock circuit, the serial clock circuit comprises a phase-locked loop circuit, the slave device comprises a display device, and the master device acquires image data to be transmitted; the phase-locked loop circuit is used for increasing the original main clock frequency of the serial clock circuit; the main device carries out coding and signal enhancement processing on the image data and transmits the processed image data; the master device dynamically performs signal shaping on a master clock signal output by the serial clock circuit; and the display device performs decoding and time sequence matching on the received image data and then displays the image data. According to the method, the display effect of the image data can be improved on the basis that an existing SPI display screen is not changed or changed at low cost.