11 results about "Lock time" patented technology

The application relates to a lock-up time calibration method, device and engineering machinery, relates to the technical field of remote lock-up, and the lock-up time calibration method comprises the following steps: acquiring the current residual running time length of a target vehicle; acquiring vehicle running data; according to the vehicle running data, a predicted daily average running time length of the target vehicle is obtained; and if the current residual running time length is less than or equal to the predicted daily average running time length, a lock-up instruction is output. The lock-up time calibration method, device and engineering machinery can effectively determine the lock-up time without receiving a time message by the vehicle, and reduce the loss of all vehicle owners.

The application relates to the technical field of digital phase-locked loops, and discloses a DPLL phase meter lock-loss frequency prediction system, which is characterized in that a frequency prediction module is additionally arranged in the DPLL phase meter, historical frequency data output by the DPLL module is analyzed through a polynomial fitting, a frequency difference value at adjacent time points is calculated as an accumulation factor, and a frequency prediction value at the next time point is obtained through updating; in combination with lock-loss detection and reset control, relocking is performed with the prediction value as an initial frequency when lock-loss occurs, and the capture is reset when the accumulated lock-loss reaches a preset threshold. The method adopts polynomial fitting and fixed-point data accumulation operation, realizes fast prediction through the accumulation of the difference value of historical frequency data, solves the problem of long secondary locking time in the phase-locked technology, effectively deals with lock-loss caused by noise disturbance, and significantly improves the measurement efficiency and stability of the phase meter.

Apparatuses and related methods related to reducing lock time include pre-calibrating and storing phase-locked loop (PLL) and / or injection-locked oscillator (ILO) adaptive values during start-up, and loading the pre-calibrated values during rate changes. In an illustrative example, an integrated circuit can include a controllable frequency circuit operable at a frequency within each of a plurality of frequency bands. A data store can store an operating setting associated with each frequency in the plurality of frequency bands. A state machine can be coupled to the controllable frequency circuit and the data store, the data store configured to select a predetermined frequency band in response to an instruction signal, extract the operating setting associated with the predetermined frequency band from the data store, and apply the extracted operating setting to the controllable frequency circuit. Through pre-calibration, PLL and / or ILO lock time during rate changes in a multi-rate serializer / deserializer (SERDES) link can be advantageously reduced.

Embodiments of the present application disclose a safe locking method and device, electronic equipment and a storage medium. The method comprises: if it is determined that an input password is an incorrect password, determining the error type of the incorrect password; determining an influence factor of a locking time according to the error types of a continuous preset number of incorrect passwords and a weighting factor of each error type; and determining a target locking time according to the influence factor of the locking time and a preset standard locking time, so as to perform safe locking according to the target locking time. The technical solution can evade the risk of malicious trial and error unlocking while improving the security and user experience of the intelligent lock.

Described herein is an Event Locking System (ELS) and its associated methods for (a) cryptographically locking a given piece of information until a certain time or the occurrence of a certain event and (b) providing an attestation of both the lock time and the locked content to prove that the information has not been accessed or tampered with since the lock time. Applications for such a system abound: from sealed bids for auctions and tenders, sports betting, elections, archiving of sensitive information, securing legal documents, and so on.

The invention discloses a phase frequency detector based on capture acceleration and noise suppression dual-mode adaptive switching, and the phase frequency detector employs a duty ratio shaping module to shape a reference signal and a feedback signal, reduces the duty ratio, expands the working range of a capture acceleration mode, and facilitates the reduction of the locking time of a loop. A mode controller is used for detecting the phase difference of a reference shaping signal and a feedback shaping signal, judging a locking state and controlling a reset path to be switched between a capture acceleration mode and a noise suppression mode, a high phase discrimination blind area introduced by the noise suppression mode is eliminated, and the phase discrimination range of the phase frequency detector is expanded. Reset paths adopted by the invention are a capture acceleration path and a noise suppression path, the capture acceleration path adopts an input delay sampling technology, inherent delay of a reset signal during generation and transmission is counteracted, a phase discrimination range is effectively expanded, and a phase discrimination blind area of the phase frequency detector is reduced; the noise suppression path optimizes the time sequence of reset signal generation and expands the loop charging and discharging time.

The present application relates to motor control technology field, disclose a kind of three-phase asynchronous motor operation control management method and system, comprising the following steps: step 1, the number of encoder per revolution pulse, motor nameplate rated speed, acceleration time, coasting stop time, hot permission threshold, load shedding threshold, tripping threshold, start-stop token upper limit and expected spin direction are determined Maximum allowable acceleration time and minimum cooling lock time;Step 2, according to three-phase existence state, under-voltage state and time condition are judged to start admission;Step 3, execute pulse accumulation and spin direction comparison to generate start determination result, and deduct start-stop token number;Step 4, during operation, based on temperature detection calculation heat index, compared with each threshold, output continue to run, load shedding or shutdown instruction;Step 5, update heat index, when meeting unlocking condition, output unlocking result.The present application realizes the whole process safety management of three-phase asynchronous motor from start determination, operation regulation to shutdown unlocking.

An apparatus and related method for reducing lock time includes pre-calibrating and storing adaptive values ​​for a phase-locked loop (PLL) and / or an injection-locked oscillator (ILO) upon startup and loading the pre-calibrated values ​​upon a rate change. In an illustrative example, an integrated circuit may include a controllable frequency circuit operable at frequencies within each of a plurality of frequency bands. A data store may store operational settings associated with each frequency of the plurality of frequency bands. A state machine may be coupled to the controllable frequency circuit and the data store and configured to select a predetermined frequency band in response to a command signal, retrieve from the data store the operational settings associated with the predetermined frequency band, and apply the retrieved operational settings to the controllable frequency circuit. The pre-calibration may advantageously reduce PLL and / or ILO lock time upon a rate change in a multi-rate serializer / deserializer (SERDES) link.

Systems and methods reduce a locking time of a type-II all-digital phase-locked loop (ADPLL) circuit by performing steps that comprise receiving a reference signal having a reference frequency and setting a digitally controlled oscillator (DCO) to a target frequency greater than the reference frequency. The DCO generates an output signal that is used to generate a feedback signal. A time-to-digital converter is used to determine an initial phase difference between the reference signal and the feedback signal, and a digital initial phase compensation circuit adjusts the initial phase difference to a substantially zero phase difference to reduce the locking time of the ADPLL circuit such that the ADPLL circuit reaches a steady-state condition in ten or fewer cycles of the reference signal.

The invention provides a phase-locked loop rapid locking method and system, and the method comprises the steps: carrying out the PLL pre-locking of boundary frequency points preset in firmware, and collecting the control voltage of a voltage-controlled oscillator (VCO) after the locking of each boundary frequency point; taking the frequency of each boundary frequency point and the corresponding VCO control voltage as reference points, and writing the reference points into a preset table LUT for storage; on the basis of the reference point of the preset table LUT, calculating a preset VCO control voltage Vdac of the target frequency to be locked by a linear difference value; after the voltage of the voltage-controlled oscillator VCO is controlled to reach Vdac, PLL locking is carried out, and the control voltage Vreal of the VCO is sampled again; and writing the to-be-locked target frequency and the Vreal new into a preset table LUT, and storing the to-be-locked target frequency and the Vreal new as a new reference point. Through high-precision open-loop presetting, only fine adjustment needs to be carried out during PLL closed loop, and the locking time is greatly prolonged; meanwhile, along with the increase of the system operation time, records in the LUT are richer and richer, the preset precision is higher and higher, and the overall performance of the system is continuously optimized along with time.

The application provides a kind of delay-locked loop circuit and system device, which optimizes the situation that the DLL locking time is lengthened by the minus 1C operation in the prior art, increases one step at the beginning of the first minus 1C operation (and can further be increased after the last minus 1C operation), so that there are two update opportunities in the original first minus 1C operation, avoids the situation that the actual minus 1C operation is "first plus 1C, then minus 2C", reduces the possibility of error in the phase detection result of the phase detector, thereby avoids the situation that the minus 1C operation which should be executed once is executed multiple times due to the error in the phase detection result of the phase detector, so that the DLL circuit can be normally locked, and the normal operation of the system device is ensured. In addition, the technical scheme of the application can further increase one step after completing the last minus 1C operation, so that there are two update opportunities in the original first fine adjustment operation (such as +4F operation), further reducing the possibility of error in the phase detection result of the phase detector.