This invention relates to the field of
integrated circuit technology, specifically to a RISC-V
instruction set shift instruction implementation circuit. The circuit integrates a shift module, which consists of a left shifter, a right shifter, and a
subtractor. When an instruction is emitted from the
instruction buffer, it enters the decoding module for instruction decoding. At this time, the decoded information and operands enter the shift module. The left shifter performs a left shift instruction, and the right shifter performs a
right shift instruction. The
subtractor provides the shift distance for the left and right shifters. After the
operand operations are completed, the result is output and the instruction is committed, thus completing the instruction execution. This circuit supports all shift operation instructions included in the RISC-V
instruction set, and its timing is easily converged, allowing for higher
clock frequencies. It is particularly suitable for architecture designs that pursue high-performance CPUs.